JPH0556654A - Switching-signal generating circuit for inverter - Google Patents

Abstract

PURPOSE:To enable the usage of a normal counter circuit for a sawtooth wave data forming means, and to reduce a limitation at the time of integration as a result by forming keying signal by using an incremental sawtooth wave data and a decremental sawtooth wave data as sawtooth wave data. CONSTITUTION:A normal counter circuit 1 outputs added values from sawtooth wave output terminals 1b, 1c, 1d at every input of a clock signal ck Zero-third bit data output from the sawtooth wave output terminals 1b, 1c are input to a comparison section 4 as incremental sawtooth wave data d1. On the other hand, a third bit is inverted by a NOT circuit 20, and input to a comparison section 34 as incremental sawtooth wave data d2 having phase shift of 90 deg. to the incremental sawtooth wave data d1. The incremental sawtooth wave data d1 input to the comparison section 4 are input to one input terminal 5a of a comparator 5 while being input to a NOT circuit 7. Each bit is inverted and output as decremental sawtooth wave data e1 having phase shift at 180 deg..

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching signal generation circuit for an inverter used in a multiplex type inverter for converting DC power into AC power.

[0002]

2. Description of the Related Art Inverters for converting DC power into AC power are often used as components of frequency converters and DC transformers of industrial equipment and electronic equipment. For example, AC power obtained from a commercial power source is converted by a converter. It is designed to be converted into DC power, and this DC power is converted into AC power of an arbitrary frequency by an inverter and used for rotation control of an AC motor.

As the above-mentioned inverter, a single-phase full-bridge type or a multiplex type is selectively used according to the purpose of use. The multiplex type inverter is used when a large capacity is obtained or when output harmonics are further improved. It is preferably used for improving the control performance with an equivalent switching frequency higher than the limit of the element, for improving the efficiency, and the like.

Explaining the multiplex type inverter taking the double type as an example, this inverter is as shown in FIG.
A pair of switch members 52a, 52b, 54a, such as thyristor elements, which have two DC power supplies 51a, 51b and are connected to the positive electrodes of these DC power supplies 51a, 51b.
54b and the pair of switch members 52c, 52d, 54c, and 54d connected to the negative electrode side are controlled to open / close the DC power, and one of the switch members 52a, 52b, 52c. 5
Switch members 54a, 54b, 54c, between 2d and the other
The power applied to the load 53 provided between 54d is converted into an alternating current state. And these switch members 52a, 52b, 52c, 52d, 54a, 54
A switching signal generation circuit for an inverter is usually used to open and close the b, 54c, 54d.

Generally, an inverter switching signal generating circuit, as shown in FIG. 6, includes modulated wave data a · a which is an ideal AC waveform and triangular wave data b1 · c1 having 180 ° mutually different phases. Of the two switch members 52a, 52b, 52 based on the comparison results.
Open / close signals X1, X2, X3 for controlling the open / close of c / 52d
・ X4 is output, and as shown in FIG. 7, 90 ° with respect to the above triangular wave data b1 and c1.
The triangular wave data b2 and c2 having a phase shift of 2 and the modulated wave data a and a are compared, and the other switch member 54a
Opening / closing signal Y1 for controlling opening / closing of 54b / 54c / 54d
・ Y2, Y3 and Y4 are output.

That is, as shown in FIG. 8, a conventional inverter switching signal generating circuit has, for example, a pair of 4-bit output UP / DOWN to which a clock signal ck is input.
The open / close signals X1 and X2 are connected to the counter circuits 55a and 55b and the UP / DOWN counter circuits 55a and 55b.
・ UP / DOW having a pair of comparison portions 56a and 56b forming X3, X4, Y1, Y2, Y3, and Y4.
From the N counter circuits 55a and 55b to the comparison units 56a and 56
Triangle wave data b1 with different phases of 90 ° to b
b2 is input.

As shown in FIGS. 9 and 10, the comparators 56a and 56b are provided with comparators 57a and 57 to which the triangular wave data b1 and b2 and the modulated wave data a and a are input.
b, and comparators 58a and 58b to which the triangular wave data f1 and f2 and the modulated wave data a and a, which are inverted and shifted in phase by 180 °, are input. Then, as shown in Table 1, one comparison unit 56a in FIG.
The comparator 57a compares the triangular wave data b1 whose initial value is "0" in the decimal notation with the modulated wave data a. When the modulated wave data a is larger than the triangular wave data b1, the comparison signal c1 is latched by the latch circuit 59a. The open / close signals X1 and X2 are output from the latch circuit 59a, while the triangular wave data f1 and the modulated wave data aa, which are inverted and whose decimal value is "15" as the initial value, are output. Are compared by the comparator 58a, and when the modulated wave data a is larger than the triangular wave data f1, the comparison signal c2 is output to the latch circuit 60a and the opening / closing signals X3 and X4 are output from the latch circuit 60a. ..

Further, the other comparing section 56b of FIG. 10 compares the triangular wave data b2 and the modulated wave data a with the initial value "8" in decimal notation in which the phase is shifted by 90 ° from the triangular wave data b1. The comparator 57b makes a comparison, and when the modulated wave data a is larger than the triangular wave data b2, the comparison signal c1 is output to the latch circuit 59b and the latch circuit 5b is output.
The open / close signals Y1 and Y2 are outputted from 9b, while the comparator 5 compares the triangular wave data f2 and the modulated wave data a which are inverted and whose decimal value is "7" as an initial value.
8b for comparison, and when the modulated wave data a is larger than the triangular wave data f2, the comparison signal c2 is used for the comparison signal c2.
0b and the latch circuit 60b outputs an opening / closing signal Y3.
It is designed to output Y4.

[0009]

[Table 1]

[0010]

However, in the above-mentioned conventional inverter switching signal generating circuit, the triangular wave data b1 and b2 have a complicated UP / DOWN structure.
Since it is formed by the counter circuits 55a and 55b, there is a problem that the number of gates is increased and there is a great restriction in integration. Especially, the triangular wave data b1 ・ b
When the resolution of 2 is increased, the internal configuration of the UP / DOWN counter circuits 55a and 55b becomes more complicated, and the restriction on integration becomes remarkable.

Further, in the conventional inverter switching signal generating circuit, the phase between the triangular wave data b1 and b2 is 9
Since it is shifted by 0 °, the complicated UP / DO with the above internal configuration is used.
Two WN counter circuits 55a and 55b are used,
These two UP / DOWN counter circuits 55a and 55b
The use of is to further increase the constraints on integration.

Therefore, in the present invention, the switching signal X1
Provided is a switching signal generation circuit for an inverter which can solve the above problems by forming X2, X3, X4, Y1, Y2, Y3 and Y4 by using one normal counter having a simple internal configuration. The purpose is to

[0013]

In order to solve the above-mentioned problems, an inverter switching signal generating circuit according to the present invention is used for an inverter which cuts off DC power by opening and closing a switch member to convert it into AC power. And has the following features.

That is, the inverter switching signal generating circuit includes a plurality of comparing means for forming an opening / closing signal of the switch member based on the normal sawtooth wave data and the modulated wave data, and to each of the comparing means. And a normal counter circuit that is a sawtooth wave data forming unit that outputs normal sawtooth wave data having a predetermined phase shift. The comparing means compares the normal sawtooth wave data with the modulated wave data and outputs a normal comparison signal, and compares the inverted sawtooth wave data obtained by inverting the normal sawtooth wave data with the modulated wave data. A comparator and a NOT circuit, which is a sawtooth data comparison unit that outputs an inverted comparison signal, and the normal comparison signal and the inverted comparison signal, which are output as a latch signal while switching each other when the normal sawtooth data reaches a predetermined value. It is characterized in that it is composed of a selector circuit which is a selector unit which operates and a latch circuit which is an opening and closing signal forming unit which outputs an opening and closing signal based on the latch signal.

[0015]

According to the above structure, the switching signal generating circuit for the inverter can form the opening / closing signal by using the increasing sawtooth data and the decreasing sawtooth data which are normal sawtooth data. Therefore, since the sawtooth wave data forming means can use the normal counter circuit having a simpler circuit configuration than the UP / DOWN counter circuit, restrictions on integration are small.

Further, in this inverter switching signal generating circuit, the sawtooth wave data forming means outputs the normal sawtooth wave data having a predetermined phase shift to each comparing means. It only needs to be equipped, and the restrictions on integration are even smaller.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The following will describe one embodiment of the present invention with reference to FIGS. 1 and 4.

The switching signal generating circuit for the inverter according to the present embodiment is adapted to be used, for example, in a duplex type inverter, and as shown in FIG. 3, a normal counter circuit which is a sawtooth wave data forming means. Have one.
The normal counter circuit 1 includes a CK terminal 1a to which a clock signal ck is input and 0th to 2nd increment sawtooth wave data d.
It has a sawtooth output terminal 1b for outputting a bit, a sawtooth output terminal 1c for outputting a third bit, and a sawtooth output terminal 1d for outputting a fourth bit.
The sawtooth wave output terminal 1c outputs the increased sawtooth wave data d1 which is, for example, 4-bit normal sawtooth wave data to which the clock signal ck is added.

When outputting the increased sawtooth wave data d1 of n bits, the 0th to (n-1) th bits of the increased sawtooth wave data d are output from the sawtooth wave output terminal 1b, and the sawtooth wave output terminal 1c is output.
From the sawtooth wave output terminal 1d to the nth bit.
It is sufficient to output +1 bit.

The sawtooth wave output terminal 1b of the normal counter circuit 1 is connected to the comparator 4 which forms the opening / closing signals X1, X2, X3, and X4, and the opening / closing signals Y1 and Y1.
It is connected to the comparison section 34 forming 2.Y3.Y4. Further, the sawtooth wave output terminal 1c of the normal counter circuit 1
Is connected to the comparison unit 4 described above and is also connected to the comparison unit 34 via the NOT circuit 20. As a result, the increasing sawtooth wave data d1 is input from the normal counter circuit 1 to the comparing section 4, while the comparing section 34 has a phase of 90 ° with respect to the increasing sawtooth wave data d1.
The shifted sawtooth wave data d2 is input.

The sawtooth wave output terminal 1 of the normal counter circuit 1 is input to the comparator 4 to which the above-mentioned increased sawtooth wave data d1 is input.
d is also connected, and the latch switching signal q1 is input from the sawtooth wave output terminal 1d. On the other hand, the 2-input XOR circuit 21 is connected to the comparison section 34 to which the increased sawtooth wave data d2 is input.
A sawtooth wave output terminal 1c and a sawtooth wave output terminal 1d of the normal counter circuit 1 are connected to 1. The comparison section 34 includes a sawtooth output terminal 1c and a sawtooth output terminal 1
The latch switching signal q2, which is the exclusive logical product of the data from d by the XOR circuit 21, is input. Further, the clock signals ck and ck inverted by the NOT circuit 22 and the modulated wave data a and a that are ideal AC waveforms (see FIG. 6) are input to both the comparison units 4 and 34. ing.

The above-mentioned comparison units 4 and 34 are the same as those shown in FIGS.
As shown in FIG. 5, a sawtooth wave data comparison unit including a pair of comparators 5, 6, 35, 36 and a NOT circuit 7, 37, a selector unit including a pair of selector circuits 8, 9, 38, 39, and a pair of It comprises an open / close signal forming section including latch circuits 10, 11, 40 and 41.

That is, the comparison section 4.34 has a pair of n-bit input terminals 5a, 5b, 35a, 35b and an output terminal 5c.
.. 35c provided with the comparators 5 and 35, and the increased sawtooth wave data d1 and d2 are input to one of the input terminals 5a and 35a of the comparator 5.35, and the other input terminal 5b and 35
The modulated wave data a * a is input to b. Then, the comparators 5 and 35 are arranged so that the modulated wave data a
When a is compared with the increased sawtooth wave data d1 and d2 and it is determined that the modulated wave data aa is greater than the increased sawtooth wave data d1 and d2, the output terminals 5c and 35c output H
The comparison signals c1 and c1 which are normal comparison signals of the level are output.

Further, the comparing units 4 and 34 are the same as the above-mentioned comparator 5.
Also has comparators 6 and 36 similar to 35. This comparator 6 and 36 is a decreasing sawtooth wave data which is the inverted sawtooth wave data obtained by inverting the increasing sawtooth wave data d1 and d2 by the NOT circuit 7 and 37. The data e1 and e2 are input to one of the input terminals 6a and 36a, and the modulated wave data a and a are input to the other input terminal 6b.
・ It is designed to be input to 36b. The comparator 6.36 compares the modulated wave data a.a with the reduced sawtooth wave data e1 and e2, and the modulated wave data a.a is larger than the reduced sawtooth wave data e1 and e2. When it is determined that they exist, the output terminals 6c and 36c output the comparison signals c2 and c2, which are inverted comparison signals of H level.

Output terminal 5c.3 of the above-mentioned comparator 5.35.
5c is connected to the E terminals 8a and 38a of the selector circuits 8 and 38 and the F terminals 9b and 39b of the selector circuits 9 and 39, while the output terminals 6c and 36 of the comparators 6 and 36 are connected.
c is connected to the F terminals 8b and 38b of the selector circuits 8 and 38 and the E terminals 9a and 39a of the selector circuits 9 and 39. These selector circuits 8, 9, 38, 39
Are the E terminals 8a, 9a, 38a, 39a and F described above.
In addition to terminals 8b, 9b, 38b, 39b, E / F terminal 8d
・ 9d ・ 38d ・ 39d and G terminal 8c ・ 9c ・ 38
It has c · 39c.

The above selector circuits 8, 9, 38 and 39 will be described in detail. As shown in FIG.
9/38/39 is AND circuit of NOT circuit 14 and 2 inputs
Each of the AND circuits 12 and 13 has an E terminal 8a, 9a, 38a, 39a and an F terminal 8b, 9b.
・ 38b and 39b are connected respectively. Also, A
E / F terminals 8d, 9d, 38d, 39d are connected to the other input terminal of the ND circuit 12 via the NOT circuit 14, and the E / F terminals 8d, 9d, 38d, 39d are connected.
Is also connected to the other input terminal of the AND circuit 13. The output terminals of the AND circuits 12 and 13 are connected to the input terminals of the OR circuit 15, and the output terminal of the OR circuit 15 is the G terminal 8c, 9c, 3
It is the structure connected to 8c and 39c.

The above selector circuits 8, 9, 38, 39
As shown in FIGS. 1 and 2, when the H-level latch switching signal q is input to the E / F terminals 8d, 9d, 38d, and 39d, the signal states of the E terminals 8a, 9a, 38a, and 39a are The same latch signal g1, g2, g1, g2 is set to G
When the L-level latch switching signal q is input to the E / F terminals 8d, 9d, 38d, 39d while being output from the terminals 8c, 9c, 38c, 39c, the F terminals 8b, 9b, 38b.・ Gatch signals g1 ・ g2 ・ g1 ・ g2 which are the same as the signal state of 39b are G terminals 8c ・ 9c ・ 8
It is designed to output from c.9c.

The G terminals 8c, 9c, 38c and 39c of the above selector circuits 8, 9, 38 and 39 are connected to the latch circuit 10 respectively.
・ 11 ・ 40 ・ 41 D terminals 10a ・ 11a ・ 40a ・
41a. These latch circuits 10.1
1.40.41 depends on the CK terminals 10a, 11a, 40a, 41a to which the inverted clock signal ck is input, the signal states of the latch signals g1, g2, g1, g2, and the rising edge of the clock signal ck, ck. Q terminals 10c, 11c, 40c, 41c for switching the output states of the open / close signals X1, X3, Y1, Y3, and Q terminals 10c,
Q terminal 10d.1, which outputs open / close signals X2, X4, Y2, Y4 in the opposite phase to the output state of 11c, 40c, 41c.
It has 1d, 40d and 41d.

The operation of the inverter switching signal generating circuit having the above-described structure will be described. For convenience of explanation, the switching signal generation circuit for the inverter is
It is assumed that 4-bit increasing sawtooth wave data d1 and d2 and modulated wave data a are used.

As shown in FIG. 3, the normal counter circuit 1 outputs the added value from the sawtooth wave output terminals 1b, 1c and 1d each time the clock signal ck is input. And
The 0th to 3rd bits of data output from the sawtooth output terminals 1b and 1c are input to the comparison unit 4 as the increased sawtooth data d1, while the NOT circuit 20 inverts the 3rd bit to increase the data. The comparison unit 34 outputs the increased sawtooth wave data d2 having a phase shift of 90 ° with respect to the sawtooth wave data d1.
Will be entered in.

Increased sawtooth wave data d1 input to the comparison unit 4
Will be input to one input terminal 5a of the comparator 5 and also input to the NOT circuit 7. Then, the increased sawtooth wave data d1 input to the NOT circuit 7
Is 180 ° when each bit is inverted as shown in Table 2.
After being output as the reduced sawtooth wave data e1 having the phase shift of 1, the input is input to one input terminal 6a of the comparator 6.

[0032]

[Table 2]

The other input terminal 5b of the comparators 5 and 6
In 6b, the modulated wave data aa is input,
The comparators 5 and 6 compare the increasing and decreasing sawtooth wave data d1 and e1 input to one of the input terminals 5a and 6a with the modulated wave data a and a input to the other input terminals 5b and 6b. Then, when the modulated wave data a · a is larger than the increasing and decreasing sawtooth wave data d1 · e1, the H level comparison signals c1 · c2 are output from the output terminals 5c · 6c, while the modulated wave data a The L level comparison signal c1 when a is a value equal to or smaller than the increasing and decreasing sawtooth wave data d1 and e1
c2 will be output from the output terminals 5c and 6c.

Comparison signal c output from the above comparator 5
1 is input to the E terminal 8a of the selector circuit 8 and the F terminal 9b of the selector circuit 9, and the comparison signal c2 output from the comparator 6 is the F signal of the selector circuit 8.
It is input to the terminal 8b and the E terminal 9a of the selector circuit 9. At this time, the latch switching signal q1 of the fourth bit is input from the sawtooth wave output terminal 1d of the normal counter circuit 1 of FIG. 3 to the E / F terminals 8d and 9d of the selector circuits 8 and 9. 9 selects the E terminals 8a and 9a and the F terminals 8b and 9b according to the signal state of the latch switching signal q1.

That is, when the latch switching signal q1 is at the H level, the selector circuit 8 outputs the comparison signal c1 input to the E terminal 8a from the G terminal 8c as the latch signal g2, and the selector circuit 9 outputs the E terminal. The comparison signal c2 input to 9a is output from the G terminal 9c as the latch signal g1. On the other hand, when the latch switching signal q1 is at the L level, the selector circuit 8 outputs the comparison signal c2 input to the F terminal 8b as the latch signal g2 from the G terminal 8c, and the selector circuit 9 inputs it to the F terminal 9b. The selected comparison signal c1 is output from the G terminal 9c as the latch signal g1. As a result, the selector circuits 8 and 9
As shown in Table 2, the latch signals g1 and g2 output from the comparators 5 and 6 process the triangular wave data because the comparison signals c1 and c2 are alternately switched by switching the signal state of the latch switching signal q1. The signal state is the same as that of the signal.

Thereafter, the above-mentioned latch signals g1 and g2 are
It is input to the D terminals 10a and 11a of the latch circuits 10 and 11, so that the latch circuits 10 and 11 open and close based on the latch signals g1 and g2 and the rising edge of the inverted clock signal ck. The output states of S2, S3 and S4 will be switched.

On the other hand, as shown in FIG. 3, the comparing section 34 to which the increasing sawtooth wave data d2 having a phase shift of 90 ° with respect to the above-mentioned increasing sawtooth wave data d1 is input, is compared with that of the normal counter circuit 1. Sawtooth output terminal 1c and sawtooth output terminal 1d
The latch switching signal q2 which is the exclusive logical product of the third bit and the fourth bit from is input. Table 3 shows the relationship between the latch switching signal q2 and the increased sawtooth wave data d2.

[0038]

[Table 3]

Then, the comparing section 34 inputs the increasing sawtooth wave data d2 to the comparator 35, the inverted decreasing sawtooth wave data e2 to the comparator 36, the latch switching signal q2 and the inverted sawtooth wave data e2. Based on the clock signal ck and the modulated wave data a, the same operation as that of the above-mentioned comparison unit 4 is executed to make the triangular wave data into a signal state equivalent to the signal processed by the comparators 35 and 36 and the open / close signal. Y1
・ Y2 ・ Y3 ・ Y4 will be output.

As described above, the inverter switching signal generation circuit of this embodiment uses the increased sawtooth wave data d1 to open / close signals X1, X2, X3, X4, Y1, Y2, Y3.
Since the output state of Y4 can be controlled, it is possible to adopt the normal counter circuit 1 having a simpler circuit configuration than the conventional UP / DOWN counter circuit. Therefore, this inverter switching signal generation circuit has small restrictions when integrated.

Further, the switching signal generating circuit for the inverter of the present embodiment is 90 with respect to the increased sawtooth wave data d1.
Since the increased sawtooth wave data d2 having a phase shift of .degree. Is formed based on the increased sawtooth wave data d1, only one normal counter circuit 1 is required, and the restriction on integration is further reduced. It has become.

In the present embodiment, the comparison section 4.34
Form the decreasing sawtooth wave data e1 and e2 based on the increasing sawtooth wave data d1 and d2 output from the normal counter circuit 1, and further open / close signals X1, X2, X3, X4, Y1.
Y2, Y3, and Y4 are formed, but the present invention is not limited to this, and the comparators 4 and 34 can open and close the opening / closing signal X1 based on the reduced sawtooth wave data output from the normal counter circuit 1.・ X2 ・ X3 ・ X4 ・ Y1 ・ Y2 ・ Y3
-Y4 may be formed. However, in this case, the predetermined value needs to be the minimum value of the reduced sawtooth wave data.

Further, in this embodiment, the switching signal generating circuit for the inverter is used for the duplex type inverter, but the present invention is not limited to this, and there is a predetermined phase shift. The increased sawtooth wave data may be input to each comparison unit to be used in a multiplex type inverter.

[0044]

INDUSTRIAL APPLICABILITY As described above, the switching signal generating circuit for an inverter of the present invention is used for an inverter that cuts DC power by opening and closing the switch member to convert it into AC power. A plurality of comparing means for forming an opening / closing signal based on the normal sawtooth wave data and the modulated wave data, and sawtooth wave data forming means for outputting the normal sawtooth wave data having a predetermined phase shift to each of the comparing means. The above-mentioned comparison means outputs the normal comparison signal by comparing the normal sawtooth wave data and the modulated wave data,
The sawtooth data comparison unit that outputs the inverted comparison signal by comparing the inverted sawtooth data obtained by inverting the ordinary sawtooth data and the modulated wave data, and the ordinary comparison signal and the inverted comparison signal When the predetermined value is reached, the selector section outputs the latch signal while switching each other, and the open / close signal forming section that outputs the open / close signal based on the latch signal.

Thus, the opening / closing signal can be formed by using the increasing sawtooth wave data and the decreasing sawtooth wave data which are normal sawtooth wave data, so that a normal counter circuit having a simpler circuit configuration than the UP / DOWN counter circuit can be realized. It becomes possible to use it for the sawtooth wave data forming means, and as a result, it is possible to reduce restrictions on integration.

Further, since the sawtooth wave data forming means outputs the normal sawtooth wave data having a predetermined phase shift to each comparing means, only one normal counter circuit is required and it is integrated. It is possible to further reduce the restriction in the case.

[Brief description of drawings]

FIG. 1 is a circuit diagram of one comparison unit in an inverter switching signal generation circuit of the present invention.

FIG. 2 is a circuit diagram of the other comparison unit in the inverter switching signal generation circuit.

FIG. 3 is a circuit diagram of an inverter switching signal generation circuit.

FIG. 4 is a circuit diagram of a selector circuit.

FIG. 5 is an explanatory diagram of an inverter.

FIG. 6 is an explanatory diagram of an operating state of the inverter switching signal generation circuit.

FIG. 7 is an explanatory diagram of an operating state of a switching signal generation circuit for an inverter.

FIG. 8 is a circuit diagram of a conventional inverter switching signal generation circuit.

FIG. 9 is a circuit diagram of one comparison unit of a conventional example.

FIG. 10 is a circuit diagram of the other comparison unit of the conventional example.

[Explanation of symbols]

1 Normal Counter Circuit (Sawtooth Wave Data Forming Means) 4.34 Comparison Unit (Comparison Means) 5.35 Comparator (Sawtooth Data Comparison Unit) 6.36 Comparator (Sawtooth Data Comparison Unit) 7.37 NOT Circuit ( Sawtooth data comparison part) 8 ・ 38 Selector circuit (selector part) 9 ・ 39 Selector circuit (selector part) 10 ・ 40 Latch circuit (opening / closing signal forming part) 11 ・ 41 Latch circuit (opening / closing signal forming part) 12 AND circuit 13 AND circuit 14 NOT circuit 20 NOT circuit 21 XOR circuit 22 NOT circuit a Modulated wave data d1 and d2 Increase sawtooth wave data (normal sawtooth wave data) e1 and e2 Decrease sawtooth wave data (reverse sawtooth wave data) c1 Comparison signal (normal) Comparison signal) c2 Comparison signal (inverted comparison signal)

Claims (1)

[Claims] 1. A switching signal generation circuit for an inverter used in an inverter for shutting off DC power by opening and closing a switch member to convert it into AC power, wherein the switching signal of the switch member is normal sawtooth wave data and modulated wave data. And a sawtooth wave data forming means for outputting normal sawtooth wave data having a predetermined phase shift to each of the comparing means. A saw that compares the sawtooth wave data and the modulated wave data to output a normal comparison signal, and also compares the inverted sawtooth wave data obtained by inverting the normal sawtooth wave data with the modulated wave data and outputs an inverted comparison signal. A wave data comparison unit, and a selector unit that outputs the normal comparison signal and the inverted comparison signal as a latch signal while switching each other when the normal sawtooth data reaches a predetermined value, A switching signal generating circuit for an inverter, comprising: an opening / closing signal forming section that outputs an opening / closing signal based on the latch signal.