JPH0556030A - Data receiver - Google Patents

Abstract

PURPOSE:To generate a recovered clock signal for a receiver side quickly and stably at the start of communication, at the changeover of radio lines and at the intermittent reception in the data receiver for mobile communication. CONSTITUTION:A receiver 2 selects a desired wave from a received input signal 7 and sends an intermediate frequency signal 8 including only a signal component from a communication opposite station to a demodulator 3. The demodulator 3 detects the signal 8 to generate a reproduction data signal 9 and a recovered clock signal 10. A digital PLL circuit 4 traces the clock signal 10 to generate a stable PLL clock signal 11 with less frequency fluctuation and phase fluctuation. Furthermore, the data receiver is provided with a controller 5 controlling a time constant (count number) of the digital PLL circuit 4, and the controller 5 controls the time constant to be lower for a reception frame at the start of communication, at the changeover of radio lines and at the intermittent reception to generate the PLL clock signal 11 in a short time in following to the recovered clock signal 10. In the case of continuous communication, the time constant is set higher and the stable PLL clock signal 11 is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving device used for mobile communication.

[0002]

2. Description of the Related Art FIG. 2 shows the configuration of a conventional data receiving apparatus. In FIG. 2, the receiver 2 selects a desired wave from the received input signal 7 from the antenna 1 and sends an intermediate frequency signal 8 containing only the signal component from the communication partner station to the demodulator 3. The demodulator 3 converts the intermediate frequency signal 8 to the reproduced data signal 9
And the reproduced clock signal 10 are generated. Digital PL
The L (Phase Lock Loop) circuit 13 follows the variable reproduction clock signal 10 to stabilize the P
Generate the LL clock signal 14. The PLL clock signal 14 is required to have little frequency fluctuation and phase fluctuation.
The time constant (count number) of the digital PLL circuit 13 is P
The value is set so that the LL clock signal 14 is sufficiently stable.

As described above, also in the conventional data receiving apparatus, the data signal and the clock signal can be regenerated, and the regenerated clock signal can be stabilized.

[0004]

However, in the conventional data receiving apparatus, since the time constant (count number) of the digital PLL circuit is constant, the communication is started, the wireless line is switched during communication, and waiting for an incoming call. At the time of the intermittent reception performed on the above, it takes a long time for the PLL clock signal to follow the reproduced clock signal.

The present invention solves the above problems, and reduces the reception time by stably generating a PLL clock signal in a short time at the start of communication, at the time of switching a wireless line during communication, and at the time of intermittent reception. The purpose is to do.

[0006]

In order to achieve the above object, the present invention provides a digital PLL in a mobile communication data receiving device at the start of communication, switching of a wireless line during communication, and intermittent reception during waiting for an incoming call. It has a configuration including a controller for controlling the time constant (count number) of the circuit to be small.

[0007]

Therefore, according to the present invention, the digital PLL
By controlling the time constant (count number) of the circuit, the time constant (count number) of the digital PLL circuit is reduced at the start of communication, switching of the wireless line, and intermittent reception.
The LL clock signal is made to follow the reproduced clock signal in a short time. Further, during continuous communication, the time constant (count number) of the digital PLL circuit is increased to generate a stable PLL clock signal.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, reference numerals 1 to 6 denote functional blocks constituting the present apparatus, and reference numerals 7 to 12 denote signals and the like which are input / output of the above functional blocks.

In FIG. 1, reference numeral 1 is an antenna, and 2 is a receiver, which is connected to the antenna 1 and receives a reception input signal 7. A demodulator 3 detects the intermediate frequency signal 8 received from the receiver 2 and generates a reproduction data signal 9 and a reproduction clock signal 10. Reference numeral 4 denotes a digital PLL circuit which follows the reproduced clock signal 10 and stabilizes the PLL.
The clock signal 11 is generated. Digital PLL circuit 4
Is equipped with a variable frequency divider and a phase comparator, detects the phase difference between the reproduced clock signal 10 and the PLL clock signal 11, and changes the phase when the phase delay or phase advance is counted by a time constant (count number) times. Change the frequency division ratio once,
It operates so that the phase difference between the reproduction clock signal 10 and the PLL clock signal 11 is reduced. Here, if the time constant is increased, the frequency division ratio does not change unless the phase difference is counted a lot, so that the PLL clock signal 11 does not easily follow the reproduced clock signal 10, but becomes a stable clock signal. Further, if the time constant is made small, the frequency division ratio is changed with a small phase difference count.
Although 1 is easy to follow, it becomes an unstable clock signal. 5
Is a controller and is composed of a microcomputer and the like. The controller 5 outputs the PLL count number control signal 12 to the digital PLL according to the operating state of the data receiving device.
It is input to the circuit 4 to switch the time constant (count number) of the digital PLL circuit 4. The PLL count number control signal 12 that controls the time constant (count number) of the digital PLL circuit 4 is a comparison value of a counter that counts the phase difference detection circuit, and the microcomputer of the controller 5 or the like registers in the digital PLL circuit. It is realized by setting to. An operation unit 6 controls the data receiving device.

Next, the operation of the above embodiment will be described.
The receiver 2 selects the desired wave from the communication partner station from the received input signal 7 and sends the intermediate frequency signal 8 containing only the signal component from the communication partner station to the demodulator 3. The demodulator 3 detects the intermediate frequency signal 8 and generates a reproduction data signal 9 and a reproduction clock signal 10. The digital PLL circuit 4 follows the variable reproduction clock signal 10 and generates a stable PLL clock signal 11 with little frequency fluctuation and phase fluctuation. The controller 5 obtains a signal for starting or ending communication from the operation unit 6 and a signal for switching the wireless line or waiting for an incoming call from the reproduction data signal 9 to control the operation state of the data receiving apparatus. The controller 5 controls the time constant (count number) of the digital PLL circuit 4 to be small by the PLL count number control signal 12 under the control of the microcomputer at the start of communication, at the time of switching the wireless line, and at the time of intermittent reception while waiting for an incoming call. Thus, the PLL clock signal 11 is made to follow the reproduced clock signal 10 in a short time. During continuous communication, the time constant (count number) of the digital PLL circuit 4 is increased to generate the PLL clock signal 11 which is stable for a long time.

As described above, according to the above embodiment, the PLL
By providing the controller 5 which issues the count number control signal 12 and controls the time constant (count number) of the digital PLL circuit 4, the PLL is provided according to the operating state of the data receiving device.
The time constant for pulling the clock signal 11 into the reproduced clock signal 10 is variable, and the PLL circuit 4 can always be operated in an appropriate state.

[0012]

As is apparent from the above-described embodiment, the present invention is provided with a controller for controlling the time constant (count number) of the PLL circuit so that reproduction is performed at the start of communication and at the time of switching the wireless line during communication. Since the clock is stable in a short time, synchronization with the communication partner station can be acquired in a short time. Further, at the time of intermittent reception performed while waiting for an incoming call, the reception time required for tracking the PLL circuit other than the reception time can be shortened, and power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a data receiving device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional data receiving device.

[Explanation of symbols]

 2 receiver 3 demodulator 4 digital PLL circuit (PLL circuit) 5 controller 8 intermediate frequency signal 9 reproduction data signal 10 reproduction clock signal 11 PLL clock signal 12 PLL count number control signal

Claims (1)

[Claims] 1. A demodulator for reproducing a clock signal and a data signal from an intermediate frequency signal converted by a receiver, a PLL circuit for stabilizing the reproduced clock signal, and a time constant of the PLL circuit. A data receiving device including a controller.