JP3214629B2 - Digital cellular telephone - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial application Conventional technology (FIG. 9) Problems to be solved by the invention (FIG. 9) Means for solving the problems (FIG. 1) Function (FIG. 1) Example (1) First example ( (1) (2) Second embodiment (FIGS. 2 to 6) (3) Third embodiment (FIG. 7) (4) Other embodiments (FIG. 8) Effects of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving apparatus, and can be applied to, for example, an automobile telephone.

[0003]

2. Description of the Related Art Conventionally, in a car telephone, a line is connected in response to a call signal by monitoring a call channel assigned to each region.

That is, as shown in FIG.
In, the transmission circuit 4 and the reception circuit 6 are connected to the antenna 8 via the antenna duplexer 2, and the reception signal S1 is input to the mixer 12 via the amplification circuit 10 in the reception circuit 6.

[0005] The PLL (phase locked loop) circuit 14
The reference signal S3 output from the reference signal generation circuit 20 after receiving the output signal S2 of the voltage controlled oscillation circuit (VCO) 16 via the prescaler 18 and dividing the frequency by a predetermined frequency division ratio.
And phase comparison. Further, the PLL circuit 14 drives the voltage control type oscillation circuit 16 based on the phase comparison result, thereby outputting the output signal S2 of the voltage control type oscillation circuit 16 to the mixer 12 as a local oscillation signal. As a result, the mixer 12 converts the received signal S1 into an intermediate frequency signal S4, and then outputs the converted signal to the mixer 23 via the bandpass filter circuit (BPF) 22.

At this time, in the PLL circuit 14, the frequency division ratio is switched based on the control signal of the control circuit 24.
The receiving frequency is switched by switching the frequency division ratio of the LL circuit 14. That is, in the United States, the frequency range is 869 [MHz] to 894 [MHz].
21 call channels are allocated at intervals of [kHz], so that, for example, in the mobile telephone 1, the frequency 915 [MH]
z] to generate a local oscillation signal S2 having a frequency of 939 [MHz] and converting the received signal S1 into an intermediate frequency signal S having a frequency of 45 [MHz].
Convert to 4.

The mixer 23 receives an oscillation output of a local oscillation circuit 28 having a crystal oscillation element 26, and receives an input signal S4
Is converted to an intermediate frequency signal S5 determined by the oscillation output, and then sequentially passed through a band-pass filter circuit 30 and an intermediate frequency amplifier (IF) 32 to a frequency discrimination circuit (DET) 3.
4 is output. The frequency discrimination circuit 34 performs FM detection on the input signal S5, and outputs the detection output from a low-pass filter circuit (L
PF) 36, hysteresis characteristic comparison circuit (COM) 3
8 to a demodulation circuit (DET) 40.

[0008] The demodulation circuit 40 demodulates the data of the output signal of the comparison circuit 38 and outputs the resulting data such as a call to the control circuit 24. The control circuit 24 controls the PLL circuit 14 to set the reception signal S1 to a predetermined call channel, and then monitors the call channel based on the output data of the demodulation circuit 40. In this state, when there is a call from the base station to the own station, the control circuit 24 switches the frequency division ratio of the PLL circuit 14 in response to the call, and switches the received signal S1 of the mobile phone to the communication channel.

As a result, in the car phone 1,
An audio signal AF of the other party is obtained through a frequency discrimination circuit 34, and the audio signal AF is output to a handset through a band-pass filter circuit 42.
By transmitting an audio signal output from the handset through the transmission circuit 4, it is possible to talk with a desired communication partner.

[0010]

As described above, in the mobile telephone 1, even when the line is not connected to the communication partner, the call channel is constantly monitored and the call of the own station is awaited. Therefore, if the power consumption in such a standby state can be reduced,
It is considered that the power consumption of the entire mobile phone 1 can be significantly reduced by that amount, which is convenient.

The present invention has been made in view of the above points, and it is an object of the present invention to propose a receiving apparatus capable of remarkably reducing power consumption as compared with the related art.

[0012]

According to the present invention, in order to solve the above-mentioned problems, a digital oscillating signal is output from a digital cellular telephone 120 which is operated in a portable state by using power supplied from a mounted battery. An oscillation circuit 16 for controlling the frequency of the oscillation signal based on the signal level of the input signal; a PLL (Phase-Locked Loop) circuit 14 for outputting a phase comparison result between the local oscillation signal and a predetermined reference signal; Antenna input signal S1 based on
A frequency conversion circuit 12 for converting the signal into an intermediate frequency signal having a predetermined frequency, a frequency discrimination circuit 34 for demodulating the intermediate frequency signal and outputting a demodulated signal, and an analog signal for converting the output signal from the frequency discrimination circuit 34 into a digital signal. A digital conversion circuit 124, error correction circuits 126 and 128 for sequentially demodulating an output signal from the analog digital conversion circuit 124 and then performing error correction processing, and selectively outputs a phase comparison result and a demodulated signal to the oscillation circuit 16. The frequency of the local oscillation signal is tuned to a predetermined channel by outputting the phase comparison result as an input signal to the oscillation circuit 16 based on the processing result of the error correction processing. By outputting the demodulated signal as an input signal to the oscillation circuit 165 instead of the phase comparison result based on the result. While the selection circuit 88,103 to hold the frequency of the local oscillation signal to a state of being tuned to channel and holds the frequency of the I connexion local oscillation signal to the selected circuit 88,103 state tuned to channel, PLL
When the power supply to the circuit 14 is stopped, and thereafter, when an increase in the bit error rate of the processing result obtained by the error correction circuits 126 and 128 is detected, the power supply to the PLL circuit 14 is restarted and driven again, and the correct channel is restored. After tuning and tuning to the correct channel, a switch circuit 108 for stopping power supply to the PLL circuit 14 again is provided.

[0013]

The channel tuning state is maintained in the AFC loop based on the processing result of the error correction processing, the power supply to the PLL circuit is stopped during that time, and then the bit error rate of the processing result obtained by the error correction circuit is increased. Is detected, the power supply to the PLL circuit is restarted and re-driven,
After tuning to the correct channel and tuning to the correct channel, the power supply to the PLL circuit is stopped again, so that the state of tuning to the correct channel can be maintained even during standby, and the bit error rate does not increase and becomes stable. In this case, the power supply to the PLL circuit can be stopped, so that the power consumption can be efficiently reduced even in the standby mode, and the operating time for operating with a constant amount of power supplied from the battery can be further lengthened.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

(1) First Embodiment In FIG. 1, in which parts corresponding to those in FIG. 9 are assigned the same reference numerals, reference numeral 40 designates a receiving apparatus as a whole. For example, a predetermined channel is always provided in preparation for broadcasting for disaster prevention radio. It can be monitored.

That is, in the receiving apparatus 40, the received signal S1 is received by the mixer 41 via the antenna 8, and is multiplied by the local oscillation signal of the voltage control type oscillation circuit 42 here. As a result, the receiving device 40 converts the received signal S1 having a predetermined frequency into an intermediate frequency signal, and outputs the intermediate frequency signal to the frequency discriminator 45 via the bandpass filter circuit 43 and the intermediate frequency amplifier circuit 44.

Here, the frequency discriminator 45 detects the frequency shift of the intermediate frequency signal by using the input frequency versus output signal characteristic consisting of the S-characteristic, and performs FM detection on the intermediate frequency signal. The resulting audio signal is output to a speaker 49 via a switch circuit 46, a preamplifier 47, and a power amplifier circuit 48. Thereby, the receiving device 40
In, the frequency of the local oscillation signal is switched so that a desired channel can be monitored.

Further, in the receiving device 40, the lock detection circuit 50 detects the presence or absence of a carrier signal, thereby detecting a tuning deviation of the local transmission signal, and switching the switch circuit 46 based on the detection result.

That is, the lock detecting circuit 50 terminates the output signal of the intermediate frequency amplifying circuit 45 in a series circuit of a capacitor 51 and a resistor 52, and terminates in a parallel circuit of a resistor 54 and a capacitor 55 via a diode 53. Thereby, the lock detection circuit 50 rectifies the output signal of the intermediate frequency amplification circuit 45 and outputs a detection signal S7 whose DC level changes according to the signal level of the carrier signal.

The comparison circuit 56 obtains a comparison result between the detection signal S7 and a predetermined reference level (57). When the signal level of the carrier signal falls to a level that causes a tuning deviation, the comparison circuit 56 outputs a signal. It outputs a lock detection signal SC1 whose level falls. Lock detection circuit 5
0 is the lock detection signal S via the inverting amplifier 57.
At C1, the switch circuit 46 is controlled to be turned on and off, whereby when the signal level of the carrier signal falls, the output of the audio signal is controlled to be stopped. When the broadcast is stopped, noise is not output through the speaker 49.

Further, the lock detection circuit 50 controls the switch circuits 58, 59, and 60 by using the lock detection signal SC1 to stop and control the operation of the PLL circuit 61, whereby the disaster prevention radio channel is controlled. For example, when power is monitored, the entire power consumption can be reduced. That is, the PLL circuit 61 divides the local oscillation signal of the voltage-controlled oscillation circuit 42 by a predetermined frequency division ratio, and obtains a phase comparison result with a predetermined reference signal. Then, the result of the phase comparison is fed back to the voltage control type oscillation circuit 42. As a result, in the receiving apparatus 40, the frequency of the local oscillation signal can be switched by switching the frequency division ratio of the PLL circuit 61, and a desired channel can be selected.

The switch circuit 59 receives the lock detection signal SC1 via the inverting amplifier circuit 63, and switches to the ON state when the signal level of the carrier signal falls. On the other hand, the frequency discrimination circuit 45
Terminates the FM detection signal in a series circuit of a resistor 64 and a capacitor 65, smoothes the FM detection signal by this, and outputs the signal to a switch circuit 58 via an amplification circuit 66.

The switch circuit 58 outputs a lock detection signal SC.
1 is switched directly to the OFF state when the signal level of the carrier signal falls, and the ON / OFF state is complementarily switched with the switch circuit 59 in accordance with the signal level of the carrier signal. As a result, in the receiving apparatus 40, when the signal level of the carrier signal falls, the switch circuit 59 is turned on, the switch circuit 58 is turned off, and the PLL circuit 61 is turned off.
The oscillation frequency of the voltage control type oscillation circuit 42 is controlled based on the result of the phase comparison.

Therefore, in the receiving apparatus 40, when a tuning error occurs, when a channel being received stops broadcasting, the frequency division ratio of the PLL circuit 61 is adjusted to select a desired channel. it can.

On the other hand, when the signal level of the carrier signal rises, the switch circuit 59 is turned off and the switch circuit 58 is turned on, and the oscillation frequency of the voltage control type oscillation circuit 42 is controlled based on the FM detection signal. I do. As a result, in the receiving device 40, when the signal level of the carrier signal rises, the voltage-controlled oscillation circuit 42 utilizes the S-characteristic of the input signal of the frequency discrimination circuit 45 versus the output signal.
Can control the oscillation frequency of the AFC
(automatic frequency control) A loop is formed so that the channel once tuned can be continuously received.

In this state, if the local oscillation frequency fluctuates beyond the pull-in range of the AFC loop, in the receiving device 40, the tuning is lost and the signal level of the lock detection signal SC1 falls, so that the PLL circuit 61 Can control the oscillation frequency of the voltage-controlled oscillation circuit 42, so that even if the tuning is lost, it is possible to quickly tune to the original channel. Thus, in the receiving device 40, once tuning to a desired channel is performed, the tuning state is maintained using an AFC loop.

Further, in this embodiment, the receiving device 40
Is maintaining tune using the AFC loop,
The power supply of the PLL circuit 61 is controlled to be stopped, thereby reducing the overall power consumption. That is, in the receiving device 40, the inverting amplifier circuit 63 terminates the output signal in a series circuit of the resistor 67 and the capacitor 68, and connects both ends of the resistor 67 with the diode 69.

As a result, in the receiver 40, when the signal level of the lock detection signal SC1 rises, the terminal voltage of the capacitor 68 falls with a delay, and conversely, when the signal level of the lock detection signal SC1 falls. ,
The terminal voltage rises rapidly following the lock detection signal SC1.

The switch circuit 60 switches the on / off state based on the terminal voltage of the capacitor 68. When the terminal voltage rises, the drive power supply 70 is switched to the PL.
It is supplied to the L circuit 61. Thus, in the receiving device 40, once locked to a desired channel, the local oscillation frequency can be controlled by the AFC loop, and the power supply of the PLL circuit 61 can be controlled to stop, so that the overall power consumption can be reduced.

In the above configuration, the received signal input via the antenna 8 is converted into an intermediate frequency signal by the mixer 41, and then is passed through the band pass filter circuit 43 and the intermediate frequency amplifier circuit 44 to the frequency discriminating circuit 45. , And the resulting audio signal is output from the speaker 49. In this state, the signal level of the output signal of the intermediate frequency amplifying circuit 44 is detected by the lock detecting circuit 50. When the signal is out of synchronization, when the broadcast of the receiving channel is stopped, the signal level falls. The signal SC1 is obtained, and the switch circuit 46 is turned on / off based on the signal level of the lock detection signal SC1.

In this way, in the receiving device 40, when synchronization is lost or when the broadcasting of the channel being received is stopped, the output of the audio signal is controlled to be stopped, so that damage to the speaker and the like can be effectively avoided. The local oscillation signal of the voltage-controlled oscillation circuit 42 is frequency-divided by the PLL circuit 61, and a phase comparison result with a predetermined reference signal is obtained. The phase comparison result is input to the switch circuit 59. On the other hand, the output signal of the frequency discrimination circuit 45 is smoothed,
The signal is input to the switch circuit 58 via the amplifier circuit 66.

In this state, at the time of the channel selection operation or after the tuning is deviated, the switch circuits 58 and 59 are set to the off state and the on state, respectively, based on the lock detection signal SC1. The oscillation frequency of the voltage-controlled oscillation circuit 42 is controlled on the basis of the voltage, and the receiving apparatus 40 can tune to a desired channel using the PLL circuit 61.

On the other hand, once tuned, the lock detection signal SC1 rises, and the switch circuit 58
And 59 are switched to the ON state and the OFF state, respectively, and the output signal of the amplifier circuit 66 is output to the voltage controlled oscillation circuit 42 instead of the phase comparison result. As a result, in the receiving device 40, an AFC loop is formed as a whole to control the oscillation frequency of the voltage-controlled oscillation circuit 42. By switching the switch circuit 60 to the off state after a predetermined time delay, By stopping and controlling the operation of the PLL circuit 61, power consumption can be reduced.

According to the above configuration, the local oscillation frequency is controlled by the phase comparison result of the PLL circuit when the tuning is deviated, etc., and once the tuning is performed, the output of the frequency discriminating circuit is replaced by the phase comparison result. By controlling the local oscillation frequency based on the signal, the operation of the PLL circuit can be controlled to stop after tuning once, thereby reducing the overall power consumption.

(2) Second Embodiment In FIG. 2, in which parts corresponding to those in FIG. 9 are assigned the same reference numerals, reference numeral 80 denotes an AMPS (advanced mobile phone) as a whole.
service), the signal level detection circuit 8
In step 1, the signal level of the carrier signal is detected.

That is, the signal level detection circuit 81 detects the signal level of the carrier signal by rectifying and smoothing the intermediate frequency signal, and outputs the detection result to the analog digital conversion circuit (A / D) 82. As a result, in the control circuit 83, a central processing unit built in is used, based on the output signal of the analog / digital conversion circuit 82 as shown in FIG.
By executing the processing procedure shown in (1), after a desired call channel is selected, a call is awaited.

That is, the control circuit 83 executes step SP1.
From step SP2, where the frequency division ratio of the PLL circuit is switched to receive the frequency assigned to the calling channel. Here, the control circuit 83 outputs control data to the frequency dividing circuit (N) 84 and switches the frequency dividing ratio of the frequency dividing circuit 84 to thereby control the voltage controlled oscillation circuit 1.
The frequency of the local oscillation signal output from 6 is switched.

That is, in the automobile telephone 80, the oscillation output of the crystal oscillator (OSC) 85 is divided by the frequency divider (M) 8
After the frequency division by 6, the phase comparison circuit (PH) 87 compares the phase with the output signal of the frequency division circuit 84. In addition, car phone 80
In the above, the phase comparison result of the phase comparison circuit 87 is output to the voltage control type oscillation circuit 16 via a switch circuit 88, a resistor 89, and an amplification circuit 90 having a low-pass filter circuit configuration. Is made up.

Thus, in the mobile telephone 80, after setting the receiving frequency to a predetermined calling channel, the signal level of the calling channel is detected via the analog digital conversion circuit 82.

That is, the control circuit 83 proceeds to step SP3, fetches the output data of the analog-to-digital conversion circuit 82 in the calling channel, and then proceeds to step SP4.

Here, the control circuit 83 operates for all calling channels assigned to the car telephone system.
It is determined whether the detection of the signal level has been completed. In this case, a negative result is obtained, and the process returns to step SP2.
Thus, in the control circuit 83, step SP2-S
Repeat the loop LOOP1 of P3-SP4-SP2,
The frequency of the local oscillation signal is switched in units of 30 [kHz], and the signal level is sequentially detected in each calling channel.

On the other hand, when signal level detection is completed for all 21 calling channels assigned to the car telephone system, a positive result is obtained in step SP4, and the control circuit 83 executes step SP4.
Then, based on the signal level detection result, the receiving frequency is switched to the paging channel having the strongest signal level.

Subsequently, the control circuit 83 proceeds to step SP6 and monitors the call channel for a predetermined period.
Detects the presence or absence of word sync. In other words, in this type of mobile telephone system, 44
A word sync is transmitted in a [msec] cycle (FIG. 5 (A)), so that it can be determined whether a correct call channel has been received or a mere carrier leak or the like has been received depending on the presence or absence of the word sync. It has been done.

As shown in FIG. 4, in the control circuit 83, the output signal CD of the comparison circuit 38 is received by a PLL circuit (PLL) 92, where a clock signal CK is extracted. Further, the PLL is controlled based on the clock signal CK.
After the input signal CD of the circuit 92 is latched by the latch circuit (L) 93, the output data of the latch circuit 93 is output to the word sync detection circuit 94.

The word sync detection circuit 94 receives the output data of the latch circuit 93 in the 11-stage shift register 95, and compares each bit of the register circuit 96 storing the word sync data with each bit of the shift register 95. The comparison is performed by the circuit 97. As a result, the word sync detection circuit 94 obtains a comparison result in which the signal level rises when the word sync WS is fetched into the shift register 95. In the control circuit 83, when the correct call channel is received, 44 A comparison result S (FIG. 5B) in which the signal level rises in [msec] cycle can be obtained.

In the control circuit 83, the comparison result S
To the monostable multivibrator (MM) 98 so that it is receiving the correct call channel,
A call channel detection signal SK (FIG. 5C) whose signal level continuously rises is obtained, and the call channel detection signal SK is input to a central processing unit (CPU) 99. Thus, the control circuit 83 determines whether or not the central processing unit 99 has received a correct calling channel. If a negative result is obtained here, the process proceeds to step SP7.

Here, the control circuit 83 subsequently switches the frequency of the local oscillation signal to a calling channel having a large signal level, returns to step SP6, and detects the word sync again. Thus, in the control circuit 83, after the loop LOOP1 is repeated, the steps SP6-SP7
By repeating the loop LOOP2 of -SP8, the paging call channels are sequentially received in descending order of the signal level, and the correct paging channel assigned to the destination zone is detected.

If an affirmative result is obtained in step SP6, the control circuit 83 proceeds to step SP8 and stops displaying the indicator indicating that the call cannot be made. That is, in the car phone 80, the resistance 101
And a light emitting diode 100 connected in series to control circuit 83
In the control circuit 83, the terminal voltage of the light emitting diode 100 is lowered to turn on the light emitting diode 100, thereby displaying a state in which communication is impossible.

When the light emitting diode 100 is turned off, the control circuit 83 proceeds to step SP9 to switch the car phone 80 to the AFC operation.
That is, in the mobile phone 80, the frequency discrimination circuit 3
4 is supplied to the amplifier circuit 90 via the switch circuit 103 and the resistor 114, thereby setting the switch circuits 88 and 103 to the ON state and the OFF state, respectively. While the frequency of the local oscillation signal can be maintained at a predetermined frequency on the basis of the above, when the switch circuits 88 and 103 are set to the off state and the on state, an AFC loop is formed to maintain the frequency of the local oscillation signal at the predetermined frequency. Have been made to gain.

In the switching operation, the control circuit 83 delays the calling channel detection signal SK by the delay circuit (DL) 104, and then outputs the detection signal SK to the switch circuit 88 via the gate circuit 105.
By outputting the output signal of the gate circuit 105 to the switch circuit 103 via the inverting amplifier circuit 106, when the local oscillation signal is tuned to the correct calling channel, the AF signal is output.
A C loop is formed to maintain the tuning state of the local oscillation signal.

After switching to the AFC operation, the control circuit 83 proceeds to step SP10, where the operation of the PLL circuit is stopped and controlled. That is, in the control circuit 83, the output signal of the inverting amplifier circuit 106 is
The output signal SK of the delay circuit 107
On / off control of the switch circuit 108 is performed based on (3).
The switch circuit 108 includes the prescaler 18 and the frequency divider 8
4, 86, the oscillation circuit 85 and the phase comparison circuit 87
C is supplied. As a result, in the mobile phone 80, after forming the AFC loop,
The operation of the LL circuit is stopped and controlled, so that the power consumption is reduced accordingly.

Subsequently, the control circuit 83 proceeds to step SP11.
Then, based on the output data of the demodulation circuit 40, the call data DT (FIG. 5) following the word sync WS is monitored, thereby detecting the presence or absence of a call of the own station. If a negative result is obtained here, the control circuit 83 proceeds to step SP12, and determines whether or not the word sync WS has been detected based on the calling channel detection signal SK. Return to SP11.
Thus, once tuned to the correct calling channel, the car phone 80 will maintain the tuned state in the AFC loop until there is a call for itself, and until it becomes difficult to detect the word sync WS. ing.

In practice, in this type of car telephone,
Due to the high receiving frequency, it is necessary to configure the prescaler 18 and the like with an emitter coupling logic circuit (ECL),
There is a feature that the power consumption of the PLL circuit is correspondingly large. Further, the mobile phone itself has a feature that the waiting time for waiting for a call is long. Therefore, as in this embodiment, if the operation is switched to the AFC loop in the standby state after tuning and the operation of the PLL circuit is controlled to be stopped, the power consumption can be significantly reduced as compared with the conventional case. it can.

On the other hand, for example, if the car equipped with the car phone 80 moves and cannot receive the correct calling channel, it cannot detect the word sync WS, so that a negative result is obtained in step SP12. Return to step SP2. As a result, when the control circuit 83 becomes unable to receive its own call, it repeats the loop LOOP1 again, and then returns to step S.
The loop LOOP2 is repeated via P5 to receive the correct calling channel for the destination zone.

At this time, when the calling channel detection signal SK falls, the control circuit 83 turns on the light emitting diode 100 and outputs the switching signal SK4 to the gate circuit 105, whereby the switch circuit 8
8, 103 and 108 are switched to immediately start the operation of the PLL circuit. Thus, once the control circuit 83 cannot receive the call of the own station, the control circuit 83 immediately searches for the calling channel, thereby shortening the state of not receiving the call of the own station. I have.

On the other hand, when the control circuit 83 detects the call of the own station, the control circuit 83 proceeds to step SP13, executes the line connection processing, and then proceeds to step SP14 to end the processing procedure. Here, the control circuit 83 executes the processing procedure shown in FIG. 6 to execute the line connection processing.

That is, when the control circuit 83 receives the call of its own station, it proceeds from step SP15 to step SP1.
The process proceeds to step 6, where a switching signal SK4 is output. Thus, in the control circuit 83, after the operation of the PLL circuit is started, the process proceeds to step SP17, in which the frequency division ratio of the frequency division circuit 84 is sequentially switched to scan the access channel.

At this time, in the control circuit 83, an analog digital conversion circuit 82 is provided for each access channel.
After detecting the signal level of each access channel, the process proceeds to step SP18 to receive the access channel having the strongest signal level. In this state, the control circuit 83 detects the presence / absence of the word sync WS, and selects and receives a correct access channel based on the detection result.

Subsequently, the control circuit 83 proceeds to step SP19, drives the transmission circuit 4 to send out a page response, and then proceeds to step SP20 to wait for the data of the initial voice channel. In this state, when the data of the initial voice channel is received, the control circuit 83 proceeds to step SP21, switches the receiving frequency to the initial voice channel, and then proceeds to step SP22.

Here, the control circuit 83 waits for an alert message in the initial voice channel, and when an alert message is received, the control circuit 83 proceeds to step SP2.
Go to step 3 and sound the tone ringer, then go to step SP2
Then, it is determined whether or not the transmission button has been turned on (step 4). If a negative result is obtained here, the control circuit 83 returns to step SP23 and continues to sound the tone ringer, whereas if a positive result is obtained in step SP24, the process proceeds to step SP25 to cancel the mute.

As a result, in the control circuit 83,
Once the call of the own station is detected, PL is replaced with AFC loop.
After the operation of the L circuit is started and the mobile phone 80 is set in a state in which communication is possible, the process proceeds to step SP26 to end the processing procedure.

According to the configuration shown in FIG. 2, after the frequency of the local oscillation signal is tuned to the calling channel by using the PLL circuit, the frequency of the local oscillation signal is maintained by using the AFC loop, so that in the standby state, The operation of the PLL circuit can be stopped and controlled, and the power consumption in the standby state can be reduced accordingly.

(3) Third Embodiment In FIG. 7, reference numeral 120 denotes a digital cellular phone as a whole, which receives a message in response to a call from the own station.

That is, in the digital cellular 120, the received signal S1 is converted into a first intermediate frequency signal by the mixer 12, and then converted into a second intermediate frequency signal by the mixer 23.
Further, the digital cellular 120 amplifies the second intermediate frequency signal by the intermediate frequency amplifying circuit 32,
4 demodulates.

At this time, in the digital cellular 120, the output signal of the intermediate frequency
After the detection at 1, the differential amplified signal with the output of the predetermined reference power supply 123 is fed back to the intermediate frequency amplifier circuit 32 via the differential amplifier circuit 122, thereby forming an AGC circuit as a whole. , The signal level of the received signal S1 is corrected.

The analog-to-digital conversion circuit 124 extracts a clock signal from the output signal of the frequency discrimination circuit 34, and converts the output signal into a digital signal based on the clock signal. The equalizer 125 performs a predetermined arithmetic operation on the output data of the analog-to-digital conversion circuit 124 between adjacent data, thereby performing an equalization process on the output data. Demodulate the data.

An error detection and correction circuit (ECC) 128 sequentially takes in the output data of the data demodulation circuit 126 and executes an error correction process. This allows the digital cellular 120
In this case, based on the output data of the error detection and correction circuit 127, a response is made to a call of the own station, and a message transmitted subsequently is taken in and displayed on a predetermined display panel.

Further, the error detection / correction circuit 128 switches the switching signals SK1, SK2,
SK3, thereby outputting the switch circuits 88, 10
3, 108 is switched to reduce the power consumption in the standby state.

That is, in the digital cellular 120, when the bit error rate is reduced by the error detection and correction circuit 128 in synchronization with a predetermined calling channel, the switch circuits 88 and 103 are switched to the ON state and the OFF state, respectively. 108 is turned off. Thereby, in the digital cellular 120,
The tuning state is maintained in the AFC loop, and the operation of the PLL circuit 14 is stopped to reduce power consumption. If the bit error rate increases in this state, the digital cellular 120 switches the switch circuit 108 to the ON state,
The switch circuits 88 and 103 are switched to the off state and the on state, respectively, thereby driving the PLL circuit 14 to select the correct call channel.

According to the configuration of FIG. 7, even if the AFC loop and the PLL circuit are switched based on the error detection and correction result, the operation of the PLL circuit can be stopped and controlled in the standby state, and the power consumption in the standby state can be controlled. Can be reduced.

(4) Other Embodiments In the above-described embodiment, the AF is performed based on the signal level of the carrier signal, the detection result of the word sync, and the error detection and correction result.
Although the case where the C loop and the PLL circuit are switched has been described, the present invention is not limited to this, and the switching may be performed based on the output signal of the frequency discrimination circuit.

That is, as shown in FIG. 8, a high-pass filter circuit (HPF) 141 receives an output signal of the frequency discrimination circuit 34 via a capacitor 140, and extracts a high-frequency noise component. That is, in the frequency modulation method, for example, when the tuning is deviated and the signal level of the target signal falls below the limit of improvement, triangular noise is mixed into the demodulated signal.

Based on this principle of noise generation, the lock detection circuit shown in FIG.
1 is amplified by the amplifier circuit 142, detected by the diode 143, the capacitor 144, and the resistor 145, and the detected output is compared with a predetermined reference voltage (146) by the comparator circuit 14.
Compare with 7. As a result, in the lock detection circuit, a detection result in which the signal level falls when it becomes difficult to receive the target signal can be obtained via the comparison circuit 147, and the AFC loop and the PLL circuit are switched based on the detection result. Thus, power consumption of the PLL circuit can be reduced.

Further, in the above-described embodiment, the case where the present invention is applied to an AMPS type car phone or the like has been described. The present invention can be widely applied to various receiving devices such as mobile phones and pagers.

[0075]

As described above, according to the present invention, the channel tuning state is maintained in the AFC loop based on the processing result of the error correction processing, the power supply to the PLL circuit during that time is stopped, and then the error correction circuit is turned off. When the increase in the bit error rate of the processing result obtained by the above is detected, the power supply to the PLL circuit is restarted and re-driven, the correct channel is selected, and after tuning to the correct channel, the PLL is again performed.
By stopping the power supply to the circuit, it is possible to always maintain the state of tuning to the correct channel even during standby, and to stop the power supply to the PLL circuit when the bit error rate is stable without increasing. Even in standby mode, power consumption can be reduced efficiently and the operating time with a fixed amount of power supplied from the battery can be further increased, thus dramatically reducing power consumption with a simple configuration A digital cellular telephone that can be used.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a receiving apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a car telephone according to a second embodiment.

FIG. 3 is a flowchart for explaining the operation.

FIG. 4 is a block diagram showing a configuration of a control circuit.

FIG. 5 is a signal waveform diagram for explaining the operation.

FIG. 6 is a flowchart for explaining the operation of a line connection process;

FIG. 7 is a block diagram showing a digital cellular according to a third embodiment.

FIG. 8 is a block diagram showing another embodiment.

FIG. 9 is a block diagram showing a conventional car telephone.

[Explanation of symbols]

1,80 ... car phone, 14,61 ... PLL circuit,
16, 42: a voltage-controlled oscillation circuit; 24, 83: a control circuit; 34, 45 ... a frequency discrimination circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-57-57048 (JP, A) JP-A-1-256234 (JP, A) JP-A-62-97436 (JP, A) JP-A-1 101029 (JP, A) Japanese Utility Model Showa 57-74545 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04B 1/16-1/26 H03J ⁷ /00-7/18 H04Q 7/38

Claims (1)

(57) [Claims] 1. A digital cellular telephone which operates in a portable state by using power supplied from a mounted battery, outputs a local oscillation signal, and controls the frequency of the local oscillation signal based on the signal level of the input signal. An oscillation circuit, a PLL (Phase-Locked Loop) circuit for outputting a phase comparison result between the local oscillation signal and a predetermined reference signal, and converting an antenna input signal to an intermediate frequency signal of a predetermined frequency based on the local oscillation signal A frequency conversion circuit that demodulates the intermediate frequency signal and outputs a demodulated signal; an analog-to-digital conversion circuit that converts an output signal from the frequency discrimination circuit into a digital signal; and an analog-to-digital conversion circuit. An error correction circuit for sequentially performing error correction processing after demodulating the output signal of The frequency of the local oscillation signal is output by selectively outputting a tuning signal to the oscillation circuit, and outputting the phase comparison result as the input signal to the oscillation circuit based on the processing result of the error correction processing. After tuning to a predetermined channel, the frequency of the local oscillation signal is output to the oscillation circuit by outputting the demodulated signal to the oscillation circuit as the input signal instead of the phase comparison result based on the processing result of the error correction processing. A selection circuit for maintaining the frequency of the local oscillation signal in a state tuned to the channel by the selection circuit;
Stop the power supply to the L circuit and then correct the error
Bit error rate of the above processing result obtained by the circuit
Power supply to the PLL circuit when an increase in
Restart the feed and restart, select the correct channel above
And a switch circuit for stopping power supply to the PLL circuit after tuning to the correct channel .