JPH0556016A - Frame synchronization time division multiplex communication system - Google Patents

Abstract

PURPOSE:To switch a channel structure even when a fault takes place in a transmission line by selecting the polarity of a frame pattern, taking synchronization respectively at a reception side and selecting a channel structure from a storage content. CONSTITUTION:When data representing a channel structure of a time division multiplexer section 5 and the channel structure of a time division demultiplexer section 6 of the same channel structure are transmitted as that are stored in memories 1, 3, the multiplexer section 5 multiplexes the terminal data of channels 1-n based on the channel structure stored in the memory 1 at a transmission side, a noninverting frame pattern and the data multiplexed by the section 5 are multiplexed by a time division multiplex section 12 without polarity inversion of the frame pattern at a polarity control means 7 and the multiplexed pattern and the data are sent to a transmission line. Since only a frame synchronization detection section 8 at a reception side detects the synchronization, a selective means 10 selects the memory 3 based on the output of the detection section 8, a demultiplexer section 6 demultiplexes the multiplexed data based on the data representing the channel structure stored in the memory 3 to implement the communication according to the channel structure stored in the memories 1, 3, and even when a fault takes place, the channel structure is switched.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a frame pattern,
Since the polarity reversal pattern does not match the non-polarity reversal pattern, the configuration of the time division multiplexing unit on the transmission side and the time division demultiplexing unit on the reception side can be configured without constructing a line for supervisory control between stations.
The present invention relates to an improvement of a frame synchronization time division multiplex communication system that can be changed to two types.

In recent years, in a frame-synchronous time division multiplex communication system, in order to diversify transmission media and efficiently use a transmission line, a CH structure of a time division multiplexing unit on a transmitting side and a time division demultiplexing unit on a receiving side is used. The CH configuration is changed so that, for example, there are many telephone CHs in the daytime, the telephone CHs are 10CH, and the data CHs are 2CH, and at night, there are many data CHs, the data CHs are 10CH, and the telephone CHs are 2CH. ..

In order to change the CH configuration, there is also a method of constructing a line for supervisory control between stations and using this line, but since the multiplexing efficiency deteriorates, the line for supervisory control It is desired to provide a frame-synchronous time division multiplex communication system capable of changing the CH configurations of the time division multiplexing unit on the transmission side and the time division demultiplexing unit on the reception side without providing the above.

[0004]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional frame synchronous time division multiplex communication system. In FIG. 3, data from channels (hereinafter referred to as CH) 1 to CHn are multiplexed by the time division multiplexing unit 5 and input to the multiplexing unit 12, and in the multiplexing unit 12, the frame pattern generation unit 11 generates the data. The frame pattern whose polarity inversion pattern does not match the non-polarity inversion pattern is further multiplexed, and the multiplexed data is transmitted to the receiving side via the transmission line 14.

On the receiving side, when the frame synchronization detector 8 detects the synchronization by the frame pattern, the reception timing generator 13 'generates a clock and supplies it to the time division separator 6 and a flip-flop (hereinafter referred to as FF). The time division separation unit 6 separates the data into CH1 to CHn.

In FIG. 3, in order to change the CH configuration of the time division multiplexer 5 on the transmission side 5 and the time division demultiplexer 6 on the reception side, 2
Data of different types of CH configurations are stored in the address control memories (hereinafter referred to as ACMs) 1 and 3 on the transmission side, and data of two types of CH configurations having the same configuration as the transmission side are stored on the ACM2 and ACM2 on the reception side. Remember in 4.

[0007] Normally, the CH configuration of the time division multiplexing unit 5 and the time division demultiplexing unit 6 communicates with the CH configuration of the data stored in the ACMs 1 and 2, and the data stored in the ACMs 3 and 4 are communicated. In the case of the CH configuration, the transmission side changes the CH configuration of the time division multiplexing unit 5 by designating the ACM 3 with a signal from a control unit (not shown), and sets the switch 17 to a specific pattern. While the specific pattern from the generation unit 18 is being sent to the transmission line 14, the transmission line 1 is switched to the dotted line side.
4 to the receiving side.

On the receiving side, when the specific pattern detecting section 16 detects a specific pattern, the detection signal is input to the FF 19, the output 0 is set to 1, the ACM 4 is designated, and the CH configuration of the time division separating section 6 is set to ACM 4. It is arranged to switch to the CH configuration of the data stored in.

The ACMs 1, 3, 2 and 4 have the same RAM.
Since the address space is divided into two and logically separate ACMs are configured, the selection signal is a signal indicating another address than the address line of the RAM.

[0010]

However, when the transmission line 14 transmits a specific pattern during a failure, the time division multiplexing unit 5 on the transmission side has a CH configuration based on the ACM 3, but the reception side does not. The problem is that the CH structure is different due to ACM2 and the CH structure is different, which causes a discrepancy in communication when the failure is recovered, and normal data cannot be transmitted while sending a specific pattern, and CH switching for changing the CH structure. Delay and the specific pattern generating unit 18, the switch 17
Also, there is a problem that the circuit size becomes large because the specific pattern detection unit 16 and the FF 19 must be provided.

According to the present invention, the circuit scale is small and fast, and even if there is a failure in the transmission line, the CH configuration of the time division multiplexing unit and the time division demultiplexing unit can be switched without causing a communication failure. It is intended to provide a division multiplex communication system.

[0012]

FIG. 1 is a block diagram showing the principle of the present invention. As shown in FIG. 1, the frame pattern is
The polarity reversal pattern does not match the non-polarity reversal pattern, and the transmission side has a first time division multiplexing unit 5 for multiplexing the data and the data multiplexed by the first time division multiplexing unit 5. Further, it has a second time division multiplexer 12 for multiplexing the frame pattern, and data showing different CH configurations of the first time division multiplexer 5 and the reception side time division demultiplexer 6. The first and third memories 1, which respectively store
3, the second and fourth memories 2 and 4, and the CH configuration of the first time division multiplexing unit 5 and the reception side time division demultiplexing unit 6 is the first and second memories 1 and 2. In the frame-synchronous time division multiplex communication system in which the configuration of the data stored in the third and fourth memories 3 and 4 is switched to the configuration of the data stored in First, third
The polarity control means 7 capable of selectively inverting and non-inverting the polarity of the frame pattern is provided in relation to which of the CH configurations stored in the memories 1 and 3 of FIG. A first frame synchronization detection unit 8 that detects synchronization by a pattern, a second frame synchronization detection unit 9 that detects synchronization by an inverted frame pattern, and the first and second frame synchronization detection units 9.
The CH configuration of the time division separation unit 6 is changed to the CH configuration stored in any of the second and fourth memories 2 and 4 depending on which of the frame synchronization detection units 8 and 9 has detected the synchronization. The configuration is such that selection means 10 for selecting whether or not is provided.

[0013]

According to the present invention, the CH configuration of the time division multiplexing unit 5 and the CH configuration of the time division demultiplexing unit 6 having the same CH configuration are stored in the first and third memories 1 and 3. When communicating as data, the transmitting side selects the first memory 1 of the first and second memories 1 and 2, and time division multiplexing is performed by the CH configuration stored in the first memory 1. CH in part 5
The terminal data of 1 to CHn are multiplexed, the polarity control means 7 does not invert the polarity of the frame pattern, and the non-inverted frame pattern and the data multiplexed by the multiplexing unit 5 are subjected to the second time division. The data is multiplexed by the multiplexing unit 12 and sent to the transmission path.

Then, on the receiving side, the synchronization is detected only by the first frame synchronization detecting section 8 which detects the non-inverted frame pattern, and therefore the output thereof selects the selecting means 10.
The third memory 3 side is selected by, and the time-division demultiplexing unit 6 demultiplexes the multiplexed data like the data indicating the CH configuration stored in the third memory 3. Communication can be performed with the CH configuration stored in the memories 1 and 3 of 3.

Here, when communication is performed by switching the CH configuration like the data of the same CH configuration stored in the second and fourth memories 2 and 4, on the transmission side, the first and second memories 1 are connected. , 2 of the second memory 2 is selected, and the CH configuration stored in the second memory 2 causes the time division multiplexing unit 5 to CH
At the same time that the terminal data of 1 to CHn are multiplexed, the polarity control means 7 inverts the frame pattern, and the inverted frame pattern and the data multiplexed by the multiplexing unit 5 are combined in the second time division multiplexing unit. It is multiplexed at 12 and sent to the transmission line.

On the receiving side, since the synchronization is detected only by the second frame synchronization detecting section 9 which detects the inverted frame pattern, the output of the second frame synchronization detecting section 9 selects the fourth memory 4 side and the fourth memory 4 side is selected. By demultiplexing the multiplexed data in the time division demultiplexing unit 6 like the data indicating the CH configuration stored in the memory 4 of the above, the CH configuration stored in the second and fourth memories 2 and 4 is obtained. Communication can be performed.

Thereafter, the first and second memories 1 and 3 are again provided.
When switching to the CH configuration stored in the above, or vice versa, switching can be performed only by the operation of the transmitting side by repeating the above operation.

In this way, either the non-inverted or inverted frame pattern is constantly transmitted from the transmitting side, and the receiving side determines whether the non-inverted or inverted frame pattern is detected on the receiving side. In order to switch the third and fourth memories 3 and 4 storing the data indicating the CH configuration,
There is no delay in switching.

Further, when the transmission path has a failure, even if the transmission side switches to a CH configuration opposite to that before the failure occurrence during the failure of the transmission path, after the failure recovery, the reception side has the polarity of the received frame pattern. According to the above, the CH configurations are switched, and in a normal state of the transmission path, the CH configurations of the transmitting side and the receiving side are always the same, and there is no trouble in communication.

Further, for example, a polarity control means 7 such as an exclusive OR circuit is provided, and on the receiving side, for example, a knot circuit for inverting the received data and a frame synchronization detecting section having the same configuration as the frame synchronization detecting section 8 normally used. Since the frame synchronization detector 9 and the selection unit 10 composed of, for example, an FF may be provided, the circuit scale can be made smaller than the conventional one.

[0021]

2 is a block diagram of a frame synchronization time division multiplex communication system according to an embodiment of the present invention.

2 is different from the conventional example shown in FIG. 3 in that the transmitting side is provided with an exclusive OR circuit 7 instead of the specific pattern generating section 18 and the switch 14, and the receiving side is provided with the specific pattern detecting section 16 , FF19, instead of the knot circuit 9-1, the frame synchronization detection section 9-2 and the FF10 having the same configuration as the frame synchronization detection section 8, a different point will be mainly described below.

For example, a control unit (not shown) outputs 0
Is input and the ACM1 side is selected, the time division multiplexing unit 5 is like the data of the CH configuration stored in the ACM1.
The frame pattern in which the polarity inversion pattern does not match the non-polarity inversion pattern is not inverted by the exclusive OR circuit 7,
It is multiplexed with the output of the time division multiplexing unit 5 in the multiplexing unit 12 and sent to the receiving side via the transmission line 14.

On the receiving side, the frame synchronization detector 8 detects synchronization and outputs 1, so that the output of the FF 10 is 1.
The CM2 side is selected, and the time division demultiplexing unit 6 uses the CH of the time division multiplexing unit 5 as the CH configuration data stored in the ACM2.
It has the same structure.

In order to switch the CH configurations of the time division multiplexing unit 5 and the time division demultiplexing unit 6 like the data that works for the ACM2 and ACM4, when the signal of 1 is input from the control unit, the ACM3 side is selected on the transmission side. Then, the time division multiplexing unit 5 becomes like the data of the CH configuration stored in the ACM 3, and the frame pattern from the frame pattern generation unit 11 is inverted by the exclusive OR circuit 7 and is then multiplexed by the multiplexing unit 12. It is multiplexed with the output of the time division multiplexing unit 5 and sent to the receiving side via the multiplexing 14.

On the receiving side, the frame sync detector 9-2 detects the sync from the data inverted by the knot circuit 9-1, and outputs 1 so that the output of the FF 10 is 0 and the ACM is ACM.
4 side is selected, and the time division demultiplexing unit 6 switches like the data of the CH configuration stored in the ACM 4, and the same as the CH configuration of the time division multiplexing unit 5.

Again, the time division multiplexing unit 5, the time division demultiplexing unit 6
When a signal of 0 is input from the control unit to switch the CH configuration of ACM1 to the data stored in ACM1 and ACM3, the operation opposite to the above is performed, and the ACM1 side is selected on the transmission side and at the same time the non-inverted frame pattern is selected. Is transmitted, and the ACM 3 is selected by detecting a non-inverted frame pattern on the receiving side.

When the frame synchronization detectors 8 and 9-2 detect synchronization, the reception timing generator 13 outputs a clock and supplies it to the time division separator 6. That is, when the transmission line has a failure, even if the CH configuration of the time division multiplexing unit 5 is switched to the CH configuration opposite to the CH configuration before the occurrence of the failure on the transmitting side during the failure, the failure recovery is performed on the receiving side. At the same time, since frame synchronization can be achieved with a frame pattern having a polarity opposite to that of the frame pattern before the occurrence of a failure, the CH configuration of the time division demultiplexing unit 6 can be immediately made the same as the CH configuration of the time division multiplexing unit 5 on the transmission side. It is possible, and there is no discrepancy in communication.

Further, since the CH configuration is switched when the synchronization by the inverted frame pattern is detected, the switching is not delayed and the transmitting side is provided with the polarity control means 7 such as an exclusive OR circuit and the receiving side receives the signal. For example, a knot circuit that inverts data and a frame synchronization detection unit 9 including a frame synchronization detection unit having the same configuration as the frame synchronization detection unit 8 that is normally used, and a selection unit 1 configured by, for example, an FF
Since 0 may be provided, the circuit scale can be made smaller than that of the conventional one.

The time division multiplexing unit 5 and the time division demultiplexing unit 6 have a CH structure stored in the ACMs 2 and 4,
When switching to the CH configuration stored in Nos. 1 and 3, the same operation is performed except that the frame pattern is switched from the inverted one to the non-inverted one.

Furthermore, for example, if the CH configuration shown by ACMs 3 and 4 includes the CH of the supervisory control line, AC
When the M3, 4 side is selected, remote control of the opposite station can be performed and the setting contents of the ACMs 2, 4 can be changed.

[0032]

As described in detail above, according to the present invention, the circuit scale is small and fast, and even if there is a failure in the transmission line, the time division multiplexing unit and the time division demultiplexing unit are not affected by communication. There is an effect that the CH configuration can be switched.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention,

FIG. 2 is a block diagram of a frame synchronization time division multiplex communication system according to an embodiment of the present invention,

FIG. 3 is a block diagram of a conventional frame synchronization time division multiplex communication system.

[Explanation of symbols]

1 to 4 are a memory, an address control memory, 5 is a time division multiplexing unit, 6 is a time division demultiplexing unit, 7 is a polarity control means,
Exclusive OR circuit, 8, 9, 9-1 is a frame synchronization detection unit, 9-1 is a knot circuit, 10 is a selection means, a flip-flop, 11 is a frame pattern generation unit, 12 is a multiplexing unit, 13, 13 'Is a reception timing generation unit, 14 is a transmission line, 16 is a specific pattern detection unit, 17 is a switch, 18
Is a specific pattern generator, and 19 is a flip-flop.

Claims (1)

[Claims] 1. The frame pattern is such that the polarity reversal pattern does not match the non-polarity reversal pattern, and the transmission side has a first time division multiplexing unit (5) for multiplexing with data and the first time division multiplexing unit. A second time division multiplexing unit (12) for further multiplexing the frame pattern on the data multiplexed by the multiplexing unit (5), and the first time division multiplexing unit (5) and First, third memories (1, 3), second, fourth memories (2, 4) storing data indicating different channel configurations of the time division separation unit (6) on the receiving side, respectively. Have
The channel configurations of the first time division multiplexer (5) and the time division demultiplexer (6) on the receiving side are set to the first and second memories (1,
In the frame-synchronous time division multiplex communication system in which the structure configured like the data stored in 2) is switched to the structure stored in the third and fourth memories (3, 4). Is a polarity control means (7) capable of selectively inverting and non-inverting the polarity of the frame pattern in relation to which of the channel configurations stored in the first and third memories (1, 3). On the receiving side, a first frame synchronization detection unit (8) for detecting synchronization with a non-inverted frame pattern and a second frame synchronization detection unit (9) for detecting synchronization with an inverted frame pattern. ) And the first and second frame synchronization detectors (8,
9) in which the synchronization is detected, the channel configuration of the time division demultiplexing unit (6) is set to the second and fourth memories (2, 4).
A frame synchronization time division multiplex communication system, characterized in that a selection means (10) for selecting in which of 4) the channel configuration to be stored is provided.