JPH0555302A - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JPH0555302A JPH0555302A JP3213789A JP21378991A JPH0555302A JP H0555302 A JPH0555302 A JP H0555302A JP 3213789 A JP3213789 A JP 3213789A JP 21378991 A JP21378991 A JP 21378991A JP H0555302 A JPH0555302 A JP H0555302A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- substrate
- semiconductor package
- support wall
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、基板に形成したバンプ
とＩＣチップの入出力部を接触させた半導体パッケージ
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package in which bumps formed on a substrate are brought into contact with input / output portions of an IC chip.
【０００２】[0002]
【従来の技術】この種の半導体パッケージは、図４に示
す構成が一般的である。図において、1 は基板で、ポリ
イミドのような耐熱樹脂を基材とし、配線回路1aを形成
するとともにこれに電気的に接続される端子ピン1bを設
けている。2 はバンプで、基板1 の配線回路1a上に多数
形成されている。3 はＩＣチップで、シリコンを基材と
し、露設された多数の入出力部 (図示せず) を有する。
4 は接着樹脂層で、粘性の低い封止剤として多用される
樹脂にて、バンプ2 とＩＣチップ3 の入出力部を接触さ
せるようＩＣチップ3 と基板1 を接着固定する。5 はキ
ャップで、ＩＣチップ3 を保護すべく基板1 に接着固定
されている。バンプ2 とＩＣチップ3 の入出力部の接触
は、接着樹脂層4 の硬化収縮力によっている。またバン
プ2 とＩＣチップ3 の入出力部を接触させる手段として
は、これらを熱圧着させる形式もある。2. Description of the Related Art This type of semiconductor package generally has a structure shown in FIG. In the figure, 1 is a substrate, which is made of a heat-resistant resin such as polyimide as a base material, forms a wiring circuit 1a, and is provided with terminal pins 1b electrically connected thereto. A plurality of bumps 2 are formed on the wiring circuit 1a of the substrate 1. An IC chip 3 is made of silicon as a base material and has a large number of exposed input / output parts (not shown).
An adhesive resin layer 4 is a resin that is often used as a low-viscosity encapsulant and adhesively fixes the IC chip 3 and the substrate 1 so that the bumps 2 and the input / output portions of the IC chip 3 come into contact with each other. Reference numeral 5 denotes a cap, which is adhesively fixed to the substrate 1 so as to protect the IC chip 3. The contact between the bump 2 and the input / output portion of the IC chip 3 depends on the curing shrinkage force of the adhesive resin layer 4. Further, as a means for bringing the bump 2 and the input / output portion of the IC chip 3 into contact with each other, there is a type in which they are thermocompression bonded.
【０００３】[0003]
【発明が解決しようとする課題】前述したような半導体
パッケージにあっては、接着樹脂を用いた接着工程や熱
圧着工程といった高度で面倒な製造技術が必要である。The semiconductor package as described above requires an advanced and troublesome manufacturing technique such as a bonding process using an adhesive resin and a thermocompression bonding process.
【０００４】本発明は、かかる事由に鑑みてなしたもの
で、その目的とするところは、接着樹脂を用いた接着工
程や熱圧着工程を不要にしてバンプとＩＣチップを接触
させる工程が簡易化できる半導体パッケージの提供にあ
る。The present invention has been made in view of the above circumstances, and an object of the present invention is to simplify the step of bringing the bump and the IC chip into contact with each other without the need for a bonding step using an adhesive resin or a thermocompression bonding step. To provide a semiconductor package that can be manufactured.
【０００５】[0005]
【課題を解決するための手段】かかる課題を解決するた
めに、本発明の半導体パッケージは、配線回路を形成す
るとともにこれに電気的に接続される端子ピンを設けた
基板と、基板の配線回路上に形成された多数のバンプ
と、露設された多数の入出力部を有するＩＣチップと、
ＩＣチップを保護すべく基板に接着固定されたキャップ
と、を有してバンプとＩＣチップの入出力部を接触させ
た半導体パッケージにおいて、前記基板に、ＩＣチップ
が一定量沈んだ状態で嵌合する支持壁を設け、しかも支
持壁の内面にＩＣチップの装着を可能にする程度に変形
しかつＩＣチップが装着された状態では一定の押圧力で
もってＩＣチップを押圧する低弾性率材料の複数の突起
を設けた構成としてある。In order to solve the above-mentioned problems, a semiconductor package of the present invention is a semiconductor package in which a wiring circuit is formed and a terminal pin electrically connected thereto is provided, and a wiring circuit of the substrate. An IC chip having a large number of bumps formed thereon and a large number of exposed input / output parts;
In a semiconductor package in which a bump and an input / output portion of the IC chip are in contact with each other, the cap being adhered and fixed to the substrate to protect the IC chip, the IC chip is fitted to the substrate with a certain amount of depression. A plurality of low-modulus materials that are provided with a supporting wall that is deformed to the extent that the IC chip can be mounted on the inner surface of the supporting wall and that presses the IC chip with a constant pressing force when the IC chip is mounted. The projection is provided.
【０００６】[0006]
【作用】この構成によれば、ＩＣチップはそれを支持壁
の突起を変形させながら押し込むだけで基板に装着で
き、しかもＩＣチップが基板に装着された状態では突起
が今度は一定の押圧力でもってＩＣチップを押圧してバ
ンプとＩＣチップの確実な接触状態を維持する。According to this structure, the IC chip can be mounted on the substrate only by pushing it in while deforming the protrusion of the support wall. Moreover, when the IC chip is mounted on the substrate, the protrusion can now be pressed with a constant pressing force. Therefore, the IC chip is pressed to maintain a reliable contact state between the bump and the IC chip.
【０００７】[0007]
【実施例】以下、本発明の半導体パッケージの一実施例
を図１乃至図３に基づいて説明する。なお、従来例の部
材と実質的に同様の部材には同一の符号を付している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the semiconductor package of the present invention will be described below with reference to FIGS. The members that are substantially similar to the members of the conventional example are designated by the same reference numerals.
【０００８】基板1 は、ポリイミドのような耐熱樹脂を
基材とし、配線回路1aを形成するとともにこれに電気的
に接続される端子ピン1bを設けていることは従来と同様
であるが、さらに後述のＩＣチップが一定量沈んだ状態
で嵌合する支持壁1cが設けられている。この支持壁1c
は、図１に示すように基板1 に積層固定した第２基板1d
に設けてもよいし、基板1 に積層固定した支持板に設け
てもよい。第２基板1dの上面に配線回路1aを形成する場
合は、これと基板1 の配線回路1aとをスルーホールを介
して電気的に接続させる。従って支持壁1cは、基板1に
積層固定した支持板に設けた方がより簡単な製造工程と
なる。The substrate 1 is made of a heat-resistant resin such as polyimide as a base material, and the wiring circuit 1a is formed and the terminal pins 1b electrically connected to the wiring circuit 1a are provided. A support wall 1c is provided in which an IC chip, which will be described later, is fitted in a state of being depressed by a certain amount. This support wall 1c
Is a second substrate 1d laminated and fixed to the substrate 1 as shown in FIG.
It may be provided on the base plate, or may be provided on a support plate laminated and fixed to the substrate 1. When the wiring circuit 1a is formed on the upper surface of the second substrate 1d, the wiring circuit 1a and the wiring circuit 1a of the substrate 1 are electrically connected via the through holes. Therefore, when the support wall 1c is provided on the support plate laminated and fixed to the substrate 1, the manufacturing process becomes easier.
【０００９】さらに、この支持壁1cには、その内面にＩ
Ｃチップの装着を可能にする程度に変形しかつＩＣチッ
プが装着された状態では一定の押圧力でもってＩＣチッ
プを押圧する低弾性率材料の複数の突起1e,1e,─が設け
られている。この突起1eは、好ましくは低弾性率であっ
て耐クリープ性が優れたポリエステル系エラストマー
(商品名「ペルプレン」「ハイトレル」「グリラックス
Ｅ」として市販されている) により、第２基板 (又は支
持板)1d に２度成形によって形成する。また、支持壁1c
の表面から突出している部分は半径0.25mm程度の疑似半
球状であってやや垂れ下がり部分を有する形状とし、Ｉ
Ｃチップを一定の押圧力でもって押圧するために、16乃
至20個設ける場合ＩＣチップの装着時に数十μm 程度変
形するよう設計する。なお、複数の突起1e,1e,─は、支
持壁1cに固定用凹所を設けておくとともに別に形成して
その凹所に接着するようにしてもよい。Further, the support wall 1c has an internal surface I
There are provided a plurality of protrusions 1e, 1e, of low elastic modulus material that are deformed to the extent that the C chip can be mounted and that press the IC chip with a certain pressing force when the IC chip is mounted. .. The protrusion 1e is preferably a polyester elastomer having a low elastic modulus and excellent creep resistance.
(Commercially available under the trade names "Perprene", "Hytrel", and "Grelax E") are formed on the second substrate (or support plate) 1d twice by molding. Also, the support wall 1c
The portion protruding from the surface of is a pseudo hemisphere with a radius of about 0.25 mm and has a shape with a slightly hanging portion.
In order to press the C chips with a constant pressing force, when 16 to 20 C chips are provided, they are designed to be deformed by several tens of μm when the IC chips are mounted. Incidentally, the plurality of protrusions 1e, 1e, -may be provided with a fixing recess in the support wall 1c, and may be separately formed and adhered to the recess.
【００１０】バンプ2 は、基板1 の配線回路1a上に多数
形成されており、具体的には、例えば80μm 角で30μm
程度の高さとし、基板1 にレジストを塗布し、フォトリ
ソグラフ工法によりレジストを除去後、電解メッキで成
長させて形成する。A large number of bumps 2 are formed on the wiring circuit 1a of the substrate 1, and specifically, for example, 80 μm square and 30 μm square.
The substrate 1 is coated with a resist having a height of about a certain degree, the resist is removed by a photolithography method, and then grown by electrolytic plating to form a film.
【００１１】ＩＣチップ3 は、従来例と同様、シリコン
を基材とし、露設された多数の入出力部 (図示せず) を
有する。このＩＣチップ3 は、図３に示すように、また
前述したように、複数の突起1e,1e,─を変形させつつ支
持壁1cに装着してその入出力部をバンプ2 に接触させ
る。図３(b) の状態では突起1eと支持壁1cが装着方向と
直交外方向に、図３(c) の状態では突起1eが装着方向に
それぞれ変形する。従ってＩＣチップ3 の入出力部は、
突起1eの変形反力により一定の押圧力でもってバンプ2
に押圧される。Like the conventional example, the IC chip 3 is made of silicon as a base material and has a large number of exposed input / output parts (not shown). As shown in FIG. 3 and as described above, this IC chip 3 is mounted on the support wall 1c while deforming the plurality of protrusions 1e, 1e,-, and its input / output portion is brought into contact with the bump 2. In the state of FIG. 3 (b), the protrusion 1e and the support wall 1c are deformed in the outer direction orthogonal to the mounting direction, and in the state of FIG. 3 (c), the protrusion 1e is deformed in the mounting direction. Therefore, the input / output section of IC chip 3
Bump 2 with constant pressing force due to the deformation reaction force of protrusion 1e
Is pressed by.
【００１２】キャップ5 も、同じく、ポリイミドのよう
な耐熱樹脂を基材とし、ＩＣチップ3 を保護すべく基板
1 に接着固定される。キャップ5 は、この実施例では平
板状であるが、支持壁1cを形成する第２基板 (あるいは
支持板)1d が小さい場合、下方が開口した箱状とする。Similarly, the cap 5 is also made of a heat-resistant resin such as polyimide as a base material, and is a substrate for protecting the IC chip 3.
Adhesively fixed to 1. The cap 5 has a flat plate shape in this embodiment, but when the second substrate (or support plate) 1d forming the support wall 1c is small, it has a box shape with an open bottom.
【００１３】[0013]
【発明の効果】本発明の半導体パッケージは、基板に、
ＩＣチップが一定量沈んだ状態で嵌合する支持壁を設
け、しかも支持壁の内面にＩＣチップの装着を可能にす
る程度に変形しかつＩＣチップが装着された状態では一
定の押圧力でもってＩＣチップを押圧する低弾性率材料
の複数の突起を設けたから、ＩＣチップはそれを支持壁
の突起を変形させながら押し込むだけで基板に装着で
き、しかもＩＣチップが基板に装着された状態では突起
が今度は一定の押圧力でもってＩＣチップを押圧してバ
ンプとＩＣチップの確実な接触状態が維持でき、接着樹
脂を用いた接着工程や熱圧着工程を不要にしてバンプと
ＩＣチップを接触させる工程が簡易化できるものとな
る。The semiconductor package of the present invention has a substrate
A support wall is provided to fit the IC chip in a certain depressed state, and the inner surface of the support wall is deformed to such an extent that the IC chip can be mounted. With the IC chip mounted, a constant pressing force is applied. Since a plurality of protrusions of low elastic modulus material for pressing the IC chip are provided, the IC chip can be mounted on the substrate only by pushing it in while deforming the protrusion of the support wall, and further, when the IC chip is mounted on the substrate, the protrusion is formed. However, this time, the IC chip can be pressed with a constant pressing force to maintain a reliable contact state between the bump and the IC chip, and the bump and the IC chip are brought into contact with each other without the need for a bonding step using an adhesive resin or a thermocompression bonding step. The process can be simplified.
【図１】本発明の一実施例を示す縦断面図である。FIG. 1 is a vertical sectional view showing an embodiment of the present invention.
【図２】その要部平面図である。FIG. 2 is a plan view of an essential part thereof.
【図３】(a)(b)(c) はＩＣチップの装着についての説明
図である。3 (a), (b) and (c) are explanatory views for mounting an IC chip.
【図４】従来例の縦断面図である。FIG. 4 is a vertical sectional view of a conventional example.
1 基板 1c 支持壁 1e 支持壁に設けた複数の突起 2 バンプ 3 ＩＣチップ 5 キャップ 1 substrate 1c support wall 1e multiple protrusions on the support wall 2 bumps 3 IC chip 5 cap
Claims (1)
気的に接続される端子ピンを設けた基板と、基板の配線
回路上に形成された多数のバンプと、露設された多数の
入出力部を有するＩＣチップと、ＩＣチップを保護すべ
く基板に接着固定されたキャップと、を有してバンプと
ＩＣチップの入出力部を接触させた半導体パッケージに
おいて、 前記基板に、ＩＣチップが一定量沈んだ状態で嵌合する
支持壁を設け、しかも支持壁の内面にＩＣチップの装着
を可能にする程度に変形しかつＩＣチップが装着された
状態では一定の押圧力でもってＩＣチップを押圧する低
弾性率材料の複数の突起を設けたことを特徴とする半導
体パッケージ。1. A substrate on which a wiring circuit is formed and terminal pins electrically connected thereto are provided, a large number of bumps formed on the wiring circuit of the substrate, and a large number of exposed input / output units. In a semiconductor package in which a bump and an input / output portion of the IC chip are in contact with each other, the IC chip having a fixed amount of the IC chip on the substrate. A support wall that fits in a depressed state is provided, and the inner surface of the support wall is deformed to the extent that the IC chip can be mounted, and when the IC chip is mounted, the IC chip is pressed with a certain pressing force. A semiconductor package comprising a plurality of protrusions made of a low elastic modulus material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3213789A JPH0555302A (en) | 1991-08-26 | 1991-08-26 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3213789A JPH0555302A (en) | 1991-08-26 | 1991-08-26 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0555302A true JPH0555302A (en) | 1993-03-05 |
Family
ID=16645083
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3213789A Pending JPH0555302A (en) | 1991-08-26 | 1991-08-26 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0555302A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6294408B1 (en) * | 1999-01-06 | 2001-09-25 | International Business Machines Corporation | Method for controlling thermal interface gap distance |
-
1991
- 1991-08-26 JP JP3213789A patent/JPH0555302A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6294408B1 (en) * | 1999-01-06 | 2001-09-25 | International Business Machines Corporation | Method for controlling thermal interface gap distance |
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