JP4428141B2 - Manufacturing method of semiconductor package - Google Patents

Manufacturing method of semiconductor package Download PDF

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JP4428141B2
JP4428141B2 JP2004155671A JP2004155671A JP4428141B2 JP 4428141 B2 JP4428141 B2 JP 4428141B2 JP 2004155671 A JP2004155671 A JP 2004155671A JP 2004155671 A JP2004155671 A JP 2004155671A JP 4428141 B2 JP4428141 B2 JP 4428141B2
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semiconductor chip
semiconductor
spacer
substrate
semiconductor package
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JP2005340415A (en
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人志 渋江
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Sony Corp
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
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    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
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    • H01L2924/181—Encapsulation

Description

本発明は半導体パッケージの製造方法に関する。詳しくは、基板と半導体チップ若しくはスペーサと半導体チップとの間隙に支持部材を形成することによって、上段に位置する半導体チップが下段に位置する半導体チップやスペーサよりも大きい場合であっても安定した品質、信頼性及び高い歩留りを実現しようとした半導体パッケージの製造方法に係るものである。 The present invention relates to a method for manufacturing a semiconductor package . Specifically, by forming a support member in the gap between the substrate and the semiconductor chip or the spacer and the semiconductor chip, stable quality even when the upper semiconductor chip is larger than the lower semiconductor chip or spacer The present invention relates to a method of manufacturing a semiconductor package that attempts to realize reliability and high yield.

昨今の各種電荷製品の小型化、薄型化、高機能化に伴い、その内部に使用される半導体パッケージにも小型化、薄型化、高機能化が要求され、従来の１つの半導体チップで１つの半導体パッケージを構成する様な単純な半導体パッケージではなく、ＳＩＰ（System in Package）やＭＣＭ（Multi Chip Module）と呼ばれる１つの半導体パッケージに複数個の半導体チップを搭載し、かつ立体的に搭載するスタックドパッケージと呼ばれるもの等の要求が多くなってきている（例えば、特許文献１参照。）。   Along with the recent miniaturization, thinning, and high functionality of various types of charge products, the semiconductor package used therein is also required to be downsized, thin, and high functionality. A stack in which a plurality of semiconductor chips are mounted in a single semiconductor package called SIP (System in Package) or MCM (Multi Chip Module) instead of a simple semiconductor package that constitutes a semiconductor package. There has been an increasing demand for a so-called package (for example, see Patent Document 1).

以下、図面を参酌しながら複数個の半導体チップを搭載した半導体パッケージ構造について説明する。
図７（ａ）は従来の半導体パッケージの一例を説明するための模式的な断面図であり、ここで示す半導体パッケージ１０１は、第１の半導体チップ１０２が配線基板１０３表面に形成されたソルダーレジスト１０４上にダイアタッチ材１０５を介して接着されている。
また、第１の半導体チップ上にはシリコンから成り第１の半導体チップよりも小さな第１のスペーサ１０６が接着され、第１のスペーサ上には第１のスペーサより大きい第２の半導体チップ１０７が接着されている。 Hereinafter, a semiconductor package structure in which a plurality of semiconductor chips are mounted will be described with reference to the drawings.
FIG. 7A is a schematic cross-sectional view for explaining an example of a conventional semiconductor package. A semiconductor package 101 shown here is a solder resist in which a first semiconductor chip 102 is formed on the surface of a wiring substrate 103. It is bonded on 104 via a die attach material 105.
Further, a first spacer 106 made of silicon and smaller than the first semiconductor chip is bonded onto the first semiconductor chip, and a second semiconductor chip 107 larger than the first spacer is bonded onto the first spacer. It is glued.

ここで、第１の半導体チップ上の電極（１）１０８及び第２の半導体チップ上の電極（２）１０９はＡｕワイヤー１１０でＡｕパッド１１１と接続され、Ａｕパッドは半導体チップ搭載側の配線パターン１１２に接続されている。また、半導体チップ搭載側の配線パターンはビア１１３によりマザー基板側の配線パターン１１４に接続され、マザー基板側の配線パターンはマザー基板側接続用端子１１５と接続されている。   Here, the electrode (1) 108 on the first semiconductor chip and the electrode (2) 109 on the second semiconductor chip are connected to the Au pad 111 by an Au wire 110, and the Au pad is a wiring pattern on the semiconductor chip mounting side. 112. Further, the wiring pattern on the semiconductor chip mounting side is connected to the wiring pattern 114 on the mother board side by vias 113, and the wiring pattern on the mother board side is connected to the mother board side connection terminal 115.

図８（ａ）は従来の半導体パッケージの他の一例を説明するための模式的な断面図であり、ここで示す半導体パッケージ１０１は、第１の半導体チップ１０２がフリップチップ接続により配線基板に接続されている。即ち、第１の半導体チップ１０２上の電極（１）１０８が直接半導体チップ搭載側の配線パターン１１２に接続されている。
また、第１の半導体チップ上には、第１の半導体チップよりも大きな第２の半導体チップ１０７が接着されている。 FIG. 8A is a schematic cross-sectional view for explaining another example of the conventional semiconductor package. In the semiconductor package 101 shown here, the first semiconductor chip 102 is connected to the wiring substrate by flip-chip connection. Has been. That is, the electrode (1) 108 on the first semiconductor chip 102 is directly connected to the wiring pattern 112 on the semiconductor chip mounting side.
In addition, a second semiconductor chip 107 larger than the first semiconductor chip is bonded onto the first semiconductor chip.

ここで、第２の半導体チップ上の電極（２）１０９はＡｕワイヤー１１０でＡｕパッド１１１と接続され、Ａｕパッドは半導体チップ搭載側の配線パターン１１２に接続されている。また、半導体チップ搭載側の配線パターンはビア１１３によりマザー基板側の配線パターン１１４に接続され、マザー基板側の配線パターンはマザー基板側接続用端子１１５に接続されている。   Here, the electrode (2) 109 on the second semiconductor chip is connected to the Au pad 111 by the Au wire 110, and the Au pad is connected to the wiring pattern 112 on the semiconductor chip mounting side. Further, the wiring pattern on the semiconductor chip mounting side is connected to the wiring pattern 114 on the mother board side by vias 113, and the wiring pattern on the mother board side is connected to the mother board side connection terminal 115.

なお、上記した従来の半導体パッケージはいずれも第１の半導体チップ、第２の半導体チップ、Ａｕワイヤー及び半導体チップ側の配線パターンがモールド樹脂１１６によって完全に被覆されている。   In each of the conventional semiconductor packages described above, the first semiconductor chip, the second semiconductor chip, the Au wire, and the wiring pattern on the semiconductor chip side are completely covered with the mold resin 116.

また、第２の半導体チップ上にシリコンから成り第２の半導体チップよりも小さな第２のスペーサ１１７が接着されると共に、第２のスペーサ上に第２のスペーサより大きい第３の半導体チップ１１８が接着され、第３の半導体チップ上の電極（３）１１９とＡｕパッドとがＡｕワイヤーで接続されることによって、３つの半導体チップが搭載された半導体パッケージ構造をそれぞれ図７（ｂ）、図８（ｂ）に示す。   In addition, a second spacer 117 made of silicon and smaller than the second semiconductor chip is adhered on the second semiconductor chip, and a third semiconductor chip 118 larger than the second spacer is formed on the second spacer. The semiconductor package structure in which three semiconductor chips are mounted by bonding the electrode (3) 119 and the Au pad on the third semiconductor chip with an Au wire is shown in FIGS. Shown in (b).

特開２００２−３７３９６８号JP 2002-373968 A

ところで、複数個の半導体チップの搭載方法は組み合わせる半導体チップの種類によっても異なり様々であるが、上記した従来の半導体パッケージの一例の様に下段に位置する第１のスペーサの大きさよりも上段に位置する第２の半導体チップの大きさが大きくなったり、上記した従来の半導体パッケージの他の一例の様に下段に位置する第１の半導体チップの大きさよりも上段に位置する第２の半導体チップの大きさが大きくなったりした場合には、オーバーハング部１２０を生じる。   By the way, although the mounting method of a plurality of semiconductor chips varies depending on the types of semiconductor chips to be combined and varies, it is positioned higher than the size of the first spacer positioned in the lower stage as in the above-described conventional semiconductor package. The size of the second semiconductor chip increases, or the size of the second semiconductor chip positioned above the size of the first semiconductor chip positioned lower than the size of the first semiconductor chip positioned lower than the conventional semiconductor package described above. When the size increases, an overhang portion 120 is generated.

ここで、オーバーハング部が生じると、ボンディングワイヤーで半導体チップと配線基板とを接続する際に、オーバーハング部を有する半導体チップに部分的な負荷がかかり、半導体チップの破損、もしくは微小なクラックによる半導体チップ内の配線の断線が生じることがある。そのために、半導体チップを薄型化できず、より多くの半導体チップを積み重ねることができなかったり、ボンディングワイヤーでの接続時の負荷を軽減する必要が生じ、半導体チップとボンディングワイヤー部の接続において充分な強度が得られなかったりする。   Here, when the overhang portion is generated, a partial load is applied to the semiconductor chip having the overhang portion when the semiconductor chip and the wiring board are connected by the bonding wire, and the semiconductor chip is damaged or is caused by a minute crack. Wire breakage in the semiconductor chip may occur. Therefore, the semiconductor chip cannot be thinned, more semiconductor chips cannot be stacked, and it is necessary to reduce the load at the time of connection with the bonding wire, which is sufficient for the connection between the semiconductor chip and the bonding wire portion. Strength may not be obtained.

本発明は以上の点に鑑みて創案されたものであって、上段に位置する半導体チップが下段に位置する半導体チップやスペーサよりも大きい場合であっても安定した品質、信頼性及び高い歩留りを実現することが可能である半導体パッケージの製造方法を提供することを目的とするものである。 The present invention was devised in view of the above points, and provides stable quality, reliability and high yield even when the semiconductor chip located in the upper stage is larger than the semiconductor chip or spacer located in the lower stage. It is an object of the present invention to provide a semiconductor package manufacturing method that can be realized.

上記の目的を達成するために、本発明に係る半導体パッケージは、基板と、該基板に搭載された第１の半導体チップと、該第１の半導体チップに搭載され、前記第１の半導体チップよりも大きな第２の半導体チップと、前記第１の半導体チップ及び第２の半導体チップを被覆する封止樹脂を備え、前記基板と前記第２の半導体チップがボンディングワイヤーによって接続されている半導体パッケージにおいて、前記基板と前記第２の半導体チップとの間隙に支持部材が形成されている。   In order to achieve the above object, a semiconductor package according to the present invention includes a substrate, a first semiconductor chip mounted on the substrate, and a first semiconductor chip mounted on the first semiconductor chip. A semiconductor package including a second semiconductor chip having a larger size and a sealing resin covering the first semiconductor chip and the second semiconductor chip, wherein the substrate and the second semiconductor chip are connected by a bonding wire. A support member is formed in a gap between the substrate and the second semiconductor chip.

また、上記の目的を達成するために、本発明に係る半導体パッケージは、基板と、該基板に搭載された第１の半導体チップと、該第１の半導体チップにスペーサを介して搭載され、同スペーサよりも大きな第２の半導体チップと、前記第１の半導体チップ及び第２の半導体チップを被覆する封止樹脂を備え、前記基板と前記第２の半導体チップがボンディングワイヤーによって接続されている半導体パッケージにおいて、少なくとも前記第１の半導体チップと前記第２の半導体チップとの間隙に支持部材が形成されている。   In order to achieve the above object, a semiconductor package according to the present invention is mounted on a substrate, a first semiconductor chip mounted on the substrate, and a spacer on the first semiconductor chip. A semiconductor having a second semiconductor chip larger than a spacer, and a sealing resin that covers the first semiconductor chip and the second semiconductor chip, and the substrate and the second semiconductor chip are connected by a bonding wire In the package, a support member is formed at least in a gap between the first semiconductor chip and the second semiconductor chip.

ここで、基板と第２の半導体チップとの間隙若しくは少なくとも第１の半導体チップと第２の半導体チップとの間隙に支持部材が形成されたことによって、基板と第２の半導体チップとをボンディングワイヤーで接続する際にオーバーハング部に加わる部分的な負荷を軽減することができる。   Here, the support member is formed in the gap between the substrate and the second semiconductor chip or at least in the gap between the first semiconductor chip and the second semiconductor chip, so that the substrate and the second semiconductor chip are bonded to each other by a bonding wire. It is possible to reduce a partial load applied to the overhang portion when connecting with the.

また、上記の目的を達成するために、本発明に係る半導体パッケージの製造方法は、基板に第１の半導体チップを搭載する工程と、該第１の半導体チップの周辺領域に支持部材を形成する工程と、前記第１の半導体チップに同第１の半導体チップよりも大きな第２の半導体チップを搭載する工程と、前記基板と前記第２の半導体チップをボンディングワイヤーによって接続する工程と、前記第１の半導体チップ及び第２の半導体チップを樹脂封止する工程を備える。   In order to achieve the above object, a method of manufacturing a semiconductor package according to the present invention includes a step of mounting a first semiconductor chip on a substrate, and a support member is formed in a peripheral region of the first semiconductor chip. Mounting a second semiconductor chip larger than the first semiconductor chip on the first semiconductor chip, connecting the substrate and the second semiconductor chip with a bonding wire, A step of resin-sealing the first semiconductor chip and the second semiconductor chip;

ここで、第１の半導体チップの周辺領域に支持部材を形成することによって、即ち、第１の半導体チップに第２の半導体チップを搭載した際に、基板と第２の半導体チップとの間隙となる領域に支持部材を形成することによって、基板と第２の半導体チップをボンディングワイヤーによって接続する際にオーバーハング部に加わる部分的な負荷を軽減することができる。   Here, by forming a supporting member in the peripheral region of the first semiconductor chip, that is, when the second semiconductor chip is mounted on the first semiconductor chip, the gap between the substrate and the second semiconductor chip is reduced. By forming the support member in the region to be formed, it is possible to reduce a partial load applied to the overhang portion when the substrate and the second semiconductor chip are connected by the bonding wire.

また、本発明に係る半導体パッケージの製造方法は、基板に第１の半導体チップを搭載する工程と、該第１の半導体チップにスペーサを搭載する工程と、該スペーサの周辺領域に支持部材を形成する工程と、前記スペーサに同スペーサよりも大きな第２の半導体チップを搭載する工程と、前記基板と前記第２の半導体チップをボンディングワイヤーによって接続する工程と、前記第１の半導体チップ及び第２の半導体チップを樹脂封止する工程を備える。   The method for manufacturing a semiconductor package according to the present invention includes a step of mounting a first semiconductor chip on a substrate, a step of mounting a spacer on the first semiconductor chip, and forming a support member in a peripheral region of the spacer. A step of mounting a second semiconductor chip larger than the spacer on the spacer, a step of connecting the substrate and the second semiconductor chip by bonding wires, the first semiconductor chip and the second semiconductor chip A step of resin-sealing the semiconductor chip.

ここで、スペーサの周辺領域に支持部材を形成することによって、即ち、スペーサに第２の半導体チップを搭載した際に、第１の半導体チップと第２の半導体チップとの間隙となる領域若しくは第１の半導体チップと第２の半導体チップとの間隙となる領域及び基板と第２の半導体チップとの間隙となる領域に支持部材を形成することによって、基板と第２の半導体チップをボンディングワイヤーで接続する際にオーバーハング部に加わる部分的な負荷を軽減することができる。   Here, by forming the support member in the peripheral region of the spacer, that is, when the second semiconductor chip is mounted on the spacer, the region or the first gap that becomes the gap between the first semiconductor chip and the second semiconductor chip. A support member is formed in a region serving as a gap between the first semiconductor chip and the second semiconductor chip and a region serving as a gap between the substrate and the second semiconductor chip, so that the substrate and the second semiconductor chip are bonded with a bonding wire. A partial load applied to the overhang portion when connecting can be reduced.

上記した本発明の半導体パッケージの製造方法では、支持部材で第２の半導体チップのオーバーハング部を支持するために、基板と第２の半導体チップをボンディングワイヤーで接続する際にオーバーハング部を有する第２の半導体チップに部分的な負荷がかかり、第２の半導体チップを破損、もしくは微小なクラックによる第２の半導体チップ内の配線の断線を抑制でき、そのため第２の半導体チップの薄型化が実現し、より多くの半導体チップをスタックすることができるようになると共に、半導体チップとボンディングワイヤー部の接続において充分な強度を得ることができる。 In the semiconductor package manufacturing method of the present invention described above, in order to support the overhang portion of the second semiconductor chip by the support member, the overhang portion is provided when the substrate and the second semiconductor chip are connected by the bonding wire. A partial load is applied to the second semiconductor chip, the second semiconductor chip is damaged, or disconnection of the wiring in the second semiconductor chip due to a minute crack can be suppressed, so that the second semiconductor chip can be thinned. As a result, more semiconductor chips can be stacked, and sufficient strength can be obtained in the connection between the semiconductor chip and the bonding wire portion.

以下、本発明の実施の形態について図面を参照しながら説明し、本発明の理解に供する。
図１は本発明を適用した半導体パッケージの一例を説明するための模式的な断面図であり、ここで示す半導体パッケージ１は、第１の半導体チップ２が配線基板３表面に形成されたソルダーレジスト４上にダイアタッチ材５を介して接着されている。 Hereinafter, embodiments of the present invention will be described with reference to the drawings to facilitate understanding of the present invention.
FIG. 1 is a schematic cross-sectional view for explaining an example of a semiconductor package to which the present invention is applied. A semiconductor package 1 shown here is a solder resist in which a first semiconductor chip 2 is formed on the surface of a wiring board 3. 4 is bonded via a die attach material 5.

上記した第１の半導体チップ上には、シリコンから成り第１の半導体チップよりも小さなスペーサ６が接着され、スペーサ上にはスペーサより大きい第２の半導体チップ７が接着されている。   A spacer 6 made of silicon and smaller than the first semiconductor chip is bonded onto the first semiconductor chip, and a second semiconductor chip 7 larger than the spacer is bonded onto the spacer.

更に、第１の半導体チップ上の電極（１）８及び第２の半導体チップ上の電極（２）９はＡｕワイヤー１０でＡｕパッド１１と接続され、Ａｕパッドは半導体チップ搭載側の配線パターン１２に接続されている。また、半導体チップ搭載側の配線パターンはビア１３によりマザー基板側の配線パターン１４に接続され、マザー基板側の配線パターンはマザー基板側接続用端子１５と接続されている。   Further, the electrode (1) 8 on the first semiconductor chip and the electrode (2) 9 on the second semiconductor chip are connected to an Au pad 11 by an Au wire 10, and the Au pad is a wiring pattern 12 on the semiconductor chip mounting side. It is connected to the. The wiring pattern on the semiconductor chip mounting side is connected to the wiring pattern 14 on the mother board side by vias 13, and the wiring pattern on the mother board side is connected to the mother board side connection terminals 15.

また、第１の半導体チップと第２の半導体チップの間隙には樹脂材料により成る支持部材２０が形成され、第２の半導体チップのオーバーハング部は支持部材によって支持されている。
更に、第１の半導体チップ、第２の半導体チップ、Ａｕワイヤー及び半導体チップ側の配線パターンはモールド樹脂１６によって完全に被覆されている。 A support member 20 made of a resin material is formed in the gap between the first semiconductor chip and the second semiconductor chip, and the overhang portion of the second semiconductor chip is supported by the support member.
Further, the first semiconductor chip, the second semiconductor chip, the Au wire, and the wiring pattern on the semiconductor chip side are completely covered with the mold resin 16.

以下、上記した半導体パッケージの製造方法について説明する。即ち、本発明を適用した半導体パッケージの製造方法の一例について説明する。   Hereinafter, a method for manufacturing the above-described semiconductor package will be described. That is, an example of a method for manufacturing a semiconductor package to which the present invention is applied will be described.

本発明を適用した半導体パッケージの製造方法の一例では、先ず、図２（ａ）で示す様に、配線基板３表面に形成されたソルダーレジスト４上に第１の半導体チップ２をダイアタッチ材５を用いて接着した後、第１の半導体チップ上にシリコンから成るスペーサ６を接着する。   In an example of a method of manufacturing a semiconductor package to which the present invention is applied, first, as shown in FIG. 2A, the first semiconductor chip 2 is attached to the die attach material 5 on the solder resist 4 formed on the surface of the wiring substrate 3. Then, a spacer 6 made of silicon is bonded onto the first semiconductor chip.

次に、図２（ｂ）で示す様に、Ａｕワイヤー１０で第１の半導体チップ上の電極（１）８とＡｕパッド１１を接続する。   Next, as shown in FIG. 2B, the electrode (1) 8 on the first semiconductor chip and the Au pad 11 are connected by the Au wire 10.

なお、本実施例では第１の半導体チップ上にスペーサを接着した後にＡｕワイヤーで電極（１）とＡｕパッドを接続しているが、Ａｕワイヤーで電極（１）とＡｕパッドを接続した後に第１の半導体チップ上にスペーサを接着しても構わない。   In this embodiment, the electrode (1) and the Au pad are connected by the Au wire after bonding the spacer on the first semiconductor chip. However, after the electrode (1) and the Au pad are connected by the Au wire, the first A spacer may be bonded onto one semiconductor chip.

続いて、図２（ｃ）で示す様に、第１の半導体チップ上の第２の半導体チップのオーバーハング部の下部に相当する領域に液状樹脂２１をポッティング法により塗布した後、図２（ｄ）で示す様に、第２の半導体チップを搭載し、塗布した液状樹脂を硬化する。   Subsequently, as shown in FIG. 2C, a liquid resin 21 is applied to a region corresponding to the lower portion of the overhang portion of the second semiconductor chip on the first semiconductor chip by a potting method, and then FIG. As shown by d), the second semiconductor chip is mounted and the applied liquid resin is cured.

ここで、第２の半導体チップの搭載時の接着剤の硬化は、液状樹脂の硬化と同タイミングで行っても良いし、硬化の条件によっては別々のタイミングで行っても良い。   Here, the curing of the adhesive when the second semiconductor chip is mounted may be performed at the same timing as the curing of the liquid resin, or may be performed at different timings depending on the curing conditions.

次に、図２（ｅ）で示す様に、第２の半導体チップ上の電極（２）９とＡｕパッドを接続した後、封止金型内に装填し、封止金型内にトランスフォーモールド法によってモールド樹脂を注入して封止を行うことによって、図１に示す様な半導体パッケージを得ることができる。   Next, as shown in FIG. 2 (e), the electrode (2) 9 on the second semiconductor chip and the Au pad are connected, and then loaded into the sealing mold, and the transform is placed in the sealing mold. A semiconductor package as shown in FIG. 1 can be obtained by sealing by injecting a mold resin by a molding method.

図３は本発明を適用した半導体パッケージの他の一例を説明するための模式的な断面図であり、ここで示す半導体パッケージは、上記した本発明を適用した半導体パッケージの一例と同様に、第１の半導体チップが配線基板表面に形成されたソルダーレジスト上にダイアタッチ材を介して接着されている。   FIG. 3 is a schematic cross-sectional view for explaining another example of the semiconductor package to which the present invention is applied. The semiconductor package shown here is similar to the above-described example of the semiconductor package to which the present invention is applied. One semiconductor chip is bonded to a solder resist formed on the surface of the wiring board via a die attach material.

上記した第１の半導体チップ上には、シリコンから成り第１の半導体チップよりも小さなスペーサが接着され、スペーサ上にはスペーサより大きい第２の半導体チップが接着されている。   A spacer made of silicon and smaller than the first semiconductor chip is bonded onto the first semiconductor chip, and a second semiconductor chip larger than the spacer is bonded onto the spacer.

更に、第１の半導体チップ上の電極（１）及び第２の半導体チップ上の電極（２）はＡｕワイヤーでＡｕパッドと接続され、Ａｕパッドは半導体チップ搭載側の配線パターンに接続されている。また、半導体チップ搭載側の配線パターンはビアによりマザー基板側の配線パターンに接続され、マザー基板側の配線パターンはマザー基板側接続用端子と接続されている。   Further, the electrode (1) on the first semiconductor chip and the electrode (2) on the second semiconductor chip are connected to an Au pad by an Au wire, and the Au pad is connected to a wiring pattern on the semiconductor chip mounting side. . The wiring pattern on the semiconductor chip mounting side is connected to the wiring pattern on the mother board side by vias, and the wiring pattern on the mother board side is connected to the connection terminal on the mother board side.

また、第１の半導体チップと第２の半導体チップの間隙及び基板と第２の半導体チップの間隙には樹脂材料より成る支持部材が形成され、第２の半導体チップのオーバーハング部は支持部材によって支持されている。
更に、第１の半導体チップ、第２の半導体チップ、Ａｕワイヤー及び半導体チップ側の配線パターンはモールド樹脂によって完全に被覆されている。 A support member made of a resin material is formed in the gap between the first semiconductor chip and the second semiconductor chip and in the gap between the substrate and the second semiconductor chip, and the overhang portion of the second semiconductor chip is formed by the support member. It is supported.
Further, the first semiconductor chip, the second semiconductor chip, the Au wire, and the wiring pattern on the semiconductor chip side are completely covered with the mold resin.

以下、上記した半導体パッケージの製造方法について説明する。即ち、本発明を適用した半導体パッケージの製造方法の他の一例を説明する。   Hereinafter, a method for manufacturing the above-described semiconductor package will be described. That is, another example of a semiconductor package manufacturing method to which the present invention is applied will be described.

本発明を適用した半導体パッケージの製造方法の他の一例では、先ず、図４（ａ）で示す様に、配線基板表面に形成されたソルダーレジスト上に第１の半導体チップをダイアタッチ材を用いて接着した後、第１の半導体チップ上にシリコンから成るスペーサを接着する。   In another example of a semiconductor package manufacturing method to which the present invention is applied, first, as shown in FIG. 4A, a first semiconductor chip is used as a die attach material on a solder resist formed on the surface of a wiring board. After bonding, a spacer made of silicon is bonded onto the first semiconductor chip.

次に、図４（ｂ）で示す様に、Ａｕワイヤーで第１の半導体チップ上の電極（１）とＡｕパッドを接続する。   Next, as shown in FIG. 4B, the electrode (1) on the first semiconductor chip and the Au pad are connected by an Au wire.

なお、本実施例では第１の半導体チップ上にスペーサを接着した後にＡｕワイヤーで電極（１）とＡｕパッドを接続しているが、上記した様に、Ａｕワイヤーで電極（１）とＡｕパッドを接続した後に第１の半導体チップ上にスペーサを接着しても構わない。   In this embodiment, the electrode (1) and the Au pad are connected with the Au wire after bonding the spacer on the first semiconductor chip. However, as described above, the electrode (1) and the Au pad are connected with the Au wire. A spacer may be bonded onto the first semiconductor chip after the connection.

続いて、図４（ｃ）で示す様に、液状樹脂を貯めておくためのダム樹脂２２を第２の半導体チップのオーバーハング部の下部に相当する領域の外周に塗布し、続いて液状樹脂をポッティング法により塗布した後、図４（ｄ）で示す様に、第２の半導体チップを搭載し、塗布した液状樹脂を硬化する。   Subsequently, as shown in FIG. 4C, the dam resin 22 for storing the liquid resin is applied to the outer periphery of the region corresponding to the lower portion of the overhang portion of the second semiconductor chip, and then the liquid resin. Is applied by a potting method, and then, as shown in FIG. 4D, a second semiconductor chip is mounted, and the applied liquid resin is cured.

ここで、第２の半導体チップの搭載時の接着剤の硬化は、液状樹脂の硬化と同タイミングで行っても良いし、硬化の条件によっては別々のタイミングで行っても良い。   Here, the curing of the adhesive when the second semiconductor chip is mounted may be performed at the same timing as the curing of the liquid resin, or may be performed at different timings depending on the curing conditions.

次に、図４（ｅ）で示す様に、第２の半導体チップ上の電極（２）とＡｕパッドを接続した後、封止金型内に装填し、封止金型内にトランスファーモールド法によってモールド樹脂を注入して封止を行うことによって、図３に示す様な半導体パッケージを得ることができる。   Next, as shown in FIG. 4E, after the electrode (2) on the second semiconductor chip and the Au pad are connected, they are loaded into a sealing mold, and transfer molding is performed in the sealing mold. A semiconductor package as shown in FIG. 3 can be obtained by injecting mold resin and sealing.

図５は本発明を適用した半導体パッケージの更に他の一例を説明するための模式的な断面図であり、ここで示す半導体パッケージは、第１の半導体チップがフリップチップ接続により配線基板に接続されている。即ち、第１の半導体チップ上の電極（１）が直接半導体チップ搭載側の配線パターンに接続されている。
また、第１の半導体チップ上には、第１の半導体チップよりも大きな第２の半導体チップが接着されている。 FIG. 5 is a schematic cross-sectional view for explaining still another example of the semiconductor package to which the present invention is applied. In the semiconductor package shown here, the first semiconductor chip is connected to the wiring substrate by flip chip connection. ing. That is, the electrode (1) on the first semiconductor chip is directly connected to the wiring pattern on the semiconductor chip mounting side.
Also, a second semiconductor chip larger than the first semiconductor chip is bonded onto the first semiconductor chip.

上記した第２の半導体チップ上の電極（２）はＡｕワイヤーでＡｕパッドと接続され、Ａｕパッドは半導体チップ搭載側の配線パターンに接続されている。また、半導体チップ搭載側の配線パターンはビアによりマザー基板側の配線パターンに接続され、マザー基板側の配線パターンはマザー基板側接続用端子と接続されている。   The electrode (2) on the second semiconductor chip is connected to an Au pad by an Au wire, and the Au pad is connected to a wiring pattern on the semiconductor chip mounting side. The wiring pattern on the semiconductor chip mounting side is connected to the wiring pattern on the mother board side by vias, and the wiring pattern on the mother board side is connected to the connection terminal on the mother board side.

また、第２の半導体チップと基板の間隙には樹脂材料より成る支持部材が形成され、第２の半導体チップのオーバーハング部は支持部材によって支持されている。
更に、第１の半導体チップ、第２の半導体チップ、Ａｕワイヤー及び半導体チップ側の配線パターンはモールド樹脂によって完全に被覆されている。 A support member made of a resin material is formed in the gap between the second semiconductor chip and the substrate, and the overhang portion of the second semiconductor chip is supported by the support member.
Further, the first semiconductor chip, the second semiconductor chip, the Au wire, and the wiring pattern on the semiconductor chip side are completely covered with the mold resin.

以下、上記した半導体パッケージの製造方法について説明する。即ち、本発明を適用した半導体パッケージの製造方法の更に他の一例について説明する。   Hereinafter, a method for manufacturing the above-described semiconductor package will be described. That is, still another example of the semiconductor package manufacturing method to which the present invention is applied will be described.

本発明を適用した半導体パッケージの製造方法の更に他の一例では、先ず、図６（ａ）で示す様に、第１の半導体チップをフリップチップ方式で配線基板に接続する。即ち、第１の半導体チップ上の電極（１）を直接半導体チップ搭載側の配線パターンに接続する。   In still another example of the semiconductor package manufacturing method to which the present invention is applied, first, as shown in FIG. 6A, the first semiconductor chip is connected to the wiring board by a flip chip method. That is, the electrode (1) on the first semiconductor chip is directly connected to the wiring pattern on the semiconductor chip mounting side.

次に、図６（ｂ）で示す様に、配線基板上の第２の半導体チップのオーバーハング部の下部に相当する領域に液状樹脂をポッティング法により塗布した後、図６（ｃ）で示す様に、第２の半導体チップを搭載し、塗布した液状樹脂を硬化する。   Next, as shown in FIG. 6B, a liquid resin is applied to a region corresponding to the lower portion of the overhang portion of the second semiconductor chip on the wiring substrate by a potting method, and then shown in FIG. 6C. Similarly, the second semiconductor chip is mounted, and the applied liquid resin is cured.

次に、図６（ｄ）で示す様に、第２の半導体チップ上の電極（２）とＡｕパッドを接続した後、封止金型内に装填し、封止金型内にトランスファーモールド法によってモールド樹脂を注入して封止を行うことによって、図５に示す様な半導体パッケージを得ることができる。   Next, as shown in FIG. 6 (d), after the electrode (2) on the second semiconductor chip and the Au pad are connected, they are loaded into a sealing mold, and transfer molding is performed in the sealing mold. By injecting mold resin and sealing, a semiconductor package as shown in FIG. 5 can be obtained.

なお、上記した本発明を適用した半導体パッケージでは、いずれも液状樹脂を硬化させて支持部材を構成していたが、支持部材は第２の半導体チップのオーバーハング部を支持することができれば充分であり、必ずしも樹脂材料によって形成される必要は無い。
なお、これまでの説明において基板は２層構造の両面版の事例で説明を行ったが、基板の層構造やその種類については、特に限定されるわけではない。 In each of the semiconductor packages to which the present invention is applied, the liquid resin is cured to form the support member. However, it is sufficient that the support member can support the overhang portion of the second semiconductor chip. There is no need to be formed of a resin material.
In the above description, the substrate has been described as an example of a double-sided version having a two-layer structure, but the layer structure and type of the substrate are not particularly limited.

上記した本発明を適用した半導体パッケージでは、第２の半導体チップのオーバーハング部の下部に相当する領域に液状樹脂を硬化させた支持部材が形成され、この支持部材で第２の半導体チップのオーバーハング部を支持するために、基板と第２の半導体チップをボンディングワイヤーで接続する際にオーバーハング部を有する第２の半導体チップに部分的な負荷がかかり、第２の半導体チップを破損、もしくは微小なクラックによる第２の半導体チップ内の配線の断線を抑制でき、そのため第２の半導体チップの薄型化が実現し、より多くの半導体チップをスタックすることができるようになると共に、半導体チップとボンディングワイヤー部の接続において充分な強度を得ることができる。   In the semiconductor package to which the present invention described above is applied, a support member in which a liquid resin is cured is formed in a region corresponding to the lower portion of the overhang portion of the second semiconductor chip, and the support member overlies the second semiconductor chip. A partial load is applied to the second semiconductor chip having the overhang portion when the substrate and the second semiconductor chip are connected by the bonding wire to support the hang portion, and the second semiconductor chip is damaged, or The disconnection of the wiring in the second semiconductor chip due to minute cracks can be suppressed, so that the thickness of the second semiconductor chip can be reduced and more semiconductor chips can be stacked. Sufficient strength can be obtained in the connection of the bonding wire portion.

また、オーバーハング部の下部に隙間が存在し、この隙間にボンディングワイヤーが位置する場合には、封止樹脂で半導体パッケージの樹脂封止をする際に、充分に封止樹脂が充填されなかったり、ボイドが発生したり、狭い隙間に封止樹脂を充填させるが故にボンディングワイヤーを変形させたりといった信頼性の低下や歩留りの低下を招くこととなるが、上記した本発明を適用した半導体パッケージでは、かかる不具合が生じない。   In addition, when there is a gap below the overhang part and the bonding wire is located in this gap, the sealing resin may not be sufficiently filled when the semiconductor package is sealed with the sealing resin. In the semiconductor package to which the present invention is applied, however, voids are generated or the bonding wire is deformed because the sealing resin is filled in a narrow gap, resulting in a decrease in reliability and yield. This problem does not occur.

本発明を適用した半導体パッケージの一例を説明するための模式的な断面図である。It is typical sectional drawing for demonstrating an example of the semiconductor package to which this invention is applied. 本発明を適用した半導体パッケージの製造方法の一例を説明するための模式的な断面図である。It is typical sectional drawing for demonstrating an example of the manufacturing method of the semiconductor package to which this invention is applied. 本発明を適用した半導体パッケージの他の一例を説明するための模式的な断面図である。It is typical sectional drawing for demonstrating another example of the semiconductor package to which this invention is applied. 本発明を適用した半導体パッケージの製造方法の他の一例を説明するための模式的な断面図である。It is typical sectional drawing for demonstrating another example of the manufacturing method of the semiconductor package to which this invention is applied. 本発明を適用した半導体パッケージの更に他の一例を説明するための模式的な断面図である。It is typical sectional drawing for demonstrating another example of the semiconductor package to which this invention is applied. 本発明を適用した半導体パッケージの製造方法の更に他の一例を説明するための模式的な断面図である。It is typical sectional drawing for demonstrating another example of the manufacturing method of the semiconductor package to which this invention is applied. 従来の半導体パッケージの一例を説明するための模式的な断面図である。It is typical sectional drawing for demonstrating an example of the conventional semiconductor package. 従来の半導体パッケージの他の一例を説明するための模式的な断面図である。It is typical sectional drawing for demonstrating another example of the conventional semiconductor package.

符号の説明Explanation of symbols

１ 半導体パッケージ
２ 第１の半導体チップ
３ 配線基板
４ ソルダーレジスト
５ ダイアタッチ材
６ スペーサ
７ 第２の半導体チップ
８ 電極（１）
９ 電極（２）
１０ Ａｕワイヤー
１１ Ａｕパッド
１２ 半導体チップ搭載側の配線パターン
１３ ビア
１４ マザー基板側の配線パターン
１５ マザー基板側接続用端子
１６ モールド樹脂
２０ 支持部材
２１ 液状樹脂
２２ ダム樹脂 DESCRIPTION OF SYMBOLS 1 Semiconductor package 2 1st semiconductor chip 3 Wiring board 4 Solder resist 5 Die attach material 6 Spacer 7 2nd semiconductor chip 8 Electrode (1)
9 Electrode (2)
DESCRIPTION OF SYMBOLS 10 Au wire 11 Au pad 12 Semiconductor chip mounting side wiring pattern 13 Via 14 Mother board side wiring pattern 15 Mother board side connection terminal 16 Mold resin 20 Support member 21 Liquid resin 22 Dam resin

Claims (1)

基板に第１の半導体チップを搭載する工程と、Mounting a first semiconductor chip on a substrate;
前記第１の半導体チップにスペーサを搭載する工程と、Mounting a spacer on the first semiconductor chip;
前記基板と前記第１の半導体チップをボンディングワイヤーによって接続する工程と、Connecting the substrate and the first semiconductor chip by a bonding wire;
前記第１の半導体チップの外周にダム樹脂を塗布する工程と、Applying a dam resin to the outer periphery of the first semiconductor chip;
前記スペーサと前記ダム樹脂との間にポッティング法により液状樹脂を塗布し、前記スペーサの周辺領域に支持部材を形成すると共に、前記基板と前記第１の半導体チップを接続するボンディングワイヤーを封止する工程と、A liquid resin is applied between the spacer and the dam resin by a potting method, a support member is formed in the peripheral region of the spacer, and a bonding wire for connecting the substrate and the first semiconductor chip is sealed. Process,
前記支持部材の形成後に、前記スペーサに同スペーサよりも大きな第２の半導体チップを搭載する工程と、Mounting a second semiconductor chip larger than the spacer on the spacer after forming the support member;
前記基板と前記第２の半導体チップをボンディングワイヤーによって接続する工程と、Connecting the substrate and the second semiconductor chip by a bonding wire;
前記第１の半導体チップ及び前記第２の半導体チップを樹脂封止する工程とを備えるAnd resin sealing the first semiconductor chip and the second semiconductor chip.
半導体パッケージの製造方法。A method for manufacturing a semiconductor package.
JP2004155671A 2004-05-26 2004-05-26 Manufacturing method of semiconductor package Expired - Fee Related JP4428141B2 (en)

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JP4998268B2 (en) * 2005-08-24 2012-08-15 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method thereof
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JP5667381B2 (en) * 2010-06-01 2015-02-12 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． Semiconductor device and manufacturing method thereof
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