JPH0555229A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0555229A JPH0555229A JP3235659A JP23565991A JPH0555229A JP H0555229 A JPH0555229 A JP H0555229A JP 3235659 A JP3235659 A JP 3235659A JP 23565991 A JP23565991 A JP 23565991A JP H0555229 A JPH0555229 A JP H0555229A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- oka
- electrode pad
- shaped solder
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
岡状半田バンプを用いた半導体装置の外部入出力部の構
造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of an external input / output section of a semiconductor device using an oka solder bump.
【０００２】[0002]
【従来の技術】従来、半導体装置の外部入出力部の構造
として、岡状半田バンプを用いた構造が採用されてい
る。この岡状半田バンプは、半導体装置に設けた配線パ
ターンの一部を電極パッド部として構成し、この電極パ
ッド部を覆う絶縁膜の一部を電極パッド部上で開口し、
この開口部に半田を岡状に形成してバンプとして構成す
るものである。この開口の形状としては、４角形や８角
形若しくは円形等、種々の形状のものが採用されてお
り、通常は電極パッド部の形状に対応した形状としてい
る。2. Description of the Related Art Conventionally, a structure using an oka-shaped solder bump has been adopted as a structure of an external input / output portion of a semiconductor device. This oka-shaped solder bump constitutes a part of the wiring pattern provided on the semiconductor device as an electrode pad part, and opens a part of an insulating film covering the electrode pad part on the electrode pad part,
The solder is formed in the opening in the shape of an oka to form a bump. As the shape of this opening, various shapes such as a quadrangle, an octagon and a circle are adopted, and usually the shape corresponds to the shape of the electrode pad portion.
【０００３】[0003]
【発明が解決しようとする課題】ところで、このような
構造の岡状半田バンプでは、岡状半田バンプの高さ並び
に体積は岡状半田バンプの底辺の長さや底面の直径に相
関があるため、開口部の形状が正方形、円形等のように
線及び点対称の形状をしている場合は、開口部の各辺に
おける岡状半田バンプの盛り上がり方が等しくなり、岡
状半田バンプの形状が均一化し、岡状半田バンプ間の高
さも揃う。しかし、開口部分の形状が長方形や楕円形の
ように線及び点対称の形状をしていない場合には、開口
部の各辺における岡状半田バンプの盛り上がり方が異な
るため、絶縁膜の開口部の形状で規定される岡状半田バ
ンプの形状は安定せず、又岡状半田バンプ間の高さも揃
わなくなる。By the way, in the Oka-shaped solder bump having such a structure, since the height and the volume of the Oka-shaped solder bump are correlated with the length of the bottom and the diameter of the bottom of the Oka-shaped solder bump, If the opening has a line or point symmetry such as a square or a circle, the swelling of the oka-shaped solder bumps on each side of the opening is the same and the shape of the oka-shaped solder bump is uniform. And the height between the oka-shaped solder bumps becomes even. However, when the shape of the opening is not a line or point symmetric shape such as a rectangle or an ellipse, the swelling of the Oka-shaped solder bumps on each side of the opening is different, and the opening of the insulating film is different. The shape of the Oka-shaped solder bumps defined by the shape is not stable, and the heights of the Oka-shaped solder bumps are not uniform.
【０００４】このため、このように開口部の周辺におけ
る岡状半田バンプの高さが揃わない状態で半導体装置の
接続を行うと、半田量が多い辺側で半田が周囲にはみ出
し易くなり、外部入出力電極間の短絡を引き起こす原因
となる。又、半田量が少ない辺側での接続を無理に行う
として半導体装置に過大な応力を加えることがあり、外
部入出力電極や絶縁膜を破壊等するおそれがある。本発
明の目的は、外部入出力電極間での短絡や、電極及び絶
縁膜の破壊を防止する外部入出力電極を備える半導体装
置を提供することにある。Therefore, if the semiconductor devices are connected in such a state that the heights of the oka-shaped solder bumps around the openings are not uniform, the solder easily squeezes out to the outside on the side where the amount of solder is large, This will cause a short circuit between the input and output electrodes. Further, excessive stress may be applied to the semiconductor device due to forced connection on the side with a small amount of solder, which may damage the external input / output electrodes or the insulating film. An object of the present invention is to provide a semiconductor device including an external input / output electrode that prevents a short circuit between the external input / output electrodes and destruction of the electrode and the insulating film.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体装置は、
岡状半田バンプを形成するために電極パッド部上に形成
される絶縁膜の開口部を、線及び点対称をした形状の複
数個の開口部で構成している。The semiconductor device of the present invention comprises:
The opening of the insulating film formed on the electrode pad portion to form the oka-shaped solder bump is composed of a plurality of openings having line and point symmetric shapes.
【０００６】[0006]
【作用】本発明によれば、複数個の開口部は線及び点対
称をした形状とされるため、各辺における岡状半田バン
プの高さが揃い、好適な接続が可能となる。According to the present invention, since the plurality of openings are formed in line and point symmetry, the heights of the oka-shaped solder bumps on each side are made uniform, and a suitable connection is possible.
【０００７】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明の半導体装置の第１実施例を示し、
（ａ）は平面図、（ｂ）はそのＡ−Ａ線縦断面図であ
る。半導体装置１はシリコン基板２の絶縁膜上にアルミ
ニウム配線の一部で電極パッド部３を形成し、その上に
窒化珪素膜４とポリイミド膜５を順次形成し、かつこれ
らの膜を開口して前記電極パッド部３を露呈させる開口
部７を設ける。このとき、電極パッド部３は長方形に形
成されているが、この電極パッド部３に縦横方向にそれ
ぞれ切欠き６を入れ電極パッド部３を複数個の正方形の
領域として画成する。但し、切欠きによって複数個の正
方形の領域を分離させることはない。そして、各正方形
の領域において前記開口部７をそれぞれ正方形に開口す
る。その上で、各開口部７に半田を岡状に形成し、複数
個の岡状半田バンプ８を形成する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 shows a first embodiment of the semiconductor device of the present invention,
(A) is a top view and (b) is the vertical sectional view on the AA line. In the semiconductor device 1, an electrode pad portion 3 is formed on a part of aluminum wiring on an insulating film of a silicon substrate 2, a silicon nitride film 4 and a polyimide film 5 are sequentially formed on the electrode pad portion 3, and these films are opened. An opening 7 is provided to expose the electrode pad portion 3. At this time, the electrode pad portion 3 is formed in a rectangular shape, but notches 6 are formed in the electrode pad portion 3 in the vertical and horizontal directions to define the electrode pad portion 3 as a plurality of square regions. However, the notches do not separate the plurality of square regions. Then, the opening 7 is opened in a square shape in each square area. Then, solder is formed in each opening 7 in an oka shape, and a plurality of oka solder bumps 8 are formed.
【０００８】この岡状半田バンプの製造工程を図２を用
いて説明すると。先ず、同図（ａ）のように、直径 125
mm、厚さ 0.6mmのシリコンウェハで構成されるシリコン
基板２の絶縁膜上にアルミニウムを厚さ１×10-3mmにな
るよう全面にスパッタ法により形成し、フォトリソグラ
フィ技術を用いて、長方形の電極パッド部３を形成する
と共に、この電極パッド部３に縦、横方向にそれぞれ切
欠き６を形成し、５×10-2mm角の電極パッド部が７×10
-2mmの間隔で２行３列にわたって配列するように形成す
る。The manufacturing process of the oka-shaped solder bump will be described with reference to FIG. First, as shown in Fig. (A), the diameter 125
of aluminum with a thickness of 1 × 10 −3 mm on the entire surface of the insulating film of the silicon substrate 2 composed of a silicon wafer having a thickness of 0.6 mm and a thickness of 0.6 mm by a photolithography technique to form a rectangular shape. The electrode pad portion 3 is formed, and notches 6 are formed in the electrode pad portion 3 in the vertical and horizontal directions, respectively, and the electrode pad portion of 5 × 10 −2 mm square is 7 × 10.
It is formed so as to be arrayed in 2 rows and 3 columns with an interval of -2 mm.
【０００９】続いて、同図（ｂ）のように、電極パッド
部３を含むシリコン基板２上にプラズマＣＶＤ法で厚さ
1.5×10-4mmの窒化珪素膜４を成長させる。更に、同図
（ｃ）のように、スピンコート法で窒化珪素膜４上に厚
さ８×10-3mmのポリイミド膜５を形成した後、アルミニ
ウム電極３上のポリイミド膜５を切欠き６を除いてフォ
トリソグラフィ技術を用いて４×10-2mm角の大きさに開
口する。その後、同図（ｄ）のように、ポリイミド膜５
をキュアした後、窒化珪素膜４をエッチングして、開口
径４×10-2mm角の開口部７を形成する。Then, as shown in FIG. 1B, the thickness is formed on the silicon substrate 2 including the electrode pad portion 3 by the plasma CVD method.
A silicon nitride film 4 of 1.5 × 10 −4 mm is grown. Further, as shown in FIG. 3C, after forming a polyimide film 5 having a thickness of 8 × 10 −3 mm on the silicon nitride film 4 by spin coating, the polyimide film 5 on the aluminum electrode 3 is cut out 6 Except for the above, a 4 × 10 −2 mm square opening is formed by using photolithography technology. After that, as shown in FIG.
After being cured, the silicon nitride film 4 is etched to form an opening 7 having an opening diameter of 4 × 10 -2 mm square.
【００１０】続いて、この半導体装置１の上面に銀を厚
さ５×10-4mmスパッタ法により形成し、これを図３に示
すような銀５％入りの共晶半田合金が入った超音波半田
付け槽９中に浸漬する。この超音波半田付槽９は、プロ
ペラ１０，半田合金噴出部１１、超音波ホーン１２、超
音波振動子１３、Ｎ2 流入口１４、酸化防止カバー１５
で構成され、前記シリコン基板２をシリコン基板ホルダ
１６を用いて浸漬させる。その後、窒素雰囲気中に遅滞
なく引き上げることにより、図１に示したような電極パ
ッド部３上の各々の開口部７部分に高さ１×10-2mmの岡
状半田バンプ８を形成することができる。Subsequently, silver was formed on the upper surface of the semiconductor device 1 by a sputtering method with a thickness of 5 × 10 -4 mm, and this was formed into a super alloy containing a eutectic solder alloy containing 5% silver as shown in FIG. Immerse in the sonic soldering bath 9. The ultrasonic soldering tank 9 includes a propeller 10, a solder alloy jetting portion 11, an ultrasonic horn 12, an ultrasonic vibrator 13, an N 2 inlet 14, and an oxidation prevention cover 15.
Then, the silicon substrate 2 is immersed using the silicon substrate holder 16. After that, by pulling up in a nitrogen atmosphere without delay, the oka-shaped solder bumps 8 having a height of 1 × 10 -2 mm are formed in each opening 7 portion on the electrode pad portion 3 as shown in FIG. You can
【００１１】この岡状半田バンプ８は図４に示すとお
り、底面の１辺の長さと高さがほぼ正比例しており、か
つ高さとばらつきが正比例していることから、切欠き６
がない半導体装置よりもバンプの高さが揃うことにな
る。そのため、図５に示すように、７×10-2mm厚の銅箔
１８上に厚さ４×10-3mm感光性レジスト１９を塗布し、
岡状バンプが接続されるところのみ開口させたポリイミ
ドベースの基板２０に、本発明の半導体装置１をフリッ
プしてベルト炉中で加熱すれば、岡状半田バンプ８をポ
リイミドベースの基板２０上の銅箔１８に接続すること
ができる。As shown in FIG. 4, the length of one side of the bottom surface of the oka-shaped solder bump 8 is almost directly proportional to the height, and the height and the variation are directly proportional to each other.
The bump height will be more uniform than that of a semiconductor device that does not have this. Therefore, as shown in FIG. 5, a photosensitive resist 19 having a thickness of 4 × 10 −3 mm is applied on a copper foil 18 having a thickness of 7 × 10 −2 mm,
If the semiconductor device 1 of the present invention is flipped and heated in a belt furnace on a polyimide-based substrate 20 that is open only where the oka-shaped bumps are connected, the oka-shaped solder bumps 8 on the polyimide-based substrate 20. It can be connected to the copper foil 18.
【００１２】このとき、岡状半田バンプ８は、正方形を
した開口部７に形成されるため、開口部７の各辺におけ
る高さが揃う状態となる。したがって、基板２０の銅箔
１８に接続する際に、開口部７の各辺においてそれぞれ
適正な接続を行うことができ、半田が周囲にはみ出るこ
とや、半田不足による過度の押圧力を必要とすることも
なく、回路の短絡を防止する一方で電極の破壊を防止す
ることが可能となる。At this time, since the oka-shaped solder bumps 8 are formed in the square openings 7, the heights of the sides of the openings 7 are the same. Therefore, when connecting to the copper foil 18 of the substrate 20, proper connection can be made on each side of the opening 7, and the solder is squeezed out to the surroundings and excessive pressing force is required due to insufficient solder. Without this, it becomes possible to prevent the short circuit of the circuit and the destruction of the electrode.
【００１３】図６は本発明の第２の実施例を示し、同
（ａ）は平面図、同図（ｂ）はそのＢ−Ｂ線縦断面図で
ある。この実施例では、半導体装置２１のシリコン基板
２２上にアルミニウム配線の一部で形成する電極パッド
部２３を１つの長方形として形成する。そして、この上
に窒化珪素膜２４とポリイミド膜２５を形成した上で、
一部にボリイミド膜２５のみを残して複数個の正方形を
した開口部２７を開設し、これら開口部２７内のみに岡
状半田バンプ２８を形成したものである。この場合ポリ
イミド膜２５の一部を桟２６として残すことで、開口部
２７を正方形に形成する。FIG. 6 shows a second embodiment of the present invention. FIG. 6 (a) is a plan view and FIG. 6 (b) is a vertical sectional view taken along the line BB. In this embodiment, the electrode pad portion 23 formed by a part of the aluminum wiring is formed on the silicon substrate 22 of the semiconductor device 21 as one rectangle. Then, after forming a silicon nitride film 24 and a polyimide film 25 on this,
A plurality of square-shaped openings 27 are opened while leaving only the polyimide film 25, and the oka-shaped solder bumps 28 are formed only in these openings 27. In this case, by leaving a part of the polyimide film 25 as the crosspiece 26, the opening 27 is formed in a square shape.
【００１４】この半導体装置の製造方法を図７に示す。
先ず、同図（ａ）のように、直径 125mm、厚さ 0.6mmの
シリコンウェハで構成されるシリコン基板２２上にアル
ミニウムを厚さ１×10-3mmになるよう全面にスパッタ法
により形成し、フォトリソグラフィ技術を用いて、入出
力部に 0.1mm×0.15mmの長方形をした電極パッド部２３
を形成する。続いて、同図（ｂ）のように電極パッド部
２３を含むシリコン基板２２上にプラズマＣＶＤ法で厚
さ 1.5×10-4mmの窒化珪素膜２４を成長し、フォトリソ
グラフィ技術を用いて窒化珪素膜２４を９×10-2mm角の
大きさに開口する。A method of manufacturing this semiconductor device is shown in FIG.
First, as shown in FIG. 3A, aluminum is formed on the entire surface by sputtering to a thickness of 1 × 10 −3 mm on a silicon substrate 22 composed of a silicon wafer having a diameter of 125 mm and a thickness of 0.6 mm. , Using the photolithography technology, the electrode pad section 23 with a 0.1mm × 0.15mm rectangular input / output section
To form. Then, a silicon nitride film 24 having a thickness of 1.5 × 10 −4 mm is grown on the silicon substrate 22 including the electrode pad portion 23 by the plasma CVD method as shown in FIG. The silicon film 24 is opened to a size of 9 × 10 -2 mm square.
【００１５】続いて、同図（ｃ）のようにスピンコート
法で電極パッド２３上を含む窒化珪素膜２４上に、厚さ
８×10-3mmのポリイミド膜２５を形成する。そして、同
図（ｄ）のようにフォトリソグラフィ技術を用いてポリ
イミド膜２５を開口し、４×10-2mm角の大きさの複数個
の開口部２７を形成する。このとき、ポリイミド膜は電
極パッド部２３上の桟２６を残すように開口部２７を形
成する。更に、ポリイミドカバー２５をキュアして硬化
させた後、第１実施例と同様に図３に示した超音波半田
付け槽９によって電極パッド部２３上の各々の開口部２
７部分に高さ１×10-2mmの岡状半田バンプ２８を形成す
る。Subsequently, as shown in FIG. 3C, a polyimide film 25 having a thickness of 8 × 10 −3 mm is formed on the silicon nitride film 24 including the electrode pads 23 by spin coating. Then, as shown in FIG. 3D, the polyimide film 25 is opened by using the photolithography technique to form a plurality of openings 27 having a size of 4 × 10 −2 mm square. At this time, the polyimide film has an opening 27 so as to leave the crosspiece 26 on the electrode pad portion 23. Further, after the polyimide cover 25 is cured and hardened, each opening 2 on the electrode pad 23 is formed by the ultrasonic soldering bath 9 shown in FIG. 3 as in the first embodiment.
Oka-shaped solder bumps 28 having a height of 1 × 10 -2 mm are formed on the seven portions.
【００１６】この実施例の構造では、ポリイミド膜２５
の表面高さが、電極パッド部２３上も窒化珪素膜２４上
もほぼ同一平面上となるため、図８に示すように、この
半導体装置をＴＡＢ（Tape Automated Bonding）テープ
のインナーリード２９に対して熱圧着法によるボンディ
ングを行っても、この際の応力はインナーリードを経て
岡状半田バンプ２８やポリイミド膜２５に加わり、そこ
で応力の緩和がなされてから電極パッド部２３や窒化珪
素膜膜２４に伝わるため、電極パッド部２３の破壊や窒
化珪素膜２４の破壊が有効に防止される。In the structure of this embodiment, the polyimide film 25 is used.
Since the surface height of the semiconductor device is substantially on the same plane both on the electrode pad portion 23 and on the silicon nitride film 24, this semiconductor device is mounted on the inner lead 29 of the TAB (Tape Automated Bonding) tape as shown in FIG. Even if the bonding is performed by the thermocompression bonding method, the stress at this time is applied to the oka-shaped solder bumps 28 and the polyimide film 25 via the inner leads, and after the stress is relaxed there, the electrode pad portion 23 and the silicon nitride film 24 are formed. Therefore, the destruction of the electrode pad portion 23 and the destruction of the silicon nitride film 24 are effectively prevented.
【００１７】[0017]
【発明の効果】以上説明したように本発明は、電極パッ
ド部上に形成される絶縁膜の開口部を、線及び点対称を
した形状の複数個の開口部で構成しているので、複数個
の開口部は線及び点対称をした形状とされるため、岡状
半田バンプの形状もこれに倣う形状とされ、岡状半田バ
ンプの各辺における高さが揃い、岡状半田バンプ形状の
均一化及び接続時の半導体装置へのダメージ低減を図
り、回路の短絡防止、及び装置の破壊防止をそれぞれ達
成することができる効果がある。As described above, according to the present invention, since the opening of the insulating film formed on the electrode pad portion is composed of a plurality of openings having line and point symmetry, a plurality of openings are formed. Since the individual openings have line and point symmetry, the shape of the oka-shaped solder bump is also made to follow this shape, and the height of each side of the oka-shaped solder bump is even. There are effects that uniformization and reduction of damage to the semiconductor device at the time of connection can be achieved, and circuit short circuit prevention and device destruction prevention can be achieved.
【図１】本発明の半導体装置の第１実施例を示し、
（ａ）は平面図、（ｂ）はそのＡ−Ａ線縦断面図であ
る。FIG. 1 shows a first embodiment of a semiconductor device of the present invention,
(A) is a top view and (b) is the vertical sectional view on the AA line.
【図２】図１の半導体装置の製造方法を示す断面図であ
る。FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor device of FIG.
【図３】岡状半田バンプを製造するための装置の構成図
である。FIG. 3 is a configuration diagram of an apparatus for manufacturing an oka-shaped solder bump.
【図４】本発明における岡状半田バンプの辺長と高さの
関係を示す図である。FIG. 4 is a diagram showing a relationship between a side length and a height of the oka-shaped solder bump in the present invention.
【図５】第１実施例の岡状半田バンプを用いた半導体装
置の搭載状態を示す断面図である。FIG. 5 is a cross-sectional view showing a mounted state of a semiconductor device using the oka-shaped solder bump of the first embodiment.
【図６】本発明の第２実施例を示し、（ａ）は平面図、
（ｂ）はそのＢ−Ｂ線縦断面図である。FIG. 6 shows a second embodiment of the present invention, (a) is a plan view,
(B) is the BB line longitudinal cross-sectional view.
【図７】図６の半導体装置の製造方法を示す断面図であ
る。7 is a cross-sectional view showing the method of manufacturing the semiconductor device of FIG.
【図８】第２実施例の岡状半田バンプを用いた半導体装
置の搭載状態を示す断面図である。FIG. 8 is a cross-sectional view showing a mounted state of a semiconductor device using the oka-shaped solder bump of the second embodiment.
１，２１ 半導体装置 ２，２２ シリコン基板 ３，２３ 電極パッド部 ４，２４ 窒化珪素膜 ５，２５ ポリイミド膜 ６ 切欠き ７，２７ 開口部 ８，２８ 岡状半田バンプ 1,21 Semiconductor device 2,22 Silicon substrate 3,23 Electrode pad part 4,24 Silicon nitride film 5,25 Polyimide film 6 Notch 7,27 Opening part 8,28 Oka solder bump
Claims (1)
を絶縁膜で覆い、この絶縁膜に開設した開口部内に露出
される前記電極パッド部上に半田を岡状に形成して外部
との電気的接続を行うための岡状半田バンプを設けた半
導体装置において、前記電極パッド部上に形成される絶
縁膜の開口部を、線及び点対称をした形状の複数個の開
口部で構成したことを特徴とする半導体装置。1. An electrode pad portion provided on a surface of a semiconductor device is covered with an insulating film, and solder is formed in an oka shape on the electrode pad portion exposed in an opening formed in the insulating film so as to be connected to the outside. In the semiconductor device provided with the oka-shaped solder bumps for electrical connection, the opening of the insulating film formed on the electrode pad portion is composed of a plurality of openings having line-shaped and point-symmetrical shapes. A semiconductor device characterized by the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3235659A JPH0555229A (en) | 1991-08-23 | 1991-08-23 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3235659A JPH0555229A (en) | 1991-08-23 | 1991-08-23 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0555229A true JPH0555229A (en) | 1993-03-05 |
Family
ID=16989297
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3235659A Pending JPH0555229A (en) | 1991-08-23 | 1991-08-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0555229A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8810521B2 (en) | 2005-08-02 | 2014-08-19 | Nlt Technologies, Ltd. | Liquid crystal display apparatus |
| CN104637906A (en) * | 2013-11-12 | 2015-05-20 | 英飞凌科技股份有限公司 | Solder bridging prevention structures for circuit boards and semiconductor packages |
-
1991
- 1991-08-23 JP JP3235659A patent/JPH0555229A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8810521B2 (en) | 2005-08-02 | 2014-08-19 | Nlt Technologies, Ltd. | Liquid crystal display apparatus |
| CN104637906A (en) * | 2013-11-12 | 2015-05-20 | 英飞凌科技股份有限公司 | Solder bridging prevention structures for circuit boards and semiconductor packages |
| US10085353B2 (en) | 2013-11-12 | 2018-09-25 | Infineon Technologies Ag | Solder bridging prevention structures for circuit boards and semiconductor packages |
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