JPH0555209A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH0555209A
JPH0555209A JP23566191A JP23566191A JPH0555209A JP H0555209 A JPH0555209 A JP H0555209A JP 23566191 A JP23566191 A JP 23566191A JP 23566191 A JP23566191 A JP 23566191A JP H0555209 A JPH0555209 A JP H0555209A
Authority
JP
Japan
Prior art keywords
wiring
integrated circuit
semiconductor integrated
circuit device
wirings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23566191A
Other languages
Japanese (ja)
Inventor
Giichi Shimizu
義一 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23566191A priority Critical patent/JPH0555209A/en
Publication of JPH0555209A publication Critical patent/JPH0555209A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve reliability against the disconnection of a wiring in a semiconductor integrated circuit device. CONSTITUTION:Wirings 4, 5 connecting a plurality of elements such as the bonding pads 1 of a semiconductor integrated circuit device and first and second resistors 2, 3 are composed of a plurality of wirings 4A, 4B, 5A, 5B connected in parallel. Accordingly, even when one wiring is disconnected, connection among the elements is ensured by the remaining wirings.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は信頼生に優れた半導体集
積回路装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having excellent reliability.

【0002】[0002]

【従来の技術】一般に半導体集積回路装置では、半導体
基板上に形成された複数の回路素子をアルミニウム等の
配線で相互接続して所要の回路を構成している。例え
ば、図2にその一例を示すように、ボンディングパッド
1と第1及び第2の抵抗体2,3を夫々アルミニウムや
多結晶シリコン等の配線7,8で相互に接続して回路を
構成している。6は配線7,8と抵抗体2,3とのコン
タクトである。
2. Description of the Related Art Generally, in a semiconductor integrated circuit device, a plurality of circuit elements formed on a semiconductor substrate are interconnected by wiring such as aluminum to form a required circuit. For example, as shown in FIG. 2 as an example, the bonding pad 1 and the first and second resistors 2 and 3 are connected to each other by wirings 7 and 8 made of aluminum or polycrystalline silicon to form a circuit. ing. Reference numeral 6 is a contact between the wirings 7 and 8 and the resistors 2 and 3.

【0003】[0003]

【発明が解決しようとする課題】このように従来の半導
体集積回路装置では、回路素子を夫々1本の配線で接続
を行っている。このため、配線を形成する際のリソグラ
フィ時に異物が付着して配線に欠けが生じて断線状態と
なった場合、或いは初期には電気的に導通していても通
電を続けるうちに金属マイグレーションにより断線が生
じた場合等に、回路素子間の導通が損なわれ、半導体集
積回路装置の機能不良を引起し、信頼性が低下されるこ
とになる。本発明の目的は、配線の断線に対する信頼性
を向上させた半導体集積回路装置を提供することにあ
る。
As described above, in the conventional semiconductor integrated circuit device, each circuit element is connected by one wiring. For this reason, when a wiring is formed and foreign matter adheres to the wiring during the lithography to cause a chipping of the wiring and the wiring is in a disconnected state, or even when the wiring is initially electrically connected, the wiring is disconnected due to metal migration while the current continues to flow. In the case of occurrence of such a problem, conduction between circuit elements is impaired, a malfunction of the semiconductor integrated circuit device is caused, and reliability is lowered. An object of the present invention is to provide a semiconductor integrated circuit device having improved reliability against disconnection of wiring.

【0004】[0004]

【課題を解決するための手段】本発明の半導体集積回路
装置は、複数の素子間を接続する配線を、複数本の並列
接続した配線で構成する。
In a semiconductor integrated circuit device according to the present invention, a wiring connecting a plurality of elements is composed of a plurality of wirings connected in parallel.

【0005】[0005]

【作用】本発明によれば、1本の配線が断線された場合
でも、残りの配線で素子間の接続を確保する。
According to the present invention, even if one wiring is broken, the remaining wiring ensures the connection between the elements.

【0006】[0006]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の半導体集積回路装置の一実施例の要
部の平面図である。同図において、1はボンディングパ
ッド、2,3は夫々第1及び第2の抵抗体である。そし
て、これらボンディングパッド1と第1及び第2の抵抗
体2,3をアルミニウム配線4,5によって夫々接続し
ている。ここで、前記ボンディングパッド1と第1の抵
抗体2との間を接続する配線4は並列接続した2本のア
ルミニウム配線4A,4Bで構成している。同様に、第
1の抵抗体2と第2の抵抗体3との間を接続する配線5
は並列接続した2本のアルミニウム配線5A,5Bで構
成している。6は各アルミニウム配線4,5と抵抗体
2,3とのコンタクトである。この場合、並列接続され
た各アルミニウム配線4A,4B,5A,5Bは、半導
体集積回路装置のレイアウトで許される限り両配線が接
近されないように形成する。又、多層配線構造を採用す
る半導体集積回路装置では、並列接続された各アルミニ
ウム配線は異なる層の配線で構成される。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a plan view of a main part of an embodiment of a semiconductor integrated circuit device of the present invention. In the figure, 1 is a bonding pad, and 2 and 3 are first and second resistors, respectively. The bonding pad 1 and the first and second resistors 2 and 3 are connected by aluminum wirings 4 and 5, respectively. Here, the wiring 4 connecting the bonding pad 1 and the first resistor 2 is composed of two aluminum wirings 4A and 4B connected in parallel. Similarly, the wiring 5 connecting between the first resistor 2 and the second resistor 3
Is composed of two aluminum wirings 5A and 5B connected in parallel. Reference numeral 6 is a contact between the aluminum wirings 4 and 5 and the resistors 2 and 3. In this case, the aluminum wirings 4A, 4B, 5A and 5B connected in parallel are formed so that the two wirings are not close to each other as long as the layout of the semiconductor integrated circuit device permits. Further, in the semiconductor integrated circuit device adopting the multilayer wiring structure, the aluminum wirings connected in parallel are composed of wirings in different layers.

【0007】この構成によれば、ボンディングパッド
1、第1及び第2の抵抗体2,3の夫々の間は夫々2本
のアルミニウム配線4A,4B,5A,5Bで電気接続
されるため、仮に一方のアルミニウム配線に欠陥が生じ
て断線されても、他方のアルミニウム配線で各素子の接
続が確保される。この場合、並列接続された各アルミニ
ウム配線は、可及的に離れて形成され、又異なる配線層
として形成されることで、各アルミニウム配線が同時に
断線状態とされる確率は極めて小さくなり、各素子の接
続を確保する確率は極めて高いものとなる。これによ
り、半導体集積回路装置の信頼性を高めることが可能と
なる。
According to this structure, the bonding pad 1 and the first and second resistors 2 and 3 are electrically connected to each other by the two aluminum wirings 4A, 4B, 5A and 5B. Even if a defect occurs in one of the aluminum wirings and the wiring is broken, the connection of each element is secured by the other aluminum wiring. In this case, since the aluminum wirings connected in parallel are formed as far apart as possible and are formed as different wiring layers, the probability that the aluminum wirings will be disconnected at the same time becomes extremely small, and The probability of securing the connection is extremely high. As a result, the reliability of the semiconductor integrated circuit device can be improved.

【0008】尚、2本のアルミニウム配線を並列接続す
ることで、各素子間の電気抵抗を低減させることも可能
である。又、前記実施例はアルミニウムで配線を構成し
た例を示しているが、多結晶シリコン或いは高融点金属
等で配線を構成する場合でも同じある。更に、レイアウ
トの余裕があれば、3本以上の配線を並列接続してもよ
い。
By connecting two aluminum wirings in parallel, it is possible to reduce the electric resistance between the respective elements. Further, although the above embodiment shows an example in which the wiring is made of aluminum, the same applies to the case where the wiring is made of polycrystalline silicon or refractory metal. Furthermore, if there is a layout margin, three or more wirings may be connected in parallel.

【0009】因みに、素子間の配線が1本のときの不良
率を 100ppm とすると、素子間の配線を2本にしたとき
の不良率は(10-4)2=0.01ppm となる。又、素子間の配
線を3本にしたときの不良率は(10-4)3=0.000001ppm
となる。
Incidentally, assuming that the defect rate when the number of wirings between the elements is one is 100 ppm, the rate of failure when the number of wirings between the elements is two is (10 −4 ) 2 = 0.01 ppm. In addition, the defect rate when the number of wires between elements is 3 is (10 -4 ) 3 = 0.000001ppm
Becomes

【0010】[0010]

【発明の効果】以上説明したように本発明は、複数の素
子間を複数本の並列接続した配線で接続しているので、
1本の配線が断線された場合でも、残りの配線で素子間
の接続を確保し、半導体集積回路装置の信頼性を高める
ことができる効果がある。
As described above, according to the present invention, since a plurality of elements are connected by a plurality of wirings connected in parallel,
Even if one wiring is broken, there is an effect that the connection between the elements can be secured by the remaining wiring and the reliability of the semiconductor integrated circuit device can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体集積回路装置の一実施例の要部
の平面図である。
FIG. 1 is a plan view of an essential part of an embodiment of a semiconductor integrated circuit device of the present invention.

【図2】従来の半導体集積回路装置の一部の平面図であ
る。
FIG. 2 is a plan view of a part of a conventional semiconductor integrated circuit device.

【符号の説明】[Explanation of symbols]

1 ボンディングパッド 2 第1の抵抗体 3 第2の抵抗体 4(4A,4B),5(5A,5B) アルミニウム配
1 Bonding Pad 2 First Resistor 3 Second Resistor 4 (4A, 4B), 5 (5A, 5B) Aluminum Wiring

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体集積回路装置に形成した複数の素
子間を接続する配線を、複数本の並列接続した配線で構
成したことを特徴とする半導体集積回路装置。
1. A semiconductor integrated circuit device, wherein a wiring connecting a plurality of elements formed in the semiconductor integrated circuit device is composed of a plurality of wirings connected in parallel.
JP23566191A 1991-08-23 1991-08-23 Semiconductor integrated circuit device Pending JPH0555209A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23566191A JPH0555209A (en) 1991-08-23 1991-08-23 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23566191A JPH0555209A (en) 1991-08-23 1991-08-23 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0555209A true JPH0555209A (en) 1993-03-05

Family

ID=16989326

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23566191A Pending JPH0555209A (en) 1991-08-23 1991-08-23 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0555209A (en)

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