JPH0554638A - Memory device - Google Patents

Abstract

PURPOSE:To provide present a memory device which increases the amplification speed of sense amplifiers for rewrite and increases the transfer operation speed. CONSTITUTION:Second transfer gates 7-1 and 7-2 which connect busses L11 and L12 and busses L21 and L22 are closed at the time of data transfer operation to stop driving of busses L21 and L22 due to data registers 5-1 and 5-2. Data appearing on busses L21 and L22 is selectively transferred to a pair of bit lines BL1 and BL2 by a signal DTSW, and thereafter, sense amplifiers in a sense amplifier array 3 are driven by a signal SADR to update and rewrite data in a memory cell array. Since data can be transferred without driving bit lines by data registers, the potential difference of updated bit lines is reduced, and the amplification speed of sense amplifiers for rewrite is increased, and thereby, the transfer operation speed is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory having a function of serially writing data.

[0002]

2. Description of the Related Art In an image memory for storing continuous high-speed data such as images, a structure is used in which data input by a serial data register is held and then transferred to a memory cell array. In such a configuration, in order to write the input image data to an arbitrary area of the memory device, it is necessary to have a function of transferring only an arbitrary bit output of the serial data register to the memory cell array.

FIG. 3 shows the configuration of a memory device using the conventional method. Here, the operation of fetching the serial data from the serial input SI and writing it in the memory cell array 1 will be described. As for the operation sequence, first, the holding operation of the serial data SI input from the outside of the memory device is performed.
Then, a data transfer operation to memory cell array 1 is performed.

First, the operation of holding the serial data SI of the memory device will be described. FIG. 4 shows the timing of each signal in the operation.

In FIG. 4, data a and b are input from the input SI.
Is serially input and is held in the data registers 5-1 and 5-2 of FIG. 3 by the serial clock SCLK. Then, complementary data a and / a, b and / b respectively appear on the buses L11 and L12. In this way, the data serially input from SI is held in the data register array 5 one after another.

Next, the data transfer operation from the data register array 5 to the memory cell array 1 will be described. Figure 5
Shows the timing of each signal in the operation.

A row address Row is given at the timing of T1 and added to the row decoder 2. After that, the selected word line WL rises at the timing of T2, so that the row data in the memory cell array 1 is selected. Then, in synchronization with the timing of T2, the data stored in the memory cells 1-1 and 1-2 appear as a minute potential difference on the bit line pair BL1 and BL2, respectively.

On the other hand, the data a, b held in the data registers 5-1 and 5-2 in the data register array 5
Are complementary data a and / a, b on buses L11, L12.
And / b respectively. Then, by the signal DTSW generated at the timing of T3, the buses L11, L12
The data a and b appearing above are respectively set to the bit line pair BL.
1 and BL2 are selectively connected. Here, the means for transferring only the arbitrary bit output of the data register 5 to the memory cell array 1 is realized by designating the logical value of each bit of the signal DTSW. In the example of FIG. 5, the transfer gate 4-1 is conductive and the transfer gate 4-2 is cut off. Therefore, the data held in the data register 5-1 through the transfer gate 4-1 appears in the bit line pair BL1 in synchronization with the timing of T3. In the figure, the data stored in the memory cell 1-1 is opposite to the newly written data a and / a, and the data on the bit line pair BL1 is inverted by the signal DTSW.
Then, since the bit line pair BL1 is driven by the data register 5-1, the potential difference between the bit line pair BL1 gradually increases thereafter. On the other hand, since the transfer gate 4-2 is cut off, the bit line pair BL2 has the memory cell 1-2.
It is constant with a very small potential according to the data.

After that, when the sense amplifier drive signal SADR rises at the timing of T4, each sense amplifier in the sense amplifier array 3 is driven, and the bit line pair BL.
1, the signal on BL2 is amplified. Then, the memory cell 1-1 is updated to the input data a after the time t1 from the timing T4, and the memory cell 1-2 is rewritten with the conventional data c after the time t2 from the timing T4. Writing is performed.

In the arrangement of sense amplifiers in a large capacity memory device, two adjacent sense amplifiers are connected as a set to the sense amplifier drive signal SADR. This is to realize high-density arrangement by sharing the wiring between the two sense amplifiers.

FIG. 6 is a connection diagram showing the arrangement of the sense amplifiers 3-1 and 3-2 and the wiring to the sense amplifier drive signal SADR. In the figure, the wiring from the sense amplifier drive signal SADR to both sense amplifiers 3-1 and 3-2 shows that the wiring xy and the wiring zu are shared in the layout. r1 and r2 are the layout
The parasitic resistance is generated by the wirings x-y and u-z of the SADR signal line shared by the sense amplifiers 3-1 and 3-2. For example, the contact resistance between the SADR signal line and the common lines x-y and u-z. Or the wiring resistance of the common lines xy and uz.

In the conventional configuration shown in FIG. 3, both the sense amplifiers 3-1 and 3 at the timing T4.
When driving -2, the bit line pair BL1 is
Since it is driven by the data register 5-1, the difference in potential difference is larger than that in the case of the bit line pair BL2. In this case, in FIG. 6, a large amount of the charging current i1 of the sense amplifier 3-1 flows at a timing earlier than the charging current i2 of the sense amplifier 3-2 due to the circuit operation, and the parasitic resistance r1 of the common wiring x-y. Amplification capability of the sense amplifier is lowered due to the voltage drop at 2, and the amplification of the sense amplifier 3-2 having a small potential difference between the bit line pair BL is delayed. In addition, the influence of the discharge current i3 of the sense amplifier 3-1 on the discharge current i4 of the sense amplifier 3-2 due to the parasitic resistance r2 between the wiring z and u is also a cause of delaying the amplification of the sense amplifier 3-2. Become.

[0013]

As described above, in the conventional configuration, in the data transfer from the serial data register to the memory cell array, the bit line pair of the bit updated by the data transfer is driven by the data register. However, the amplification of the sense amplifier that performs rewriting without data transfer is delayed, which is a problem in increasing the speed of the transfer operation.

It is an object of the present invention to provide a memory device capable of improving the amplification speed of a sense amplifier for rewriting and speeding up a transfer operation.

[0015]

The memory device of the present invention comprises:
In order to solve the above problems, a memory cell array, a row decoder for selecting row data from the memory cell array, a sense amplifier for amplifying the selected row data, and dynamically holding data A dynamic data holding circuit, a serial data register for holding serially input data, a first data transfer gate for transferring data from the dynamic data holding circuit to a bit line, and a serial data register A second data transfer gate for transferring data to the dynamic data holding circuit is provided.

[0016]

According to the present invention, the serially input data is transferred to the dynamic data holding circuit according to the above-mentioned configuration, so that the data transfer to the memory cell can be performed without driving the bit line by the serial data register of the transfer source. Since it is possible to reduce the potential difference between the bit line pairs that are updated at the time of data transfer and improve the amplification speed of the sense amplifier that performs rewriting,
The transfer operation can be speeded up.

[0017]

1 shows the structure of a memory device according to an embodiment of the present invention. Here, the operation of fetching the serial data from the serial input SI and writing it in the memory cell array 1 will be described. Similar to the conventional example, the operation sequence is such that the holding operation of the serial data SI input from the outside of the memory device is performed first, and then the data transfer operation to the memory cell array 1 is performed.

First, the serial data holding operation of the memory device is exactly the same as the conventional example.

Next, the data transfer operation of the memory device according to the embodiment of the present invention will be described. FIG. 2 shows the timing of each signal in the operation.

A row address Row is given at the timing of T1 and added to the row decoder 2. After that, the selected word line WL rises at the timing of T2, so that the row data in the memory cell array 1 is selected. Then, in synchronization with the timing of T2, the data stored in the memory cells 1-1 and 1-2 appear as a minute potential difference on the bit line pair BL1 and BL2, respectively.

On the other hand, the data a, b held in the data registers 5-1 and 5-2 in the data register array 5
Are complementary data a and / a, b on buses L11, L12.
And / b respectively. The transfer control signal CHSW is a signal for controlling conduction and interruption of the second transfer gate 7.
By making the transfer gates 7-1 and 7-2 conductive by this CHSW, the buses L11 and L12 are respectively connected to the bus L.
21 and L22, and the same data as that of the buses L11 and L12 appears on the buses L21 and L22. T
At timing 3, the individual transfer gates in the second transfer gate 7 are all cut off. By this operation, the data of the data registers 5-1 and 5-2 are transferred to the dynamic data holding circuits 6-1 and 6-2, respectively, and the buses L21 and L22 of the data registers 5-1 and 5-2 are respectively transferred. Shut off the drive.

As the present embodiment, the case where each of the dynamic data holding circuits 6-1 and 6-2 of FIG. 1 is composed of one capacitance element is shown.

At timing T4, the buses L21 and L2 are
The data a and b appearing above 2 are selectively connected to the bit line pair BL1 and BL2 by the signal DTSW. Here, as in the conventional example, conduction or interruption of each transfer gate in the first transfer gate 4 is realized by designating a logical value of each bit of the signal DTSW. In the example of FIG. 2, the transfer gate 4-1 is conductive and the transfer gate 4-2 is cut off as in the conventional example. Therefore, bit line pair BL1
The transfer gate 4-1 in synchronization with the timing of T4.
Through, the data held in the dynamic data holding circuit 6-1 appears. Here, since the dynamic data holding circuit 6-1 is composed of a capacitive element, the minute potential difference between the bit line pair BL1 after the transfer gate 4-1 is turned on depends on the capacitance of the dynamic data holding circuit 6-1 and the memory. It is uniquely determined by the capacitance of the cell 1-1 and the wiring capacitance of the bit line pair BL1. Then, if the capacity of the dynamic data holding circuit 6-1 is made larger than the capacity of the memory cell 1-1, as shown in FIG. 2, the data stored in the memory cell 1-1 and the data a to be written have opposite phases. In case of
The data on the bit line pair BL1 is inverted in synchronization with the timing T4, and has a potential difference corresponding to the data a to be written.
The bit line pair BL1 keeps the potential difference constant because the transfer gate 7-1 is cut off. On the other hand, since the transfer gate 4-2 is cut off, the bit line pair BL2 is kept constant as a minute potential according to the data of the memory cell 1-2.

After that, when the sense amplifier drive signal SADR rises at the timing of T5, each sense amplifier in the sense amplifier array 3 is driven, and the bit line pair B
The signals on L1 and BL2 are amplified. Then, the memory cell 1-1 is updated to the input data a after the time t1 from the timing of T5, and the memory cell 1-2 is rewritten with the conventional data c after the time t2 from the timing of T5. Writing is performed.

In the configuration of the embodiment according to the present invention, when the serial data is transferred through the first transfer gate 4, the bit line pair BL1 is driven by the dynamic data holding circuit 6-1. The small potential difference is kept constant. Therefore, the difference between the timing and the current value of both the charging current i1 of the sense amplifier 3-1 and the charging current i2 of the sense amplifier 3-2 shown in FIG. Is improved compared to. The same applies to the discharge current i3 of the sense amplifier 3-1 and the discharge current i4 of the sense amplifier 3-2.

[0026]

As described above, according to the present invention,
Since the data transfer can be performed without driving the bit line by the serial data register, the potential difference of the updated bit line can be reduced, and the amplification speed of the sense amplifier for rewriting can be improved. I was able to speed up.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a memory device according to an embodiment of the present invention.

FIG. 2 is a timing chart of a data transfer operation of the memory device of the same embodiment.

FIG. 3 is a block diagram of a conventional memory device.

FIG. 4 is a timing diagram of a serial data holding operation of the memory device.

FIG. 5 is a timing diagram of a data transfer operation of a conventional memory device.

FIG. 6 is a drive signal connection diagram in the sense amplifier.

[Explanation of symbols]

 1 memory cell array 1-1, 1-2 memory cell 2 row decoder 3 sense amplifier array 3-1, 3-2 sense amplifier 4 first transfer gate 4-1 and 4-2 transfer gate 5 data register array 5-1, 5-2 Data register 6 Dynamic register array 6-1, 6-2 Dynamic register 7 Second transfer gate 7-1, 7-2 Transfer gate

Claims (2)

[Claims] 1. A memory cell array, a row decoder for selecting row data from the memory cell array, a sense amplifier for amplifying the selected row data, and dynamic data holding for dynamically holding data. A circuit, a serial data register for holding serially input data, a first data transfer gate for transferring data from the dynamic data holding circuit to a bit line, and data from the serial data register A memory device having a second data transfer gate for transferring to a dynamic data holding circuit. 2. The memory device according to claim 1, wherein the dynamic data holding circuit is composed of a capacitive element.