JP2634916B2 - Semiconductor memory - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a semiconductor memory, and more particularly, to a semiconductor memory having a flash write per bit function.

[Conventional technology]

Conventionally, in this type of semiconductor memory, when writing the same information to all the memory cells connected to a selected word line (hereinafter referred to as flash writing), the digit line level is controlled by a driver circuit, and flash writing is not performed. Digit lines (hereinafter referred to as flash write mask) transmit the signal amount of a memory cell to these digit lines, amplify them by a sense amplifier, and perform rewriting (refreshing).

This flash write and refresh were performed simultaneously.

[Problems to be solved by the invention]

In the above-described conventional semiconductor memory, flash writing in which the level of the digit line greatly changes and refresh in which the level of the digit line slightly changes according to the signal amount of the memory cell are performed simultaneously, and the digit line at the time of refreshing is in a floating state. So
When these digit lines are adjacent to each other, due to the parasitic capacitance between the digit lines, a change in the level of the digit line to be flash-written affects the level of the digit line being refreshed, thereby preventing an operation of correctly refreshing information. There is a disadvantage that.

To avoid this, separate the digit line area for flash writing and the digit line for refreshing,
There is also a disadvantage that the number of circuits for controlling these increases, resulting in an increase in chip size.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory that can be correctly refreshed without being affected by parasitic capacitance even if a digit line to be flash-written and a digit line to be flash-masked and refreshed are adjacent to each other, thereby reducing the chip size. Is to provide.

[Means for solving the problem]

The semiconductor memory of the present invention includes a plurality of word lines, a plurality of memory cells connected to each of the word lines, and a plurality of first and second memory cells connected to predetermined ones of the memory cells and transmitting complementary signal pairs. A second digit line pair and a plurality of first digit lines provided corresponding to the first and second digit line pairs and turned on / off by a first control signal to control transmission of mutually complementary input signal pairs. A flash write register provided with a plurality of capacitive elements having a predetermined capacity for temporarily holding signals from the corresponding transfer gates, respectively, and the first digit A signal provided between the line pair and the corresponding capacitive element, which is turned on / off by a second control signal and held by the capacitive element, And a plurality of second transfer gates, each of which controls transmission to a corresponding one of the digit line pairs, and is turned on / off by a third control signal provided between each of the second digit line pairs and the corresponding one of the capacitive elements. A plurality of third transfer gates for controlling transmission of signals held in the capacitive element to these second digit line pairs.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In this embodiment, a plurality of word lines (WL1) and a plurality of memory cells (NC1 to MC1) connected to each word line (WL1) are used.
4) and predetermined memory cells MC1, MC3,
A plurality of first and second pairs of digit lines DL1, ▲ ▼, DL3, ▲ connected to MC2, MC4 and transmitting mutually complementary signal pairs
▼, DL2, ▲ ▼, DL4, ▲ ▼ and these first and second digit line pairs DL1, ▲ ▼, ~, D
L4, ▲ ▼, which are provided corresponding to the first connection signal Φ ₁ to be turned on / off by the first connection signal Φ ₁ and are mutually complementary input signal pairs DT, ▲
A plurality of first transfer gates T11 for controlling transmission
To T18, a flash write register including a plurality of capacitive elements C1 to C8 provided in correspondence with the respective transfer gates T11 to T18 and temporarily holding signals from the corresponding transfer gates, and a first digit line. Capacitor C corresponding to DL1, ▲ ▼, DL3, ▲ ▼
1, C2, C5, and C6, which are turned on / off by a _second control signal Φ2, and the signals held in these capacitive elements C1, C2, C5, and C6 are transferred to these first digit line pairs. Transfer gates T21 to T24 for controlling transmission to
And each second digit line pair DL2, ▲ ▼, DL4, ▲
▼ and the corresponding capacitance elements C3, C4, C7, C8 are provided and turned on / off by a _third control signal Φ3, and the signals held in these capacitance elements C3, C4, C7, C8 are A plurality of third transfer gates T31 to T34 for controlling transmission to the second digit line pairs, respectively;
Sense amplifiers SA1 to SA4 which are provided corresponding to ▼ to DL4 and ▲ ▼ to amplify and output signals of these digit line pairs DL1, ▲ to DL4 and ▲ ▼, and each digit line pair DL1, ▲ to DL4 , ▲ ▼ and these digit line pairs DL1, ▲ ▼ ~ DL4, ▲
▼ has a digit line pair level control circuit DC1~DC4 for controlling the supply of the balance and the reference voltage V _R from the configuration having.

 Next, the operation of this embodiment will be described.

FIG. 2 is a timing chart of signals of respective parts for explaining the operation of this embodiment.

First, the first control signal Φ _{1 is set} to a high level,
The information (DT, ▲ ▼) to be flash-written by the transfer gates T11 to T18 is stored in the flash write register 1.
After conveyed to the capacitors C1~C8 of turning off the transfer gate T11~T18 the first control signal [Phi ₁ to a low level.

Next, after the operation of the digit line level control circuits DC1 to DC4 is stopped, the selected word line WL1 is set to the selected level, and the digit line pair DL2, ▲ ▼, DL4, ▲
The third control signal Φ _{3 is set} to a high level to flash-write ▼.

Then in a floating state at the reference voltage V _R (period T) the digit line pairs DL1, ▲ ▼, DL3, ▲
In ▼, a difference (A) in signal amount between the memory cells MC1 and MC3 occurs, and the digit line pair DL2, ▲ ▼, DL4, ▲
▼ indicates the capacitive elements C3, C4, C of the flash write register 1.
A signal amount difference (B) occurs due to 7, C8.

At this time, the signals of the capacitors C3, C4, C7, C8 are
By properly selecting the capacitance values of 1 to C8, the high level side immediately drops to a level slightly higher than the high level side of the flash write masked digit line pair DL1, ▲ ▼, DL3, ▲ ▼, these digit line pair DL1, ▲ ▼ ~DL4, ▲ ▼ since the difference between the levels of small, they are never influence each other by the parasitic capacitance C _S.

Thereafter, the sense amplifier SA1~SA4 activated by sense amplifier activation signals [Phi ₄ goes high, the digit line pairs DL1, ▲ ▼, DL3, ▲ ▼ the memory cells M
C1 and MC3 are rewritten (refreshed) with these signals, and digit line pairs DL2, ▲ ▼, DL4, ▲
Flash-write the memory cells MC2 and MC4 in ▼.

Also, by switching the levels of the control signals Φ ₂ and Φ ₃ , the memory cell to be refreshed and the memory cell to be flash-written can be switched.

〔The invention's effect〕

As described above, according to the present invention, the first transfer gate is turned off after the signal for flash writing is transmitted to the capacitor having a predetermined capacitance by the first transfer gate, and then the capacitor is connected to the digit line. The effect of the parasitic capacitance can be eliminated even if the digit line for flash writing and the digit line for refreshing are adjacent to each other, so that the digit line for flash writing and the flash write mask (refresh And digit lines can be mixed and layout design can be performed, and the control circuit can be reduced in size, so that the chip size can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 4 is a timing chart of signals of respective parts for explaining the operation of the embodiment shown in the figure. 1 ...... flash write register, C1 to C8 ...... capacitive element, C _S ...... parasitic capacitance, DC1 to DC4 ...... digit line level control circuit, DL1, ▲ ▼ ~DL4, ▲ ▼ ...... digit line pair, MC1～ MC4 memory cell, SA1 to SA4 sense amplifier, T11 to T18, T21 to T24, T31 to T34 transfer gate, WL1 word line.

Claims (2)

(57) [Claims] 1. A plurality of word lines, a plurality of memory cells connected to each word line, and a plurality of first and second memory cells connected to predetermined ones of the memory cells and transmitting complementary signal pairs. And a plurality of first transfer circuits provided corresponding to the first and second digit line pairs and turned on / off by a first control signal to control transmission of complementary input signal pairs. A gate, a flash write register provided in correspondence with each of the transfer gates, and provided with a plurality of capacitance elements having a predetermined capacity for temporarily holding signals from the corresponding transfer gates; And turned on and off by a second control signal provided between the first capacitor and the corresponding capacitance element, and the signals held in these capacitance elements are converted into the first digit. A plurality of second transfer gates, each of which controls transmission to a corresponding one of the line pairs, and a capacitor which is provided between each of the second digit line pairs and a corresponding one of the capacitors, and which is turned on / off by a third control signal and And a plurality of third transfer gates for controlling transmission of the signal held in the second digit line pair to the second digit line pair, respectively. 2. The first transfer gate is turned off before at least one of the second and third transfer gates is turned on, and at least one of the second and third transfer gates is turned off. When one is turned on and the signal of the corresponding capacitive element is transmitted to the corresponding digit line pair, the high level side of these digit line pair is the high level side of the digit line pair when the signal of the corresponding memory cell is transmitted. The capacitance value of each of the capacitance elements is set so as to have a slightly higher level.
The semiconductor memory according to any one of the preceding claims.