JP3088595B2 - Semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory having a function of writing data serially.

[0002]

2. Description of the Related Art In an image memory for storing continuous high-speed data such as images, a configuration is used in which input data is held by a serial data register and then transferred to a memory cell. In such a configuration, a function of transferring only an arbitrary bit output of the serial data register to the memory cell is necessary to write the input image data to an arbitrary area of the memory.

Hereinafter, a semiconductor memory using a conventional method will be described with reference to the drawings.

FIG. 3 shows a configuration of a conventional semiconductor memory. As shown in FIG. 3, the conventional semiconductor memory has memory cells 1-1, 1-2,... And dummy cells 7-1, 7-.
Memory cell array 1 having 2, 7-3, 7-4,.
, A row decoder 2, and sense amplifiers 3-1, 3-2,
, A transfer gate array 4 consisting of transfer gates 4-1 4-2,... As data transfer means, and serial data registers 5-1 5-1.
, And a mask register array 6 composed of mask registers 6-1, 6-2,.

[0005] One bit line of the bit line pair BL1 is connected to the memory cell 1-1 and the dummy cell 7-1, and the other bit line is connected to the dummy cell 7-2. One bit line is memory cell 1
-2 and the dummy cell 7-3, and the other bit line is connected to the dummy cell 7-4. The row address signal ROW is input to the row decoder 2, the word line WL is connected to the memory cells 1-1 and 1-2, the dummy word line DWL0 is connected to the dummy cells 7-1 and 7-3, and the dummy word Line DWL1 is connected to dummy cells 7-2, 7-
4 is connected. The sense amplifier drive signal SADR is input to the sense amplifiers 3-1 and 3-2. In addition,
D1 and D2 are buses, SI is serial data, MI is mask data, SCLK is a serial clock, DT1 and DT
2 indicates a signal, and VCP indicates a potential.

Here, the operation of taking in the serial data SI from a serial input (not shown) and writing it into the memory cell array 1 will be described. As an operation order, first, an operation of holding serial data SI and mask data MI input from outside the memory is performed, and then, a data transfer operation to memory cell array 1 is performed.

First, the operation of holding the serial data SI and the mask data MI will be described.

FIG. 4 shows the timing of each signal in the holding operation. As shown in FIG. 4, with respect to the serial data SI, data a and b are serially input from a serial input, and the serial data S
These are held in the serial data registers 5-1 and 5-2 in FIG. Then, complementary data a is provided on buses D1 and D2.
And / a, b and / b respectively appear.

In this manner, data input serially from the serial input is held in the serial data register array 5 one after another.

Similarly, with respect to the mask data MI, similarly, data is serially input from a serial input, and the mask register MI of FIG.
1, 6-2. In this case, since the bit line pair BL1 is considered as the update side and the bit line pair BL2 is considered as the rewrite side, the signal DT1 is set high and the signal DT2 is set low.

Next, a data transfer operation from the serial data register array 5 to the memory cell array 1 will be described.

FIG. 5 shows the timing of each signal in the data transfer operation. As shown in FIG. 5, a row address signal ROW is supplied at a timing T1 and applied to the row decoder 2. Thereafter, at the timing of T2, the dummy word line DWL0 of the dummy cells 7-1 and 7-3 corresponding to the selected memory cells 1-1 and 1-2 is set to low.

At the timing of T3, the selected word line WL rises, so that the row data in the memory cell array 1 is selected. Then, in synchronization with this timing, the data stored in the memory cells 1-1 and 1-2 appears on the bit line pairs BL1 and BL2 as an initial difference potential, respectively.

On the other hand, the data a and b stored in the data registers 5-1 and 5-2 appear on the buses D1 and D2 as complementary data a and / a, b and / b, respectively. At the timing of T4, the data a and b appearing on the buses D1 and D2 are respectively transferred to the bit line pairs BL1 and B2.
Selectively connect to L2. At this time, the mask register 6-
Since 1 is high and the mask register 6-2 is low, only the signal DT1 becomes high at the same timing, the transfer gate 4-1 becomes conductive, and the transfer gate 4-2 is cut off. As a result, the data a held in the serial data register 5-1 through the transfer gate 4-1 appears on the bit line pair BL1 in synchronization with the timing of T4. FIG.
In this case, the data held in the memory cell 1-1 and the newly written data a and / a have opposite phases, and the data on the bit line pair BL1 is inverted by the signal DT1.
The bit line pair BL1 is connected to the serial data register 5
Since it is driven by -1, the potential difference gradually increases. On the other hand, the bit line pair BL2 is connected to the transfer gate 4-2.
Is interrupted, so that the initial difference potential remains constant.

Thereafter, at the timing of T5, the sense amplifier drive signal SADR drives the sense amplifiers 3-1 and 3-2, and the signals on the bit line pair BL1 and BL2 are amplified. The memory cell 1-1 is updated to the data a after the time t1 from the timing of T5, and the memory cell 1-2 is rewritten with the conventional data c after the time t2 from the timing of T5. Is performed.

[0016]

However, in the conventional semiconductor memory, in the data transfer operation, the bit line pair to be updated is driven by the serial data register to increase the difference potential, so that rewriting is performed. There is a problem in that the amplification of the sense amplifier is slowed down and the transfer operation is speeded up.

Here, the cause of the above problem will be considered.

In the arrangement of sense amplifiers in a large-capacity semiconductor memory, two adjacent sense amplifiers are paired and connected to a sense amplifier drive signal line for supplying a sense amplifier drive signal SADR. This is for realizing high-density arrangement by sharing wiring between two sense amplifiers.

FIG. 6 shows the arrangement of the sense amplifiers 3-1 and 3-2 and the connection between the sense amplifiers 3-1 and 3-2 and the sense amplifier drive signal line for supplying the sense amplifier drive signal SADR. As shown in FIG. 6, the sense amplifiers 3-1 and 3-2 share the wiring xy and the wiring zu on the layout in connection with the sense amplifier drive signal line. r1 and r2 are wirings xy and u shared by the sense amplifiers 3-1 and 3-2 in the layout.
This is a parasitic resistance generated at −z, for example, a contact resistance between the sense amplifier drive signal line and the common wiring xy, uz, and a wiring resistance of the common wiring xy, uz.

In the conventional configuration shown in FIG. 3, when driving the sense amplifiers 3-1 and 3-2 at the timing T5, the bit line pair BL1 is connected to the data register 5-1 as described above. Since the electrodes are driven, the difference in the potential difference is larger than that in the case of the bit line pair BL2. In this case, in FIG. 6, due to the circuit operation, the charging current i1 of the sense amplifier 3-1 flows at a timing earlier than the charging current i2 of the sense amplifier 3-2.
The voltage drop at the parasitic resistance r1 of the common wiring xy decreases the amplification capability of the sense amplifier, and in particular, the amplification of the sense amplifier 3-2 having a small potential difference between the bit line pair BL is delayed. In addition, the effect of the discharge current i3 of the sense amplifier 3-1 on the discharge current i4 of the sense amplifier 3-2 due to the parasitic resistance r2 of the common wiring zu is similarly determined.
Causes the amplification of the DNA to be delayed.

As a result of considering the above problems, as a solution, as described in Japanese Patent Application No. 3-217127 filed by the inventors of the present invention and applied for a patent, data is dynamically stored. By providing a dynamic data holding circuit for holding, and transferring serially input data to the dynamic data holding circuit,
It is conceivable that data is transferred to the memory cell without driving the bit line by the transfer source serial data register.

However, the above solution requires at least four transistors per bit line pair and two capacitance elements having the same capacity as the memory cell, which results in an increase in circuit size and layout size. There is.

The present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor memory capable of achieving a high-speed transfer operation with a simple configuration.

[0024]

In order to achieve the above object, the present invention improves the amplification speed of a sense amplifier by performing data transfer from a serial data register to a bit line through a dummy cell. is there.

According to the present invention, the semiconductor memory has a memory
Recell, sense amplifier, dummy cell, serial data
Data register and data transfer means. Memory cell
Are connected to word lines and bit lines. Sensean
The amplifier amplifies the potential of the bit line. Dummy cell, Dami
-Connected to word lines and bit lines. Serial data
The register holds serially input data.
The data transfer means is held in the serial data register.
Output the data. In addition, the dummy cell
The output node of the data transfer means and the bit line are capacitively coupled.

[0026]

According to the above configuration, the bit line potential can be shifted in the direction corresponding to the data in the serial data register by a fixed voltage determined by the capacity coupling of the cell capacity of the dummy cell. In this way, the potential difference between the updated bit line pair can be reduced, and the amplification speed of the sense amplifier on the rewriting side can be improved.

The data transfer means can be constituted by using only four transistors per bit line pair, for example.

[0028]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of the semiconductor memory according to the embodiment. As shown in FIG. 1, the semiconductor memory according to the embodiment has memory cells 1-1, 1-2,. , A memory cell array 1 having dummy cells 7-1, 7-2, 7-3, 7-4,..., A row decoder 2, and sense amplifiers 3-1, 3-2,. Sense amplifier array 3 and transfer gates 4-1 and 4
, And a serial data register 5 for holding serially input data.
, A serial data register array 5 composed of mask registers 6-1, 6-2,..., And a dummy cell composed of dummy cell plate equalizers 8-1, 8-2,. A data transfer means for the bit line pair BL1 is constituted by a transfer gate 4-1 comprising two transistors and a dummy cell plate equalizer 8-1 comprising two transistors. , 2
Transfer gate 4-2 comprising two transistors and a dummy cell plate equalizer 8- comprising two transistors
2 constitute data transfer means for the bit line pair BL2.

One bit line of the bit line pair BL1 is connected to the memory cell 1-1 and the dummy cell 7-1, and the other bit line is connected to the dummy cell 7-2. One bit line is memory cell 1
-2 and the dummy cell 7-3, and the other bit line is connected to the dummy cell 7-4. The row address signal ROW is input to the row decoder 2, the word line WL is connected to the memory cells 1-1 and 1-2, the dummy word line DWL0 is connected to the dummy cells 7-1 and 7-3, and the dummy word Line DWL1 is connected to dummy cells 7-2, 7-
4 is connected. The sense amplifier drive signal SADR is input to the sense amplifiers 3-1 and 3-2. The dummy cell plate pair CP1 of the dummy cells 7-1 and 7-2 is
It is connected to the dummy cell plate equalizer 8-1, and further connected to the serial data register 5-1 via the transfer gate 4-1. Similarly, dummy cells 7-3,
The dummy cell plate pair CP2 of 7-4 is connected to the dummy cell plate equalizer 8-2, and further connected to the serial data register 5-2 via the transfer gate 4-2. D1 and D2 are buses, SI is serial data, MI is mask data, SCLK is a serial clock, DT1, DT2, / DT1, and / DT2 are signals, V
CP indicates a potential.

Here, the operation of taking in serial data SI from a serial input (not shown) and writing it into the memory cell array 1 will be described. As the operation order, as in the conventional example, first, an operation of holding serial data SI and mask data MI input from outside the memory is performed, and then, a data transfer operation to memory cell array 1 is performed.

In the semiconductor memory according to the present embodiment, the operation of holding the serial data SI and the mask data MI is exactly the same as in the conventional example. Hereinafter, regarding the data transfer operation,
This will be described with reference to the timing chart of FIG.

As shown in FIG. 2, at the timing of T1,
The row address signal ROW is applied to the row decoder 2. Then, at the timing of T2, the word line WL becomes high, and information of the selected memory cells 1-1 and 1-2 appears on the bit line pair BL1 and BL2 as an initial difference potential.
As in the conventional example, the bit line pair BL1 is changed to the update side,
The bit line pair BL2 is on the rewriting side.

Since the mask register 6-1 holds high, the signal DT1 becomes high at the timing of T3. At this time, the dummy cell plate equalizer 8-1 is turned off and the transfer gate 4-1 is turned on, so that the complementary data a and / a held in the serial data register 5-1 are stored in the dummy cell plate pair CP1. appear.

On the other hand, on the rewriting side, the signal DT2 is also low because the mask register 6-2 holds low. Then, dummy cell plate equalizer 8
-2 conducts and the transfer gate 4-2 is cut off, so that the dummy cell plate pair CP2 maintains the potential VCP.

When the signal DT1 goes high at the timing of T3, the potential of the dummy cell plate pair CP1 becomes VC
The potential changes from P potential to high and low. Therefore, the potential difference between the bit line pair BL1 changes due to the capacitive coupling in the dummy cells 7-1 and 7-2. When the cell capacity of the memory cell 1-1 is equal to the cell capacity of the dummy cells 7-1 and 7-2, the variation amount of the difference potential of the bit line pair BL1 is about twice the initial difference potential by the following calculation. It turns out that it becomes.

The cell capacity of the memory cell is Cs, the wiring capacity of the bit line is Cb, the cell capacity of the dummy cell is Cd, and the power supply voltage is Vc.
Assuming that c, the initial difference potential V0 is expressed as V0 = Cs / (Cs + Cb + Cd) .times.Vcc / 2 (1), and due to the coupling on the bit line on the side where the potential changes from Vcp to Vcc. The variation ΔVa is ΔVa = Cd / (Cs + Cb + Cd) × (Vcc−Vcp) (2), and the variation ΔVb due to coupling on the bit line on the side where the potential changes from Vcp to 0 is ΔVb = Cd / (Cs + Cb + Cd) × (−Vcp) (3) The variation amount ΔV1 of the difference potential is obtained by the equation (2) − (3), and is as follows: ΔV1 = ΔVa−ΔVb = Cd / (Cs + Cb + Cd) × Vcc (4) If Cs = Cd, equation (1) is expressed as V0 = Cs / (2Cs + Cb) × Vcc / 2 (5), and equation (4) is expressed as ΔV1 = Cs / (2Cs + Cb) × Vcc… (6) is expressed. From the equations (5) and (6), the variation amount ΔV1 of the difference potential can be expressed as the following equation (7) using the initial difference potential V0.

.DELTA.V1 = 2.times.V0 (7) For this reason, it is possible to supply charges necessary for inverting the data of the bit line pair BL1.

The level of the bit line pair BL2 does not fluctuate because the potential of the dummy cell plate pair CP2 is constant.

At timing T4, dummy cells 7-1 and 7-3 corresponding to the selected memory cells 1-1 and 1-2.
Of the dummy word line DWL0 is set to low.

Thereafter, at the timing of T5, the sense amplifier drive signal SADR drives the sense amplifiers 3-1 and 3-2, and the signals on the bit line pair BL1 and BL2 are amplified. The memory cell 1-1 is updated to the data a after the time t1 from the timing of T5, and the memory cell 1-2 is rewritten with the conventional data c after the time t2 from the timing of T5. Is performed.

The data transfer operation is performed by dummy cells 7-1 and 7-
In order to realize by the capacity coupling by the cell capacity of 2,
The difference potential after the transfer of the bit line pair BL1 can be suppressed to the same level as the initial difference potential. Therefore, the sense amplifier 3 shown in FIG.
-1 and the charging current i of the sense amplifier 3-2.
Since the difference between the timing and the current value between the two is smaller, the amplification capability of the sense amplifier 3-2 is improved as compared with the conventional example. This is the same for the discharge current i3 of the sense amplifier 3-1 and the discharge current i4 of the sense amplifier 3-2.

[0043]

As described above, according to the semiconductor memory of the present invention, the data is updated by, for example, using four transistors per bit line pair and performing data transfer using capacitive coupling. Since the potential difference between the paired bit lines can be reduced and the amplification speed of the sense amplifier on the rewriting side can be improved, the transfer operation can be speeded up with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory according to one embodiment of the present invention.

FIG. 2 is a timing chart showing a data transfer operation of the semiconductor memory according to the embodiment.

FIG. 3 is a circuit diagram showing a configuration of a conventional semiconductor memory.

FIG. 4 is a timing chart showing a serial data holding operation of the semiconductor memory.

FIG. 5 is a timing chart showing a data transfer operation of the conventional semiconductor memory.

FIG. 6 is a connection diagram of a sense amplifier and a sense amplifier drive signal line in the semiconductor memory;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory cell array 1-1, 1-2 Memory cell 2 Row decoder 3 Sense amplifier array 3-1 and 3-2 Sense amplifier 4 Transfer gate array 4-1 and 4-2 Transfer gate 5 Serial data register array 5-1 5-2 Serial data register 6 Mask register array 6-1, 6-2 Mask register 7-1, 7-2, 7-3, 7-4 Dummy cell 8 Dummy cell plate equalizer array 8-1, 8-2 Dummy cell plate equalizer

Claims (1)

(57) [Claims] A memory cell connected to a word line and a bit line; a sense amplifier for amplifying the potential of the bit line; a dummy word line and a dummy cell connected to the bit line; And outputs the data held in the serial data register.
The data transfer means, wherein the dummy cell is connected to an output node of the data transfer means.
A semiconductor memory, which is capacitively coupled to the bit line .