JPH0553355B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a signal readout circuit for a CCD having a floating diffusion type output circuit in a solid-state image sensor.

(Prior Art) A CCD signal readout method using a floating diffusion type output circuit has the disadvantage that noise is generated when resetting the output diode of the floating diffusion. However, this drawback can be overcome by using the correlated double sampling method. In principle, the clock period is divided into four time intervals in this scheme. First, a reset pulse is input during a first period to reset the potential of the output diode. Then during a second period the input potential of the readout amplifier,
That is, the feedthrough level is clamped to a constant value. During the third period, signal charge flows into the input circuit of the readout amplifier, so during the fourth period, this signal charge is sampled and held until the fourth period of the next clock period, and is then transferred to the signal output. Extract as

(Problems to be solved by the invention) This method is excellent in itself, but it has
Because each clock period is divided into four, the circuit must operate at extremely high speeds. In particular, the pulses for clamping during the second period must be narrow pulses and generated with high timing accuracy. For example, having 400 pixels horizontally and 500 vertically
In the case of CCDs for TV cameras, one clock cycle is approximately
140ns, and the width of the clamp pulse is approximately 35ns
becomes. As the image quality of CCD image sensors increases, it is now possible to manufacture image sensors with 800 horizontal pixels, but if the same method is applied in this case, the width of the clamp pulse will be 17.5 ns, which is extremely possible. Have difficulty. In other words, the correlated double sampling method is not compatible with the trend toward higher image quality of CCD image sensors.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a signal readout circuit for a CCD that can perform correlated double sampling without requiring high speed and high precision pulses.

(Means and effects for solving the problem) According to the present invention, this object is achieved as follows. That is, at least two pre-stage sample and hold circuits that sequentially select the output of the CCD in each signal readout period, sample the field-through level of each pixel, and hold the sample for at least the signal readout period; The side on which the field-through level is held operates in pairs, and the second-stage first sample-and-hold circuit that resamples within the corresponding signal readout period and the second-stage first sample-and-hold circuit operate in pairs, and the second-stage first sample-and-hold circuit operates as a pair. and a second sample and hold circuit in the latter stage that samples and holds the signal charge level of the pixel in synchronization with the circuit.
The output of the signal readout circuit is the difference between the first and second sample and hold circuits in the latter stage, which sample and hold within the same signal period.

If, for example, two sample and hold circuits are connected to the output circuit of the CCD, sampling only needs to be performed once during two readout periods.
Further, since it is sufficient that the pulse change occurs during the feed-through level period corresponding to the second period, the requirements for timing accuracy are gradually relaxed compared to the conventional clamp pulse. Further, even when three sample-and-hold circuits are provided, for example, the requirements for timing accuracy are significantly relaxed.

When two sample and hold circuits are provided at the front stage, four sample and hold circuits are provided at the rear stage. Two of the four latter stages sample and hold at the same timing within the same read cycle, and these two sample and hold circuits sample and hold the outputs of the different sample and hold circuits in the previous stage. Therefore, one of these two sample and hold circuits in the latter stage samples and holds the feedthrough level corresponding to the second period, and the other samples and holds the signal charge level corresponding to the fourth period. Holding. Therefore, the difference between the outputs of these two sample and hold circuits corresponds to the desired amount of signal charge.

According to the CCD signal readout circuit according to the present invention,
By providing a plurality of sample and hold circuits in the preceding stage connected to the CCD output circuit, an extended readout operation time can be obtained.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a CCD readout circuit according to the present invention. Two sample and hold circuits 21 and 22 are connected to the output circuit of the CCD. The output waveform of the CCD is shown in Figure 3, where the feedthrough level is 11
The signal charge level is indicated by 12, and each readout cycle is distinguished by a dash attached to the number. Sample hold circuit 21, 22
The control signals of are shown as SP21 and SP22, respectively, and when the control signals SP21 and SP22 are at high level, the sample and hold circuits 21 and
22 performs sampling, and control signals SP21, SP2
Holds the sampled level while 2 is at low level. The configuration of the sample and hold circuit is shown in FIG. Here, control input terminal SP
When a high level signal is applied to the switch SW, the switch SW is closed, ie, sampling is performed. Also, while a low level signal is supplied to the control input terminal SP,
The value of the signal that reaches the end of the sample period is held.

These preceding sample and hold circuits 21 and 22
The outputs S21 and S22 of S21 and S22 in FIG.
2. Output S21 holds the feedthrough level 11 sampled in the previous readout cycle over this readout cycle and continues sampling again during the next cycle. That is, during the next period, the input signal is transmitted as is to the output, and the next feedthrough level 11'' is held.
On the other hand, the output S22 has signal charge levels 12 and 1.
2'' is transmitted to the output as is, and the feedthrough level 11' is held.

These outputs S21 and S22 are sampled and held by sample and hold circuits 23, 24, 25, and 26 at the subsequent stage. Sample hold circuit 2
The control signals of 3 and 24 are shown in FIG. 3 SP23,
The control signals for the sample and hold circuits 25 and 26 are:
It is indicated by SP25 in the figure. Therefore, the output signal sampled and held by the sample and hold circuit 23 corresponds to the signal charge level 12', and the output signal sampled and held by the sample and hold circuit 24 corresponds to the feedthrough level 11'. do. The difference between the two output signals output from the differential amplifier 27 is the desired image signal in every other readout period, for example in an even numbered readout period. On the other hand, the output signal of the sample and hold circuit 25 corresponds to the feedthrough level 11, 11'', and the output of the sample and hold circuit 26 corresponds to the signal charge level 12, 12''. The difference between these two output signals from the differential amplifier is, for example, the desired image signal of the odd readout period.

In the above case, if a micro color filter with a color arrangement as shown in FIG. independently extracted from. In this case, according to the present circuit, color separation can be performed at the same time as noise removal.

FIGS. 5 and 6 are diagrams showing a configuration in which the sample and hold circuits 30, 31, and 32 at the previous stage in the circuit according to the present invention are operated at a cycle corresponding to three times the read cycle, and the operation of each part in that case. Since the operation of this circuit is the same as that shown in FIG. 1, it can be easily understood by those skilled in the art by comparing FIGS. 5 and 6. In this case, the repetition period of the sample hold control signals P30, P31, and P32 at the previous stage is three times the read period. Further, it is sufficient that the falling points of these control signals coincide with the period during which the feed-through level (corresponding to 11, 11', 11'' of the CCD output in FIG. 3) is output.
The timing precision imposed on these control signals is therefore also significantly relaxed.

In this case, each differential amplifier 39, 40, 4
The outputs S39, S40, and S41 of 1 are respectively
This corresponds to the 3n-2nd, 3n-1st, and 3n-th read cycles (n is a positive integer). Therefore, in this case, if a microcolor film having a color arrangement as shown in FIG. 7 is used, R, G, and B color signals can be taken out independently from each output terminal.

(Effects of the Invention) As described above, according to the CCD signal readout circuit of the present invention, correlated double sampling processing can be performed using pulses with relaxed speed and timing accuracy. It is possible to remove the reset noise of the image sensor. That is, a high quality image with less noise can be realized. Also,
Since the present invention can simultaneously perform correlated double sampling processing and color separation, it is possible to reduce both circuit scale and power consumption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of a CCD readout circuit according to the present invention, and FIG. 2 is a diagram showing an embodiment of a sample and hold circuit. Figure 3 is a waveform diagram for explaining the operation of the circuit in Figure 1;
5 is a block diagram showing a second embodiment of the circuit according to the invention; FIG.
FIG. 7, a waveform diagram for explaining the operation of the circuit shown in the figure, is a schematic diagram of another micro color filter that can be advantageously used in the present invention. 21-26, 30-38... Sample hold circuit, 27, 28, 39-41... Differential amplifier.

Claims (1)

[Claims] 1. In a CCD signal readout circuit having a floating diffusion type output circuit, the output of the CCD is sequentially selected in each signal readout period, and the field-through level of each pixel is sampled to at least At least two front-stage sample-and-hold circuits that hold the signal during the signal readout period; and a first rear-stage sample-and-hold circuit in which the side where the field-through level is held operates and resamples within the signal readout period. a sample-and-hold circuit, and a second second sample-and-hold circuit that operates in pairs with the first second sample-and-hold circuit and samples and holds the signal charge level of the pixel in synchronization with the first second sample-and-hold circuit; A signal readout circuit for a CCD, characterized in that the difference between the first and second sample and hold circuits that sample and hold within the same signal period is the output of the signal readout circuit.