JPH0553144A - Thin film transistor element array - Google Patents

Abstract

PURPOSE:To form the thin film transistor element array in which a step difference on the end face in a source/drain area is reduced, and a difference disconnection occurs in smaller numbers. CONSTITUTION:A source/drain area is formed by performing impurity implantation into an amorphous silicon film 13. This array is structured so that when a metal is formed to a film thereafter, a silicide layer 17 formed on the source/ drain surface is connected electrically with a picture element electrode 16, as a source electrode. Also, by patterning a metal 9 onto the picture element electrode, the thin film transistor element array in which a step difference disconnection occurs in smaller numbers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor element array used in an active matrix type liquid crystal display.

[0002]

2. Description of the Related Art In recent years, research and development of a thin film transistor element array used as a driving device for a liquid crystal flat display has been actively conducted. An active matrix liquid crystal display using a thin film transistor as a switching element of each pixel has a structure in which a pixel electrode is connected to a source electrode of the thin film transistor for driving liquid crystal. FIG. 3 shows a sectional view of one element of a conventional thin film transistor element array. In the conventional structure, n is formed on the source / drain region of the island-shaped amorphous silicon 13 in order to form an ohmic junction at the source / drain electrode portion.
⁺ Amorphous silicon 20 is formed and patterned. Thereafter, the pixel electrode 16, the source / drain electrode 18, or the source / drain electrode 18, and the pixel electrode 16 are formed and patterned in this order to complete a thin film transistor element array.

[0003]

However, in the above-described thin film transistor element array, the step difference at the end face of the source / drain region becomes large, and the source / drain electrode used for contact between the pixel electrode and the source region has a step difference. May come. This causes defects and causes problems in productivity.

An object of the present invention is to provide a highly productive thin film transistor element array structure which is unlikely to cause a step difference between the source region and the pixel electrode in the above thin film transistor element array.

[0005]

The present invention provides a gate electrode formed on an insulating substrate, a first transparent insulating film formed so as to cover the gate electrode, and a first transparent insulating film formed on the first transparent insulating film. An island-shaped amorphous silicon film formed, and a second transparent insulating film patterned on the island-shaped amorphous silicon film,
By using the second transparent insulating film as a mask, the entire area of the amorphous silicon layer except under the second transparent insulating film or the non-side surface of the non-insulating substrate other than under the second transparent insulating film is removed. A source / drain region having an impurity implanted in the surface of crystalline silicon, a thin film transistor having silicide formed on the surface of a part or the whole of the source / train region, and a thin film transistor formed on the first transparent insulating film. In a thin film transistor element array including pixel electrodes, pixel electrodes are patterned by overlapping the amorphous silicon surface of the source region where impurities are introduced or the silicide surface formed on the amorphous silicon of the source region. A thin film transistor element array characterized by electrically connecting an electrode and a source region, and the thin film transistor element array. In Lee, a thin film transistor array, characterized by having a metal that is patterned on the pixel electrodes on the stepped portion generated between the source region and the pixel electrode.

[0006]

In the conventional thin film transistor element array, as shown in FIG. 3, since the n ⁺ amorphous silicon 20 is used to form the ohmic layer, the step difference at the end face of the source / drain region becomes large. Therefore, the source / drain metal used for contact between the pixel electrode and the source region may have a step difference at this portion, and it is difficult to form a stable device. On the other hand, the present invention is shown in FIG.
As shown in (b), (c), and (d), it is not necessary to form n ⁺ amorphous silicon to form the source train region, so that the step difference at the end face of the source train region is significantly reduced. The possibility of running out of steps is reduced.

Further, as shown in FIG. 2, phosphorus is introduced into the amorphous silicon film as impurity atoms using the second transparent insulating film as a mask to form the source / drain regions.
Then, this amorphous silicon film is patterned into the shape of a transistor island. As the subsequent process sequence, there are two types of source / drain electrode formation, pixel electrode formation or the opposite pixel electrode formation, and source / drain electrode formation. 2C and 2D show a case where the pixel electrode is formed first. In this case, the pixel electrode is patterned so as to overlap the source region of the island-shaped amorphous silicon film, and then the source / drain electrode metal is formed and patterned to form the source / drain electrode. 2F and 2G show the case where the source / drain electrodes are formed first. In this case, since a low-resistance silicide is formed on the surface of the amorphous silicon, the metal on the source electrode side can be removed and this silicide can be directly used as the drain electrode. Then, patterning is performed so that the pixel electrode overlaps the silicide drain electrode. By using these structures, it is possible to electrically connect the pixel electrode and the drain electrode without causing a large step at the end face of the source / drain region as in the conventional example. In addition to this structure, by patterning a metal on the pixel electrode in the step portion between the pixel electrode and the island-shaped amorphous silicon film to prevent step breakage that may occur in this portion, a structure with fewer defects is possible. (Fig. 2 (e),
(H)). Due to these effects, it is possible to form a stable device with few defects.

[0008]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a sectional view of one element of four types of thin film transistor element arrays according to the present invention. FIG. 2 is a sectional view and a completed view of an element showing a method of manufacturing a thin film transistor element array according to the present invention in the order of steps. First, on the glass substrate 10 serving as an insulating substrate, chromium is deposited as a gate metal by a 100 nm sputtering method and patterned to form the gate electrode 11. Next, the gate insulating film SiN _x 400 nm as the first insulating film 12, the amorphous silicon film 13 as 100 nm, the second insulating film 14Si
After forming N _x by the 100 nm plasma CVD method, the second
The insulating film SiN _x is patterned into a desired shape.
Subsequently, phosphorus 15 is introduced into the amorphous silicon film as impurity atoms by using the patterned second insulating film as a mask (FIG. 2A). Further, amorphous silicon is patterned on the transistor islands (FIG. 2B).

First, the case where the pixel electrode is formed first will be described. As the pixel electrode 16, 30 nm of ITO is patterned so as to overlap with the source region of the island-shaped amorphous silicon film into which impurities are introduced (FIG. 2C). And 70 nm of chromium is used as the metal for the source and drain electrodes.
A film is formed by a sputtering method. At this time, the silicide layer 17 is formed to a thickness of about 5 nm between the amorphous silicon and chromium in the source / drain regions, but in order to form the silicide layer more reliably, a light hydrofluoric acid treatment or 150 treatment is performed before forming the chromium layer. It is advisable to anneal at 20 ° C. for 20 minutes. After that, the shape of the drain electrode 18 is patterned with chromium (FIG. 2D). At that time
As shown in (e), chromium is simultaneously patterned on the pixel electrode in the step portion between the pixel electrode ITO and the island-shaped amorphous silicon film, and the metal 19 for preventing the step difference is left, so that the step difference is further reduced. Structure is possible.

Next, the case where the source / drain electrodes are formed first will be described. First, as a metal for the source / drain electrodes, a film of chromium having a thickness of 70 nm is formed and patterned into the shape of the drain electrode. At this time, low-resistance silicide is formed on the surface of the amorphous silicon in the source region (FIG. 2 (f)). After that, ITO30 is used as a pixel electrode.
nm is patterned so as to overlap with the source region, and electrical connection is established (FIG. 2 (g)). Further, as shown in FIG. 2 (h), by patterning chromium on the pixel electrode at the step between the pixel electrode ITO and the island-shaped amorphous silicon film, a structure with less step difference is possible.

In the manufacture of the thin film transistor element array, SiN _x was used as the first and second insulating films, but any transparent insulating film such as SiO _x or TaO _x can be used in combination. Further, as the forming method, a sputtering method, a photo-CVD method or the like can be used.

In addition to chromium, the source / drain electrode metal may be nickel, molybdenum, vanadium, or the like, or may be a laminated structure of chromium-aluminum, chromium-nickel, nickel-gold, or an alloy. Regarding the metal for preventing the step difference between the pixel electrode and the silicide, in the case of the structure of FIG. 2H, a bus line is formed at the same time when patterning the step portion.
If the layer wiring is used, the resistance can be reduced.

[0013]

As described above, in the structure of the present invention, the pixel electrode is directly patterned on the amorphous silicon into which impurities are introduced or the silicide formed on the amorphous silicon so as to be electrically patterned. Since the connection structure is used, the step difference at the end face of the source / drain region is small, and the possibility of the step difference occurring at this portion is reduced, and the thin film transistor element array can be formed with a higher yield than in the conventional case.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing the structure of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing method for realizing the structure of the present invention in the order of steps.

FIG. 3 is a cross-sectional view showing a conventional structure.

[Explanation of symbols]

 10 Glass Substrate 11 Gate Electrode 12 First Insulating Film 13 Amorphous Silicon Film 14 Second Insulating Film 15 Impurity Atom 16 Pixel Electrode 17 Silicide Layer 18 Drain Electrode 19 Step Prevention Metal

Claims (2)

[Claims] 1. A gate electrode formed on an insulating substrate,
A first transparent insulating film formed to cover the gate electrode, an island-shaped amorphous silicon film formed on the first transparent insulating film, and an island-shaped amorphous silicon film formed on the island-shaped amorphous silicon film. The patterned second transparent insulating film, and the entire region of the amorphous silicon layer except under the second transparent insulating film or under the second transparent insulating film using the second transparent insulating film as a mask And a thin film transistor having a source / drain region in which impurities are implanted into the surface of the amorphous silicon on the side opposite to the insulating substrate and a silicide on the surface of a part or the whole of the source / train region, and the first In the thin film transistor element array including the pixel electrode formed on the transparent insulating film, the pixel electrode is formed on the surface of the amorphous silicon in which the impurity of the source region is introduced or on the amorphous silicon of the source region. Thin-film transistor element array, wherein a structure having electrical connection between the pixel electrode and the source region by patterning so as to overlap the side surface. 2. The thin film transistor element array according to claim 1, wherein the thin film transistor element array has a patterned metal on the pixel electrode in a step portion formed between the source region and the pixel electrode.