JPH0553068B2 - - Google Patents
Info
- Publication number
- JPH0553068B2 JPH0553068B2 JP61075788A JP7578886A JPH0553068B2 JP H0553068 B2 JPH0553068 B2 JP H0553068B2 JP 61075788 A JP61075788 A JP 61075788A JP 7578886 A JP7578886 A JP 7578886A JP H0553068 B2 JPH0553068 B2 JP H0553068B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- elements
- semiconductor device
- semiconductor element
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 claims description 52
- 239000000758 substrate Substances 0.000 claims description 16
- 238000000605 extraction Methods 0.000 claims description 8
- 230000010354 integration Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の素子の配置構造に関
し、特に高周波アナログ用の半導体装置における
集積化構造および、素子の配置により半導体装置
の電気的特性を向上する配線構造に関する。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an arrangement structure of elements of a semiconductor device, and in particular, to an integrated structure in a semiconductor device for high-frequency analog use, and an improvement in the electrical characteristics of a semiconductor device by the arrangement of elements. This invention relates to a wiring structure that improves performance.
従来この種の半導体装置は、半導体装置を構成
する上で必要となる半導体素子およびその他の回
路素子等を、半導体素子基板の同一平面上もしく
は、薄い絶縁膜等を介して、層状に配置、配線さ
れる構造となつていた。
Conventionally, this type of semiconductor device has been constructed by arranging and wiring semiconductor elements and other circuit elements necessary for configuring the semiconductor device on the same plane of the semiconductor element substrate or in layers through a thin insulating film, etc. The structure was such that
上述した従来の半導体装置は、半導体素子基板
上の同一平面上に半導体装置を構成する半導体素
子、および抵抗素子、静電容量素子、外部取り出
し用電極等の半導体装置が必要とする。各素子お
よび各回路素子が配置されているので、必要とす
る素子数及び回路素子数によつて半導体装置のチ
ツプ面積が決定される。特に、外部取り出し用電
極及び静電容量素子等は、回路を構成上で、大き
な面積を必要とするため、半導体装置のチツプ面
積を大きくし、従来の半導体装置では、装置の集
積度が低下する欠点がある。
The conventional semiconductor device described above requires a semiconductor element, a resistive element, a capacitive element, an electrode for external extraction, etc., which constitute the semiconductor device on the same plane on a semiconductor element substrate. Since each element and each circuit element are arranged, the chip area of the semiconductor device is determined by the required number of elements and circuit elements. In particular, electrodes for external extraction and capacitance elements, etc. require a large area in the circuit configuration, which increases the chip area of the semiconductor device, and in conventional semiconductor devices, the degree of integration of the device decreases. There are drawbacks.
また、半導体素子基板の同一平面上に各素子及
び各回路素子が高密度に配置されるため、素子間
での電気的悪影響が生じ、半導体装置の電気的特
性を低下させる欠点がある。 Furthermore, since each element and each circuit element are arranged at high density on the same plane of the semiconductor element substrate, there is a drawback that electrical effects occur between the elements and deteriorate the electrical characteristics of the semiconductor device.
さらに、外部取り出し用電極等の寄生容量等
が、装置の電気的特性に影響を及ぼすような半導
体装置においては、半導体素子基板上では、薄い
高誘電率の絶縁層上に配置されるため、半導体装
置の電気的性能を低下させる欠点がある。 Furthermore, in semiconductor devices where parasitic capacitance, etc. of external lead-out electrodes, etc. affect the electrical characteristics of the device, the semiconductor device is placed on a thin high dielectric constant insulating layer on the semiconductor element substrate. It has the disadvantage of reducing the electrical performance of the device.
本発明の半導体装置は、半導体素子基板に配置
される半導体素子及び回路素子において、外部取
り出し用電極および静電容量素子回路等のおきな
面積形状を必要とする回路素子が、半導体基板上
に形成される半導体素子およびその周辺回路素子
に対し立体的に配置し、半導体装置のチツプ面積
を少なくして半導体装置の集積度を高める構造
と、立体的に配置された素子間層に、低誘電率の
厚い絶縁層が用いられることで、各素子間の電気
的影響を少なくし、絶縁層上に配置される素子に
生じる寄生容量が少なくなるため、半導体装置の
電気的特性を向上させ、低コストで高性能の半導
体装置を提供する構造を有している。
In the semiconductor device of the present invention, in semiconductor elements and circuit elements arranged on a semiconductor element substrate, circuit elements that require a large area shape, such as an electrode for external extraction and a capacitance element circuit, are formed on the semiconductor substrate. The semiconductor element and its peripheral circuit elements are arranged three-dimensionally to reduce the chip area of the semiconductor device and increase the degree of integration of the semiconductor device. By using a thick insulating layer of It has a structure that provides a high-performance semiconductor device.
次に、本発明について図面を参照して説明す
る。
Next, the present invention will be explained with reference to the drawings.
第１図は、本発明の一実施例の断面図である。
半導体素子４および、半導体素子の周辺に必要と
される回路素子３，５は、半導体素子基板１の上
面に形成される。さらに、半導体素子基板１の上
面には、低誘電率の厚い絶縁層２が形成され、絶
縁層２の上面には外部取り出し用の電極６、およ
び、静電容量素子回路７等が、絶縁層２の側面等
に形成される配線用回路素子８によつて、半導体
素子基板上の素子３，４，５と電気的に結線され
て配置、形成される。 FIG. 1 is a sectional view of one embodiment of the present invention.
The semiconductor element 4 and the circuit elements 3 and 5 required around the semiconductor element are formed on the upper surface of the semiconductor element substrate 1. Further, a thick insulating layer 2 with a low dielectric constant is formed on the upper surface of the semiconductor element substrate 1, and an electrode 6 for external extraction, a capacitive element circuit 7, etc. are formed on the upper surface of the insulating layer 2. The wiring circuit elements 8 formed on the side surfaces of the semiconductor element substrate 2 are arranged and formed so as to be electrically connected to the elements 3, 4, and 5 on the semiconductor element substrate.
絶縁層２の上面に形成された、外部取り出し用
電極６は、絶縁層２が、低誘電率の厚い層である
ため寄生容量が小さくなる。また電極６と静電容
量素子回路７と半導体素子基板１上の回路素子
３，４，５との影響も少ない。 The external extraction electrode 6 formed on the upper surface of the insulating layer 2 has a small parasitic capacitance because the insulating layer 2 is a thick layer with a low dielectric constant. Further, the influence of the electrode 6, the capacitive element circuit 7, and the circuit elements 3, 4, and 5 on the semiconductor element substrate 1 is also small.
さらに、半導体装置の素子面積の1/2近くを要
する電極６と静電容量素子回路７は、半導体素子
基板１上の回路素子３，４，５に関係なく、絶縁
層２の上面に、任意に配置できるため、素子面積
を小さく集積度を高める。 Further, the electrode 6 and the capacitive element circuit 7, which require nearly half the element area of the semiconductor device, can be arbitrarily placed on the upper surface of the insulating layer 2, regardless of the circuit elements 3, 4, and 5 on the semiconductor element substrate 1. Since the device can be placed in multiple locations, the device area can be reduced and the degree of integration can be increased.
〔発明の効果〕
以上説明したように本発明は、半導体装置に内
造される外部取り出し用電極と静電容量素子回路
等の大きな面積が必要とされる回路素子が、半導
体素子基板上に形成される半導体素子および周辺
の回路素子に対して、立体的に配置されることか
ら、半導体装置のチツプ面積を小さくすることが
できる。さらに従来の製造寸法規程において半導
体装置の集積度を高めることができる。また、半
導体装置のチツプ面積が少さくなり、製造課程に
おける論理チツプ収量が向上され、低コストの半
導体装置を提供することができる。[Effects of the Invention] As explained above, the present invention enables circuit elements that require a large area, such as external extraction electrodes and capacitance element circuits, which are internally manufactured in a semiconductor device, to be formed on a semiconductor element substrate. The chip area of the semiconductor device can be reduced because it is arranged three-dimensionally with respect to the semiconductor element and surrounding circuit elements. Furthermore, the degree of integration of semiconductor devices can be increased within conventional manufacturing size regulations. Furthermore, the chip area of the semiconductor device is reduced, the yield of logic chips in the manufacturing process is improved, and a low-cost semiconductor device can be provided.
また、立体的に配置された素子間に、低誘電率
の厚い絶縁層を有することから、上面に配置され
る電極層に生じる寄生容量が小さく、さらに、絶
縁層間に配置された素子間の電気的な悪影響が少
いため、より優れた高周波特性の半導体装置を提
供することができる。 In addition, since there is a thick insulating layer with a low dielectric constant between the three-dimensionally arranged elements, the parasitic capacitance generated in the electrode layer placed on the top surface is small, and the electric current between the elements arranged between the insulating layers is small. Since there are few adverse effects, it is possible to provide a semiconductor device with better high frequency characteristics.
第１図は、本発明の半導体装置の素子の断面図
である。
１……半導体素子基板、２……絶縁層、３，
４，５……半導体素子および周辺の回路素子、６
……外部取り出し用電極、７……静電容量素子回
路、８……配線用回路素子。
FIG. 1 is a sectional view of an element of a semiconductor device according to the present invention. 1... Semiconductor element substrate, 2... Insulating layer, 3,
4, 5... Semiconductor element and peripheral circuit element, 6
...Electrode for external extraction, 7...Capacitive element circuit, 8... Circuit element for wiring.
Claims (1)
としての複数の素子が半導体素子基板上に配置さ
れ、該半導体素子基板および該複数の素子上に低
誘電率の厚い絶縁層が形成され、該絶縁層上に外
部取り出し用電極と該複数の素子のうちの数個の
素子にまたがる静電容量素子とが配置されている
ことを特徴とする半導体装置。1. A semiconductor element and a plurality of elements as circuit elements around the semiconductor element are arranged on a semiconductor element substrate, a thick insulating layer with a low dielectric constant is formed on the semiconductor element substrate and the plurality of elements, and a thick insulating layer with a low dielectric constant is formed on the insulating layer. 1. A semiconductor device, wherein an electrode for external extraction and a capacitance element spanning several of the plurality of elements are arranged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7578886A JPS62232154A (en) | 1986-04-01 | 1986-04-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7578886A JPS62232154A (en) | 1986-04-01 | 1986-04-01 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62232154A JPS62232154A (en) | 1987-10-12 |
| JPH0553068B2 true JPH0553068B2 (en) | 1993-08-09 |
Family
ID=13586302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7578886A Granted JPS62232154A (en) | 1986-04-01 | 1986-04-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62232154A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS611048A (en) * | 1985-04-17 | 1986-01-07 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Memory element |
-
1986
- 1986-04-01 JP JP7578886A patent/JPS62232154A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS611048A (en) * | 1985-04-17 | 1986-01-07 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Memory element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62232154A (en) | 1987-10-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |