JPH0552111B2 - - Google Patents

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Publication number
JPH0552111B2
JPH0552111B2 JP62063321A JP6332187A JPH0552111B2 JP H0552111 B2 JPH0552111 B2 JP H0552111B2 JP 62063321 A JP62063321 A JP 62063321A JP 6332187 A JP6332187 A JP 6332187A JP H0552111 B2 JPH0552111 B2 JP H0552111B2
Authority
JP
Japan
Prior art keywords
period
overflow drain
drain region
during
frame transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62063321A
Other languages
Japanese (ja)
Other versions
JPS63228886A (en
Inventor
Eiichiro Azuma
Takashi Adachi
Masakazu Inami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP62063321A priority Critical patent/JPS63228886A/en
Publication of JPS63228886A publication Critical patent/JPS63228886A/en
Publication of JPH0552111B2 publication Critical patent/JPH0552111B2/ja
Granted legal-status Critical Current

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  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Description

【発明の詳細な説明】 (イ) 産業上の利用分野 本発明は固体撮像素子の駆動方法、特にフレー
ムトランスフア方式による固体撮像素子の駆動方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method for driving a solid-state image sensor, and particularly to a method for driving a solid-state image sensor using a frame transfer method.

(ロ) 従来の技術 固体撮像デバイスには、インターライントラン
スフア(IT)方式CCD(Charge Coupled
Device)とフレームトランスフア(FT)方式
CCDとがある。IT方式CCDでは撮像領域と蓄積
領域が交互に配置され、FT方式CCDでは撮像部
と蓄積部が分離配置されている。
(b) Conventional technology Solid-state imaging devices include interline transfer (IT) type CCDs (Charge Coupled
Device) and frame transfer (FT) method
There is a CCD. In an IT CCD, the imaging area and the storage area are arranged alternately, and in an FT CCD, the imaging section and the storage section are arranged separately.

FT方式CCDの撮像部の構造を第4図および第
5図に示す。この撮像部はクロスゲート構造を採
用しており、1はP型のシリコン基板、2はゲー
ト酸化膜、3はLOCOS構造を有するフイールド
酸化膜より成るチヤンネル分離領域、4,5は水
平方向に延在されるポリシリコンより成る下層ゲ
ート電極、6,7は垂直方向に延在されるポリシ
リコンより成る上層ゲート電極、8はN+型のオ
ーバーフロードレイン領域、9はN型の蛇行した
チヤンネル領域、10は開口窓、11は開口窓1
0下に設けたP+型の開口領域である。
The structure of the imaging section of the FT CCD is shown in FIGS. 4 and 5. This imaging section adopts a cross-gate structure, in which 1 is a P-type silicon substrate, 2 is a gate oxide film, 3 is a channel isolation region made of a field oxide film having a LOCOS structure, and 4 and 5 are horizontally extending regions. 6 and 7 are vertically extending upper gate electrodes made of polysilicon; 8 is an N + type overflow drain region; 9 is an N type meandering channel region; 10 is an opening window, 11 is an opening window 1
This is a P + type opening area provided below 0.

斯るFT方式CCDは第6図に示すクロツクパル
スで駆動される。クロツクパルスφ1,φ3は上層
ゲート電極6,7に1つおきに印加され、VL
VM,VHの3つのレベルを持つ、クロツクパルス
φ2,φ4は下層ゲート電極4,5に1つおきに印
加され、VL,VHの2つのレベルを持つ。
Such an FT type CCD is driven by a clock pulse shown in FIG. Clock pulses φ 1 and φ 3 are applied to every other upper layer gate electrode 6 and 7, and V L ,
Clock pulses φ 2 and φ 4 having three levels, V M and V H , are applied to every other lower gate electrode 4 and 5, and have two levels, V L and V H.

2:1インタレース駆動の奇数フイールドにお
いて、クロツクパルスφ2,φ3およびφ4がVLにセ
ツトされ、クロツクパルスφ1はVMにセツトされ
て光蓄積期間に入る。この光蓄電期間中に光電変
換された電荷は、開口窓10周辺のクロツクφ1
を印加された上層ゲート電極6、クロツクφ2
φ4を印加された下層ゲート電極4,5下に蓄積
され、クロツクφ3を印加された上層ゲート電極
7下でせき止められている。なお強い入射光によ
り過剰発生した電荷は、クロツクφ1を印加した
上層ゲート電極6下のチヤンネル分離領域3を通
して隣接したオーバーフロードレイン領域8にあ
ふれ出る。この蓄積された電荷は、次のフレーム
転送期間で4相駆動法により撮像部から蓄積部に
転送される。
In the odd field of the 2:1 interlaced drive, clock pulses φ 2 , φ 3 and φ 4 are set to V L and clock pulse φ 1 is set to VM to enter the light accumulation period. The charges photoelectrically converted during this photoaccumulation period are transferred to the clock φ 1 around the aperture window 10.
is applied to the upper layer gate electrode 6, the clock φ 2 ,
It is accumulated under the lower layer gate electrodes 4 and 5 to which the clock φ 4 is applied, and is blocked under the upper layer gate electrode 7 to which the clock φ 3 is applied. Note that excessive charges generated by the strong incident light overflow into the adjacent overflow drain region 8 through the channel separation region 3 under the upper layer gate electrode 6 to which the clock φ 1 is applied. This accumulated charge is transferred from the imaging section to the storage section by the four-phase driving method in the next frame transfer period.

次に偶数フイールドにおいて、光蓄積期間中ク
ロツクパルスφ1,φ2およびφ4がVLにセツトされ、
クロツクパルスφ3はVMにセツトされる。この期
間中に光電変換された電荷は、開口窓10周辺の
クロツクφ3を印加された上層ゲート電極7、ク
ロツクφ2,φ4を印加された下層ゲート電極4,
5下に蓄積され、クロツクφ1を印加された上層
ゲート電極6下でせき止められている。この電荷
は同様にフレーム転送期間中に4相駆動法により
撮像部から蓄積部に転送される。
Then in the even field, clock pulses φ 1 , φ 2 and φ 4 are set to V L during the photoaccumulation period;
Clock pulse φ3 is set to VM . The charges photoelectrically converted during this period are transferred to the upper layer gate electrode 7 around the aperture window 10 to which clock φ 3 is applied, the lower layer gate electrode 4 to which clocks φ 2 and φ 4 are applied,
5 and is blocked below the upper layer gate electrode 6 to which the clock φ1 is applied. Similarly, this charge is transferred from the imaging section to the storage section by the four-phase driving method during the frame transfer period.

なお光蓄積期間およびフレーム転送期間を通し
てオーバーフロードレイン領域8のOFD電圧は
チヤンネル分離領域3のポテンシヤルよりも深い
ポテンシヤルを与える必要がある。この理由はオ
ーバーフロードレイン領域からチヤンネル領域9
への電荷の逆流を阻止するためである。従つてチ
ヤンネル分離領域3のポテンシヤルはフレーム転
送期間に上層ゲート電極6,7にVHを印加した
時に最も深くなり、OFD電圧は上層ゲート電極
6,7にVHを印加した時のチヤンネル分離領域
3のポテンシヤルよりも高いDC電圧に固定され
ていた。
Note that it is necessary to give the OFD voltage of the overflow drain region 8 a deeper potential than that of the channel separation region 3 throughout the optical accumulation period and the frame transfer period. The reason for this is from the overflow drain region to the channel region 9.
This is to prevent charge from flowing backwards. Therefore, the potential of the channel separation region 3 becomes the deepest when V H is applied to the upper layer gate electrodes 6 and 7 during the frame transfer period, and the OFD voltage becomes the deepest in the channel separation region when V H is applied to the upper layer gate electrodes 6 and 7. It was fixed at a DC voltage higher than the potential of 3.

以上に述べた従来技術は、例えば工業調査会発
行電子材料1986年3月号、P123〜P127に記載さ
れている。
The above-mentioned conventional technology is described, for example, in the March 1986 issue of Electronic Materials published by Kogyo Kenkyukai, pages 123 to 127.

(ハ) 発明が解決しようとする問題点 しかしながら斯上した従来のFT方式CCDの駆
動方法では、1/2インチ形光学系の場合には、20
万画素のCCDを30万画素に高解像度化すると、
1画素当りの開口窓10の面積が約7割減少する
ことになる。このために開口窓10の面積減少に
より感度の低下が発生する問題点を有していた。
(c) Problems to be solved by the invention However, in the conventional FT CCD driving method described above, in the case of a 1/2 inch optical system,
When the resolution of a million pixel CCD is increased to 300,000 pixels,
The area of the aperture window 10 per pixel is reduced by about 70%. For this reason, there was a problem in that the sensitivity decreased due to the reduction in the area of the aperture window 10.

この感度の低下は、開口窓10で光電変換され
た電荷がオーバーフロードレイン領域8に流出す
る割合が増加するものと考えられる。第7図は撮
像部のCCDの拡大図であり、偶数フイールドの
光蓄積期間を示している。このとき−線断面
のポテンシヤルは第8図に示されている。即ち、
オーバーフロードレイン領域8には最も深いポテ
ンシヤルが与えられているので、開口窓10で発
生した点線で示す電荷はオーバーフロードレイン
領域8の電界により点線の矢印で示される様にオ
ーバーフロードレイン領域8に流出してしまうの
である。
This decrease in sensitivity is considered to be due to an increase in the rate at which charges photoelectrically converted in the aperture window 10 flow out to the overflow drain region 8. FIG. 7 is an enlarged view of the CCD of the imaging section, showing the light accumulation period of an even field. At this time, the potential of the - line cross section is shown in FIG. That is,
Since the deepest potential is given to the overflow drain region 8, the charge generated in the opening window 10, shown by the dotted line, flows out to the overflow drain region 8 as shown by the dotted arrow due to the electric field of the overflow drain region 8. It's put away.

(ニ) 問題点を解決するための手段 本発明は斯上した問題点に鑑みてなされ、光蓄
積期間におけるオーバーフロードレイン領域の
OFD電圧を下げることにより、従来の問題点を
改善した固体撮像素子の駆動方法を提供するもの
である。
(d) Means for solving the problems The present invention has been made in view of the above-mentioned problems.
The present invention provides a method for driving a solid-state image sensor that improves the conventional problems by lowering the OFD voltage.

(ホ) 作用 本発明に依れば、光蓄積期間におけるオーバー
フロードレイン領域8のOFD電圧を下げること
により、オーバーフロードレイン領域8の電界を
チヤンネル領域9よりも弱めて開口窓10に発生
する電荷をチヤンネル領域9に流入させる割合を
大幅に高めて感度の低下を防止している。
(E) Effect According to the present invention, by lowering the OFD voltage of the overflow drain region 8 during the photoaccumulation period, the electric field of the overflow drain region 8 is made weaker than that of the channel region 9, thereby channeling the charges generated in the aperture window 10. The rate of inflow into region 9 is greatly increased to prevent a decrease in sensitivity.

(ヘ) 実施例 本発明の一実施例を第1図乃至第3図を参照し
て詳述する。
(F) Embodiment An embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

第1図は撮像部のCCDの拡大図であり、偶数
フイールドの光蓄積期間を示している。第2図は
第1図の−線断面のポテンシヤルを示してい
る。第1図および第2図は第7図および第8図と
対応しており、同一構成要素には同一符号を付し
てある。
FIG. 1 is an enlarged view of the CCD of the imaging section, showing the light accumulation period of an even field. FIG. 2 shows the potential of the cross section taken along the line -- in FIG. 1 and 2 correspond to FIGS. 7 and 8, and the same components are given the same reference numerals.

本発明の特徴はオーバーフロードレイン領域8
のOFD電圧を従来のVHからVMに低下させたこと
にある。この結果、第2図のポテンシヤル図から
明白な様に、オーバーフロードレイン領域8のポ
テンシヤルは第8図に比較して大幅に浅くなり、
オーバーフロードレイン領域8のOFD電圧によ
る電界は弱められる。従つて開口窓10で発生し
た点線で示す電荷はオーバーフロードレイン領域
8のポテンシヤルより深く設定されたチヤンネル
領域9に流入する割合が大幅に向上し、大部分は
実線の矢印に示す様にチヤンネル領域9に流入す
る。
The feature of the present invention is that the overflow drain region 8
The reason for this is that the OFD voltage of the device was lowered from the conventional VH to VM . As a result, as is clear from the potential diagram in FIG. 2, the potential of the overflow drain region 8 becomes significantly shallower than in FIG.
The electric field due to the OFD voltage in the overflow drain region 8 is weakened. Therefore, the charge generated in the opening window 10, shown by the dotted line, has a significantly increased rate of flowing into the channel region 9, which is set deeper than the potential of the overflow drain region 8, and most of it flows into the channel region 9, as shown by the solid arrow. flows into.

一方、オーバーフロードレイン領域8のポテン
シヤルはチヤンネル分離領域3のポテンシヤルよ
り深く設定されている。この理由はオーバーフロ
ードレイン領域8の本来の役割である強い入射光
による過剰発生電荷を吸収するためである。
On the other hand, the potential of the overflow drain region 8 is set deeper than the potential of the channel separation region 3. The reason for this is that the overflow drain region 8 has an original role of absorbing excessive charges caused by strong incident light.

第3図に本発明の固体撮像素子の駆動方法に用
いるクロツクパルスを示す。第3図は第6図と対
応しており、クロツクパルスφ1,φ2,φ3,φ4
従来のものと同一であり、駆動方法も同一である
ので動作説明を省略する。本発明の特徴はオーバ
ーフロードレイン領域8に印加されるOFD電圧
を光蓄積期間はVMにフレーム転送期間はVHに設
定したパルス状にした点にある。従つてフレーム
転送期間中はオーバーフロードレイン領域8の
OFD電圧は最も深いポテンシヤルが与えられ、
フレーム転送期間中は従来と同様にオーバーフロ
ードレイン領域8からチヤンネル領域9への電荷
の逆流は阻止されている。
FIG. 3 shows clock pulses used in the method for driving a solid-state image pickup device of the present invention. FIG. 3 corresponds to FIG. 6, and the clock pulses φ 1 , φ 2 , φ 3 , and φ 4 are the same as those of the prior art, and the driving method is also the same, so a description of the operation will be omitted. The feature of the present invention is that the OFD voltage applied to the overflow drain region 8 is pulsed with V M during the optical accumulation period and V H during the frame transfer period. Therefore, during the frame transfer period, the overflow drain region 8
OFD voltage is given the deepest potential,
During the frame transfer period, reverse flow of charges from the overflow drain region 8 to the channel region 9 is prevented as in the conventional case.

(ト) 発明の効果 本発明に依れば、光蓄積期間のオーバーフロー
ドレイン領域8のOFD電圧をVMに低下させるこ
とにより、開口窓10での発生電荷がオーバーフ
ロードレイン領域8の電界によりオーバーフロー
ドレイン領域8に流出する割合を従来に比較して
低減でき、短波長光感度は従来より約20%向上で
きる利点を有する。
(g) Effects of the Invention According to the present invention, by lowering the OFD voltage of the overflow drain region 8 during the photoaccumulation period to V M , the electric charge generated in the aperture window 10 is transferred to the overflow drain by the electric field of the overflow drain region 8. It has the advantage that the ratio of leakage to region 8 can be reduced compared to the conventional method, and the short wavelength light sensitivity can be improved by about 20% compared to the conventional method.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による固体撮像素子の撮像部の
CCDを説明する上面図、第2図は第1図の−
線断面のポテンシヤル図、第3図は本発明の駆
動方法に用いるクロツクパルスのタイミングチヤ
ート図、第4図はFT方式CCDを説明する上面
図、第5図は第4図の−線断面図、第6図は
従来の駆動方法に用いるクロツクパルスのタイミ
ングチヤート図、第7図は従来のFT方式CCDの
撮像部のCCDを説明する上面図、第8図は第7
図の−線断面のポテンシヤル図である。 1は半導体基板、2はゲート酸化膜、3はチヤ
ンネル分離領域、4,5は下層ゲート電極、6,
7は上層ゲート電極、8はオーバーフロードレイ
ン領域、9はチヤンネル領域、10は開口窓、1
1は開口領域である。
FIG. 1 shows the imaging section of the solid-state imaging device according to the present invention.
A top view explaining the CCD, Figure 2 is the − of Figure 1.
3 is a timing chart of clock pulses used in the driving method of the present invention, FIG. 4 is a top view illustrating an FT type CCD, and FIG. 5 is a sectional view taken along the line 4 in FIG. Fig. 6 is a timing chart of clock pulses used in the conventional driving method, Fig. 7 is a top view explaining the CCD of the imaging section of the conventional FT type CCD, and Fig. 8 is a timing diagram of the clock pulse used in the conventional driving method.
It is a potential diagram of the cross section taken along the line - in the figure. 1 is a semiconductor substrate, 2 is a gate oxide film, 3 is a channel isolation region, 4 and 5 are lower layer gate electrodes, 6,
7 is an upper layer gate electrode, 8 is an overflow drain region, 9 is a channel region, 10 is an opening window, 1
1 is an opening area.

Claims (1)

【特許請求の範囲】[Claims] 1 撮像部と蓄積部とを分離して有し、光蓄積期
間中に前記撮像部で光電変換により電荷の蓄積を
行い、フレーム転送期間中に前記電荷を前記蓄積
部に転送するフレームトランスフア方式の固体撮
像素子において、光蓄積期間中、前記撮像部のチ
ヤンネル分離領域内に設けたオーバーフロードレ
イン領域に、フレーム転送期間の印加電圧より低
い電圧を前記撮像部の転送電極と独立して印加す
ることを特徴とした固体撮像素子の駆動方法。
1. A frame transfer method in which an imaging section and a storage section are separated, the imaging section accumulates charges by photoelectric conversion during a photoaccumulation period, and the charges are transferred to the storage section during a frame transfer period. In the solid-state imaging device, during a light accumulation period, a voltage lower than a voltage applied during a frame transfer period is applied to an overflow drain region provided in a channel separation region of the imaging section independently of a transfer electrode of the imaging section. A method for driving a solid-state image sensor characterized by:
JP62063321A 1987-03-18 1987-03-18 Method for driving solid-state image pickup element Granted JPS63228886A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62063321A JPS63228886A (en) 1987-03-18 1987-03-18 Method for driving solid-state image pickup element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62063321A JPS63228886A (en) 1987-03-18 1987-03-18 Method for driving solid-state image pickup element

Publications (2)

Publication Number Publication Date
JPS63228886A JPS63228886A (en) 1988-09-22
JPH0552111B2 true JPH0552111B2 (en) 1993-08-04

Family

ID=13225885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62063321A Granted JPS63228886A (en) 1987-03-18 1987-03-18 Method for driving solid-state image pickup element

Country Status (1)

Country Link
JP (1) JPS63228886A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57109475A (en) * 1980-12-26 1982-07-07 Sony Corp Solid image pickup element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57109475A (en) * 1980-12-26 1982-07-07 Sony Corp Solid image pickup element

Also Published As

Publication number Publication date
JPS63228886A (en) 1988-09-22

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