JP2698072B2 - Solid-state imaging device - Google Patents
Solid-state imaging deviceInfo
- Publication number
- JP2698072B2 JP2698072B2 JP62063322A JP6332287A JP2698072B2 JP 2698072 B2 JP2698072 B2 JP 2698072B2 JP 62063322 A JP62063322 A JP 62063322A JP 6332287 A JP6332287 A JP 6332287A JP 2698072 B2 JP2698072 B2 JP 2698072B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- channel
- opening
- photoelectric conversion
- impurity concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000003384 imaging method Methods 0.000 title claims description 25
- 239000012535 impurity Substances 0.000 claims description 24
- 238000009825 accumulation Methods 0.000 claims description 8
- 238000000926 separation method Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims 5
- 238000002955 isolation Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 230000035945 sensitivity Effects 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 206010034960 Photophobia Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000012776 electronic material Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 208000013469 light sensitivity Diseases 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14887—Blooming suppression
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Description
【発明の詳細な説明】
(イ)産業上の利用分野
本発明は固体撮像素子、特にフレームトランスファ方
式による固体撮像素子に関する。
(ロ)従来の技術
固体撮像デバイスには、インターライントランスファ
(IT)方式CCD(Charge CouPled Device)とフレームト
ランスファ(FT)方式CCDとがある。IT方式CCDでは撮像
領域と蓄積領域とが交互に配置され、FT方式CCDでは撮
像部と蓄積部が分離配置されている。
FT方式CCDの撮像部の構造を第4図および第5図に示
す。この撮像部はクロスゲート構造を採用しており、
(1)はP型のシリコン基板、(2)はゲート酸化膜、
(3)はLOCOS構造を有するフィールド酸化膜より成る
チャンネル分離領域、(4)(5)は水平方向に延在さ
れるポリシリコンより成る下層ゲート電極、(6)
(7)は垂直方向に延在されるポリシリコンより成る上
層ゲート電極、(8)はN+型のオーバーフロードレイン
領域、(9)はN型の蛇行したチャンネル領域、(10)
は開口窓、(11)は開口窓(10)下に設けたP+型の開口
領域である。
斯るFT方式CCDは第6図に示すクロックパルスで駆動
される。クロックパルスφ1,φ3は上層ゲート電極
(6)(7)に1つおきに印加され、VL,VM,VHの3つの
レベルを持つクロックパルスφ2,φ4は下層ゲート電極
(4)(5)に1つおきに印加され、VL,VHの2つのレ
ベルを持つ。
2:1インタレース駆動の奇数フィールドにおいて、ク
ロックパルスφ2,φ3およびφ4がVLにセットされ、ク
ロックパルスφ1はVMにセットされて光蓄積期間に入
る。この光蓄積期間中に光電変換された電荷は、開口窓
(10)周辺のクロックφ1を印加された上層ゲート電極
(6)、クロックφ2,φ4を印加された下層ゲート電極
(4)(5)下に蓄積され、クロックφ3を印加された
上層ゲート電極(7)下でせき止められている。なお強
い入射光により過剰発生した電荷は、クロックφ1を印
加した上層ゲート電極(6)下のチャンネル分離領域
(3)を通して隣接したオーバーフロードレイン領域
(8)にあふれ出る。この蓄積された電荷は、次のフレ
ーム転送期間で4相駆動法により撮像部から蓄積部に転
送される。
次に偶数フィールドにおいて、光蓄積期間中クロック
パルスφ1,φ2およびφ4がVLにセットされ、クロック
パルスφ3はVMにセットされる。この期間中に光電変換
された電荷は、開口窓(10)周辺のクロックφ3を印加
された上層ゲート電極(7)、クロックφ2,φ4を印加
された下層ゲート電極(4)(5)下に蓄積され、クロ
ックφ1を印加された上層ゲート電極(6)下でせき止
められている。この電荷は同様にフレーム転送期間中に
4相駆動法により撮像部から蓄積部に転送される。
なお光蓄積期間およびフレーム転送期間を通してオー
バーフロードレイン領域(8)のOFD電圧はチャンネル
分離領域(3)のポテンシャルよりも深いポテンシャル
を与える必要がある。この理由はオーバーフロードレイ
ン領域(8)からチャンネル領域(9)への電荷の逆流
を阻止するためである。従ってチャンネル分離領域
(3)のポテンシャルはフレーム転送期間に上層ゲート
電極(6)(7)にVHを印加した時に最も深くなり、OF
D電圧は上層ゲート電極(6)(7)にVHを印加した時
のチャンネル分離領域(3)のポテンシャルよりも高い
DC電圧に固定されていた。
以上に述べた従来技術は、例えば工業調査会発行電子
材料1986年3月号、P123〜P127に記載されている。
(ハ)発明が解決しようとする問題点
しかしながら斯上した従来のFT方式CCDの駆動方法で
は、1/2インチ形光学系の場合には、20万画素のCCDを30
万画素に高解像度化すると、1画素当りの開口窓(10)
の面積が約7割減少することになる。このために開口窓
(10)の面積減少により感度の低下が発生する問題点を
有していた。
この感度の低下は、開口窓(10)で光電変換された電
荷がオーバーフロードレイン領域(8)に流出する割合
が増加するものと考えられる。第7図は撮像部のCCDの
拡大図であり、偶数フィールドの光蓄積期間を示してい
る。このときのVIII−VIII線断面のポテンシャルは第8
図に示されている。即ち、オーバーフロードレイン領域
(8)には最も深いポテンシャルが与えられているの
で、開口窓(10)で発生した点線で示す電荷はオーバー
フロードレイン領域(8)の電界により点線の矢印で示
される様にオーバーフロードレイン領域(8)に流出し
てしまうのである。
(ニ)問題点を解決するための手段
本発明は斯上した問題点に鑑みてなされ、開口窓下の
開口領域のオーバーフロードレイン領域側を高不純物濃
度に形成することにより、従来の問題点を改善した固体
撮像素子を提供するものである。
(ホ)作用
本発明に依れば、開口窓(10)下の開口領域(11)に
不純物濃度を異ならせて、オーバーフロードレイン領域
(8)側のポテンシャルを浅くしているので、開口領域
(11)で発生した電荷はオーバーフロードレイン領域
(8)に流入させることなくチャネル領域(9)に流入
させて、感度の低下を防止している。
(ヘ)実施例
本発明の実施例を第1図乃至第3図を参照して詳述す
る。
第1図は撮像部のCCDの拡大図であり、偶数フィール
ドの光蓄積期間を示している。第2図は第1図のII−II
線断面のポテンシャルを示している。第1図および第2
図は第7図および第8図と対応しており、同一構成要素
には同一符号を付してある。
本発明の特徴は開口窓(10)下の開口領域(11)にP+
型高不純物濃度領域(12)とP型又はN型低不純物濃度
領域(13)とを設け、開口領域(11)にポテンシャル勾
配をつけたことにある。即ち、高不純物濃度領域(12)
は第1図に示す如く、開口窓(10)のチャンネル分離領
域(3)と隣接する下層ゲート電極(4)(5)に沿っ
て周辺にコの字状に形成され、ゲート酸化膜(2)上に
突出した上層ゲート電極(7)の方にコの字の開口を向
けている。そして開口領域(11)の中央部は低不純物濃
度領域(13)が設けられている。
斯上した開口領域(11)の高不純物濃度領域(12)と
低不純物濃度領域(13)は次のように形成される。
第1の方法としては、開口領域(11)全面にボロンを
ドーズ量8×1011cm-2、加速電圧70KeVでイオン注入し
て、開口領域(11)全体をP-型の低不純物濃度領域(1
3)とする。次に開口領域(11)の中央部をレジスト層
でマスクして、開口領域(11)のチャンネル分離領域
(3)および隣接した下層ゲート電極(4)(5)と接
する周辺部にボロンをドーズ量5×1012cm-2、加速電圧
70KeVで追加イオン注入して、開口領域(11)の3辺の
周辺部にP+型の高不純物濃度領域(12)を形成する。
第2の方法としては、開口領域(11)全面にボロンを
ドーズ量5×1012cm-2、加速電圧70KeVでイオン注入し
て、開口領域(11)全体をP+型の高不純物濃度領域(1
2)とする。次に開口領域(11)の周辺部をレジスト層
でマスクして、開口領域(11)の中央部にリンをイオン
注入して中央部をN-型の低不純物濃度領域(13)に反転
させる。
上述した周辺部に高不純物濃度領域(12)を有し、中
央部に低不純物濃度領域(13)を有する開口領域(11)
を持つ本発明のCCDは、第2図に示す様なポテンシャル
を有している。即ち、開口領域(11)を除く各領域のポ
テンシャルは第8図と一致しているが、第8図では開口
領域(11)が平坦なポテンシャルであったものが、第2
図では高不純物濃度領域(12)で浅いポテンシャルにな
り、低不純物濃度領域(13)で深いポテンシャルにな
る。従って開口窓(10)で発生した点線で示す電荷は高
不純物濃度領域(12)で形成された浅いポテンシャル障
壁によりオーバーフロードレイン領域(8)側に流出せ
ず、略全部の発生電荷を実線の矢印に示すようにチャン
ネル領域(9)に流入させる。この結果、開口窓(10)
での発生電荷を略全部チャンネル領域(9)に効率良く
流入でき、感度を従来より約30%向上できる。
第3図は本発明の固体撮像素子の他の実施例を示す。
この実施例の特徴は、高不純物濃度領域(12)をT字状
に形成さたものである。即ち、高不純物濃度領域(12)
はチャンネル分離領域(3)の周辺と開口窓(10)の中
央部に形成される。従ってチャンネル分離領域(3)に
沿って周辺に設けた高不純物濃度領域(12)は開口窓
(10)での発生電荷のオーバーフロードレイン領域
(8)への流入を防止する役割を有し、中央部に設けた
高不純物濃度領域(12)は光蓄積期間における発生電荷
のチャンネル領域(9)でのせき止め障壁として働く役
割を有している。
斯上した本発明の固体撮像素子は第6図に示すクロッ
クパルスφ1,φ2,φ3,φ4で駆動され、動作原理も従来
のものと同一であるので説明は省略する。
(ト)発明の効果
本発明に依れば、開口窓(10)下の開口領域(11)の
少くともチャンネル分離領域(3)に沿った周辺に高不
純物濃度領域(12)を設け、その部分のポテンシャルを
浅く設定しているので、開口窓(10)での発生電荷がこ
のポテンシャル勾配によりほぼチャンネル領域(9)へ
流入され、短波長光感度は従来より約30%向上できる利
点を有する。The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device using a frame transfer method. (B) Conventional technology Solid-state imaging devices include an interline transfer (IT) type CCD (Charge Coupled Device) and a frame transfer (FT) type CCD. The imaging area and the accumulation area are alternately arranged in the IT CCD, and the imaging section and the accumulation section are separately arranged in the FT CCD. 4 and 5 show the structure of the imaging unit of the FT type CCD. This imaging unit adopts a cross gate structure,
(1) is a P-type silicon substrate, (2) is a gate oxide film,
(3) is a channel isolation region made of a field oxide film having a LOCOS structure, (4) and (5) are lower gate electrodes made of polysilicon extending in a horizontal direction, and (6).
(7) is an upper gate electrode made of polysilicon extending in the vertical direction, (8) is an N + -type overflow drain region, (9) is an N-type meandering channel region, (10)
Denotes an opening window, and (11) denotes a P + type opening region provided below the opening window (10). Such an FT type CCD is driven by clock pulses shown in FIG. The clock pulses φ 1 and φ 3 are applied to the upper gate electrodes (6) and (7) alternately, and the clock pulses φ 2 and φ 4 having three levels of V L , V M and V H are applied to the lower gate electrodes. (4) Every other voltage is applied to (5) and has two levels, V L and V H. 2: 1 in an odd field of interlace driving, the clock pulses phi 2, phi 3 and phi 4 are set to V L, the clock pulses phi 1 is set to V M enters the light accumulating period. Photoelectrically converted charge during the light accumulation period, opening window (10) around the clock phi 1 the applied upper gate electrode (6), the clock phi 2, lower gate electrode applied to phi 4 (4) (5) are accumulated under, are dammed up clock phi 3 in the upper gate electrode (7) under applied to. Incidentally charges excessively generated by a strong incident light, overflows to the overflow drain region adjacent through upper gate electrode of applying a clock phi 1 (6) the channel separation region (3) of the lower (8). The stored charges are transferred from the imaging unit to the storage unit by the four-phase driving method in the next frame transfer period. Next, in the even field, the light storage period in the clock pulses phi 1, phi 2 and phi 4 are set to V L, the clock pulse phi 3 is set to V M. Photoelectrically converted charge during this period, opening window (10) around the clock phi 3 the applied upper gate electrode (7), the clock phi 2, phi 4 lower gate electrode (4) applied to (5 ) is accumulated under, are dammed up clock phi 1 in the upper gate electrode (6) under applied to. This charge is similarly transferred from the imaging unit to the storage unit by the four-phase driving method during the frame transfer period. The OFD voltage of the overflow drain region (8) needs to give a potential deeper than the potential of the channel separation region (3) throughout the light accumulation period and the frame transfer period. The reason for this is to prevent backflow of charges from the overflow drain region (8) to the channel region (9). Therefore, the potential of the channel isolation region (3) becomes deepest when VH is applied to the upper gate electrodes (6) and (7) during the frame transfer period, and OF
The D voltage is higher than the potential of the channel isolation region (3) when VH is applied to the upper gate electrodes (6) and (7).
DC voltage was fixed. The prior art described above is described, for example, in Electronic Materials, March 1986, P123 to P127 issued by the Industrial Research Council. (C) Problems to be Solved by the Invention However, in the conventional FT CCD driving method described above, in the case of a 1 / 2-inch optical system, a CCD of 200,000 pixels requires 30
When the resolution is increased to 10,000 pixels, the aperture window per pixel (10)
Is reduced by about 70%. For this reason, there is a problem that the sensitivity is reduced due to the reduction in the area of the opening window (10). This decrease in sensitivity is considered to increase the rate at which the charges photoelectrically converted in the opening window (10) flow out to the overflow drain region (8). FIG. 7 is an enlarged view of the CCD of the imaging unit, and shows a light accumulation period of an even field. At this time, the potential of the section along the line VIII-VIII is
It is shown in the figure. That is, since the deepest potential is given to the overflow drain region (8), the electric charge shown by the dotted line generated in the opening window (10) is caused by the electric field of the overflow drain region (8) as shown by the dotted arrow. It flows out to the overflow drain region (8). (D) Means for Solving the Problems The present invention has been made in view of the above problems, and the conventional problems are solved by forming the overflow drain region side of the opening region below the opening window with a high impurity concentration. An object of the present invention is to provide an improved solid-state imaging device. (E) Function According to the present invention, the opening region (11) under the opening window (10) is made different in impurity concentration to make the potential on the overflow drain region (8) side shallower. The charge generated in 11) flows into the channel region (9) without flowing into the overflow drain region (8), thereby preventing a decrease in sensitivity. (F) Embodiment An embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is an enlarged view of a CCD of an imaging unit, and shows a light accumulation period of an even field. FIG. 2 is II-II of FIG.
The potential of the line cross section is shown. FIG. 1 and FIG.
The drawings correspond to FIGS. 7 and 8, and the same components are denoted by the same reference numerals. The feature of the present invention is that the P +
A high impurity concentration region (12) and a P-type or N-type low impurity concentration region (13) are provided, and a potential gradient is applied to the opening region (11). That is, the high impurity concentration region (12)
As shown in FIG. 1, the gate oxide film (2) is formed around the lower gate electrodes (4) and (5) adjacent to the channel isolation region (3) of the opening window (10). The U-shaped opening is directed toward the upper gate electrode (7) protruding upward. A low impurity concentration region (13) is provided at the center of the opening region (11). The high impurity concentration region (12) and the low impurity concentration region (13) of the opening region (11) are formed as follows. As a first method, boron is ion-implanted into the entire surface of the opening region (11) at a dose of 8 × 10 11 cm −2 and an acceleration voltage of 70 KeV, and the entire opening region (11) is a P − -type low impurity concentration region. (1
3) Next, a central portion of the opening region (11) is masked with a resist layer, and boron is dosed to a peripheral portion of the opening region (11) in contact with the channel isolation region (3) and the adjacent lower gate electrodes (4) and (5). Volume 5 × 10 12 cm -2 , acceleration voltage
Additional ions are implanted at 70 KeV to form a P + -type high impurity concentration region (12) around the three sides of the opening region (11). As a second method, boron is ion-implanted into the entire surface of the opening region (11) at a dose of 5 × 10 12 cm −2 and an acceleration voltage of 70 KeV, and the entire opening region (11) is a P + -type high impurity concentration region. (1
2) Next, the peripheral portion of the opening region (11) is masked with a resist layer, and phosphorus is ion-implanted into the central portion of the opening region (11) to invert the central portion to an N − type low impurity concentration region (13). . An opening region (11) having a high impurity concentration region (12) in the peripheral portion described above and a low impurity concentration region (13) in the center portion
The CCD of the present invention having the potential has the potential as shown in FIG. That is, the potentials of the respective regions except the opening region (11) match those of FIG. 8, but in FIG. 8, the potential of the opening region (11) is a flat potential.
In the figure, the potential becomes shallow in the high impurity concentration region (12) and becomes deep in the low impurity concentration region (13). Therefore, the electric charge indicated by the dotted line generated in the opening window (10) does not flow out to the overflow drain region (8) side due to the shallow potential barrier formed in the high impurity concentration region (12), and almost all the generated electric charge is replaced by a solid arrow. As shown in FIG. As a result, the opening window (10)
, And almost all the charges generated in the channel region can efficiently flow into the channel region (9), and the sensitivity can be improved by about 30% as compared with the conventional case. FIG. 3 shows another embodiment of the solid-state imaging device of the present invention.
The feature of this embodiment is that the high impurity concentration region (12) is formed in a T shape. That is, the high impurity concentration region (12)
Are formed at the periphery of the channel separation region (3) and at the center of the opening window (10). Therefore, the high impurity concentration region (12) provided along the periphery along the channel isolation region (3) has a role of preventing the charge generated in the opening window (10) from flowing into the overflow drain region (8). The high-impurity-concentration region (12) provided in the portion functions as a barrier for blocking the generated charges in the channel region (9) during the light accumulation period. The above-described solid-state imaging device of the present invention is driven by clock pulses φ 1 , φ 2 , φ 3 , φ 4 shown in FIG. 6 and its operation principle is the same as that of the conventional one, so that the description is omitted. According to the present invention, a high impurity concentration region (12) is provided at least around the opening region (11) below the opening window (10) along the channel separation region (3). Since the potential of the portion is set to be shallow, the charges generated in the opening window (10) are almost flowed into the channel region (9) by this potential gradient, and the short-wavelength light sensitivity can be improved by about 30% as compared with the related art. .
【図面の簡単な説明】
第1図は本発明による固体撮像素子の撮像部のCCDを説
明する上面図、第2図は第1図のII−II線断面のポテン
シャル図、第3図は本発明の他の実施例による固体撮像
素子の撮像部のCCDを説明する上面図、第4図はFT方式C
CDを説明する上面図、第5図は第4図のV−V線断面
図、第6図は従来の駆動方法に用いるクロックパルスの
タイミングチャート図、第7図は従来のFT方式CCDの撮
像部のCCDを説明する上面図、第8図は第7図のVIII−V
III線断面のポテンシャル図である。
(1)は半導体基板、(2)はゲート酸化膜、(3)は
チャンネル分離領域、(4)(5)は下層ゲート電極、
(6)(7)は上層ゲート電極、(8)はオーバーフロ
ードレイン領域、(9)はチャンネル領域、(10)は開
口窓、(11)は開口領域、(12)は高不純物濃度領域、
(13)は低不純物濃度領域である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a top view for explaining a CCD of an imaging unit of a solid-state imaging device according to the present invention, FIG. 2 is a potential diagram taken along the line II-II in FIG. 1, and FIG. FIG. 4 is a top view illustrating a CCD of an imaging unit of a solid-state imaging device according to another embodiment of the present invention.
FIG. 5 is a top view for explaining a CD, FIG. 5 is a sectional view taken along line VV of FIG. 4, FIG. 6 is a timing chart of clock pulses used in a conventional driving method, and FIG. FIG. 8 is a top view illustrating a CCD of a part, and FIG.
FIG. 3 is a potential diagram of a cross section taken along line III. (1) is a semiconductor substrate, (2) is a gate oxide film, (3) is a channel isolation region, (4) and (5) are lower gate electrodes,
(6) (7) is an upper gate electrode, (8) is an overflow drain region, (9) is a channel region, (10) is an opening window, (11) is an opening region, (12) is a high impurity concentration region,
(13) is a low impurity concentration region.
Claims (1)
され、光蓄積期間中に前記撮像部で光電変換により電荷
の蓄積を行い、フレーム転送期間中に前記光電変換電荷
を前記撮像部から前記蓄積部へ転送するフレームトラン
スファ方式の固体撮像素子において、 前記撮像部は、前記半導体基板の表面に一方向に延在し
て互いに平行に形成され、過剰電荷を吸収するオーバー
フロードレイン領域を含む複数のチャンネル分離領域
と、前記複数のチャンネル分離領域の間で光電変換によ
り電荷を発生すると共に、発生した光電変換電荷が転送
される複数のチャンネル領域と、前記複数のチャンネル
領域上に2層に形成され、前記チャンネル領域内のポテ
ンシャルの状態を制御する複数のゲート電極と、を備
え、前記複数のゲート電極の間に前記チャンネル領域上
で一辺が前記チャンネル分離領域上に架かる開口窓を形
成し、前記開口窓内の開口領域を前記チャンネル分離領
域側で高不純物濃度に形成することを特徴とする固体撮
像素子。(57) [Claims] An imaging unit and a storage unit are separately arranged on a semiconductor substrate, and charge is accumulated by photoelectric conversion in the imaging unit during a light accumulation period, and the photoelectric conversion charge is transferred from the imaging unit to the photoelectric conversion unit during a frame transfer period. In a solid-state imaging device of a frame transfer system for transferring to a storage unit, the imaging unit is formed on a surface of the semiconductor substrate in one direction and formed in parallel with each other, and includes a plurality of overflow drain regions that absorb excess charges. A channel separation region, a plurality of channel regions in which charges are generated by photoelectric conversion between the plurality of channel separation regions, and the generated photoelectric conversion charges are transferred, and two layers are formed on the plurality of channel regions. A plurality of gate electrodes for controlling a state of potential in the channel region, wherein the channel is provided between the plurality of gate electrodes. A solid-state imaging device, wherein an opening window having one side extending over the channel separation region is formed on the tunnel region, and an opening region in the opening window is formed with a high impurity concentration on the channel separation region side.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62063322A JP2698072B2 (en) | 1987-03-18 | 1987-03-18 | Solid-state imaging device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62063322A JP2698072B2 (en) | 1987-03-18 | 1987-03-18 | Solid-state imaging device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63228747A JPS63228747A (en) | 1988-09-22 |
JP2698072B2 true JP2698072B2 (en) | 1998-01-19 |
Family
ID=13225912
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62063322A Expired - Lifetime JP2698072B2 (en) | 1987-03-18 | 1987-03-18 | Solid-state imaging device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2698072B2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3317248B2 (en) | 1998-09-18 | 2002-08-26 | 日本電気株式会社 | Solid-state imaging device |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63114252A (en) * | 1986-10-31 | 1988-05-19 | Sony Corp | Solid-state image sensing device |
-
1987
- 1987-03-18 JP JP62063322A patent/JP2698072B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS63228747A (en) | 1988-09-22 |
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