JPH0548998B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image display terminal device, and particularly to an improvement of its clock control section.

[Summary of the Invention] The present invention relates to an image display terminal device, particularly to its clock control unit, and relates to a video RAM device in which image data extracted from line data and address data specifying a character of a character generator are stored in a cycle-steal manner. As an address forming means, the address forming clock for character specification (CRTC clock) is configured to always maintain a predetermined phase difference with respect to the address forming clock for the CPU (CPU clock). This prevents the phase fluctuation of the character address forming clock relative to the CPU address forming clock due to variations in the clock forming circuit for character address forming or temperature characteristics, thereby eliminating disturbances in the playback screen. be.

[Conventional technology]

As is well known, the PRESTEL terminal device has the configuration shown in FIG.

In the figure, line data is supplied via a line control unit 1 to a decoder 2 consisting of a computer for processing image data, and the processed image data is stored in a video RAM 3, and the data is used to create a character. The generator 4 is controlled to form a display image signal corresponding to the image data, which is displayed on the monitor 5.

The decoder 2 and video RAM 3 are controlled based on various clocks generated from a clock control section 10.

FIG. 4 is a system diagram showing an example of a conventionally known clock control section 10, and in this example, as mentioned above, the video RAM 3 stores each data by cycle stealing.
Clock formation circuit for CPU address formation (first
(15) and a second clock forming circuit 23 for forming address data for specifying a character for the character generator 4.

14 is a reference clock generation source, and the frequency of the reference clock a (FIG. 5A) obtained from this is 12 MHz in this example. The reference clock a is counted down to 1/6 at count 16 to form the pulse b shown in FIG. An output c is formed. Therefore, its frequency is 1MHz. This first FF output c output from the Q terminal is supplied to the D terminal of the D-type flip-flop 18. On the other hand, the reference clock a is phase-inverted by the inverter 28 and then supplied to the flip-flop 18 as a clock signal (D in the same figure). FF output d is formed.

The first FF output c and the second FF output d output from the flip-flops 17 and 18, respectively, are supplied to the first AND gate 19, thereby producing the first AND output (hereinafter for CPU) shown in FIG. A clock (referred to as a clock) e is formed, and the phase-inverted outputs of the first and second FF outputs c and d output from the Q terminals of the first and second flip-flops 17 and 18 are supplied to the NOR gate 20. , a clock signal f (not shown) whose phase is reversed from that of the clock signal e, and these signals are supplied to the CPU 21 constituting the decoder 2. Therefore, this CPU2
1 will be data processed in a 1MHz cycle.

A clock signal for forming a 1 MHz CPU address data output from the CPU 21 is supplied to the corresponding address forming circuit 11, and is sent to the video RAM.
Address data for CPU 3 is formed. Although not shown in the address forming circuit 11,
CAS obtained from the first clock forming circuit 15
(Column Address Stable) Pulse and RAS
(Row Address Stable) pulse is supplied.

The second clock forming circuit 23 has a clock forming section 24 for forming addresses for specifying characters, and various clock signals (RAS pulses, etc.) for forming address data outputted from this section are used to form the second address. Video supplied to circuit 12
Address data for RAM3 is formed.

Each address signal of the first and second address forming circuits 11 and 12 is sent to an address switching circuit 13.
The signal is supplied to the video RAM 3 via the . The switching pulse uses the CPU clock e.

The frequency of the clock formed by the clock forming section 24 is the same as the frequency of the first AND output, that is, the CPU clock e. The CPU 21 executes data processing by cycle stealing, and in this example, the latter half cycle of the CPU clock e is used as the CPU processing period.
The first half cycle is used as a character specification processing period.

1MHz clock signal (hereinafter referred to as CRTC clock) output from the clock forming section 24 h
(FIG. 5G) shows the OR gate 25 that constitutes the clock formation timing control system together with the first FF output c.
CRTC for the first FF output c
The phases of the clock signals h are compared, and the OR gate output i (H in the figure), which is the phase comparison output, is supplied to the AND gate 26. This and gate 2
6 is supplied with a reference clock a, and the gate state of the reference clock a is controlled based on the OR gate output i. The AND gate output j (I in the figure) is stepped down by 1/2 by a counter 27, and based on this, the clock generation timing of the clock control section 24 is controlled. As a result, the output timing of the address signals of the address forming circuits 11 and 12 is controlled to be constant.

[Problem that the invention seeks to solve]

By the way, the CRTC address signal is formed from the address forming clock obtained from the clock forming section 24, and the CRTC address signal is used to generate the video signal.
RAM3 is accessed, but this video RAM
Both the CAS pulse and the RAS pulse for clock signal No. 3 are generated from the first clock forming circuit 15. Therefore, in order for the video RAM 3 to be accessed normally, the clock timings of the first and second clock forming circuits 15 and 23 must always maintain a constant relationship.

Moreover, since the IC of the clock forming section 24 has variations and has temperature characteristics, the phase of the clock signal supplied to the second address forming circuit 12 fluctuates.

For this reason, in order to create the above-mentioned timing relationship, conventionally the first
The phases of FF output c and CRTC clock h are compared. An example of the operation will be explained with reference to FIG.

Now, the first FF supplied to the OR gate 25
If the phase relationship between the output c and the CRTC clock h is as shown in Figure 5 F and G, and the phase difference φ is within 1 clock (with respect to a 1MHz clock), then the OR gate shown in Figure 5H Since an output i is obtained, which gates the reference clock a,
The gate output j is shown in the same figure. In this case, although the pulse width of the reference clock a becomes narrower, the clock timing does not become discontinuous and the counter output k
(J in the same figure) remains unchanged.

On the other hand, when the phase difference φ becomes 1 clock or more, the reference clock a becomes discontinuous, as is clear from K to M in the figure, and this causes the counter output k to
The pulse width (N in the figure) becomes wider than before, and the rising timing of the CRTC clock h becomes delayed, so that the phase of the CRTC clock h approaches the phase of the CPU clock e.

However, in this conventional clock timing control, the control system does not operate unless there is a phase difference φ of at least one clock, so the phase shifts by at least one clock.

On the other hand, if a video RAM 3 with a fast access time is used, the video RAM 3 may not be accessed correctly due to such clock shifts, and the screen on the monitor 5 may become distorted.

This is because, as shown in FIG. 5F, the first half of the CPU clock e is
This is the access period for the CRTC address signal, and the latter half is the access period for the CPU address signal, and the address signal used by the CPU 21 must be determined during the CRTC period.

For this reason, the various clock signals (Row and Column addresses) output from the second clock forming circuit 23 to the video RAM 3 will be
This is because the video RAM 3 is no longer stable when accessed during the CRTC period, resulting in the above-mentioned screen disturbance.

Therefore, the present invention is an attempt to solve these problems, and is designed to prevent the phase difference between clocks e and h from being more than one clock.

[Means for solving problems]

In order to solve the above-mentioned problems, in the present invention, in the clock control section 10 shown in FIG.
The CRTC clock e and the CRTC clock h output from the clock forming section 24 are used.

[Effect]

According to this configuration, when the phase difference φ between the clocks e and h becomes 0.5 clock or more as shown in FIG. Since the phase of the operating clock h is corrected, the phase difference φ is
It will never be more than 0.5 clocks.

As long as such a phase difference, high-speed video
Even if RAM3 is used, there will be no instability when accessing video RAM3. As a result, even if the video RAM 3 having a short access time is used, screen distortion does not occur.

〔Example〕

FIG. 1 is a block diagram showing an example of a clock control section 10 used in an image display terminal device according to the present invention, and the same parts as those shown in FIG. 4 are designated by the same reference numerals. The explanation will be omitted.

In this invention, [Means for solving the problem]
As explained in the above section, as the phase comparison clock supplied to the OR gate 25, in addition to the CRTC clock h, the CPU clock e outputted from the first AND gate 19 is used.

Now, when the CPU clock e is supplied to the OR gate 25, the
If the phase difference φ of the CRTC clock h is within 0.5 clocks as shown in Figure 2 F and G, the second
The continuity of the clock of the AND gate output j gated by the AND gate 26 is maintained as it is (I, J in the same figure). In that case, the pulse width of the counter output k will be different at this point, but the periodic operation of the counter 27 will be the same as before. Therefore, the generation timing of the CRTC clock h formed based on the counter output j remains unchanged.

However, when the phase difference φ between the CRTC clock h and the CPU clock e becomes 0.5 clocks or more as shown in FIG. 2F and K, the AND gate output j gated by the second AND gate 26 The continuity of the clock is disturbed in the section where the AND gate output j is obtained, and the clock is not output in this section (as shown by the broken line in M in the figure). Therefore, the pulse width of the counter output k (N in the same figure) becomes more than one clock at this point, and the frequency division period of the counter output k becomes more than its basic period. Therefore, the generation timing of the CRTC clock h, which is formed based on the counter output j, is delayed by that amount, and as a result, the generation timing of the CRTC clock h is delayed, and the phase of the CPU clock e is further delayed. approach.

Due to such a clock timing control operation, the phase difference φ between the CRTC clock h and the CPU clock e does not increase by more than 0.5 clocks. If the phase difference φ is within 0.5 clocks,
CRTC period even if high-speed video RAM 3 is used
Address signals to the CPU can be determined.

〔Effect of the invention〕

As explained above, in this invention, the clock formation timing of the second clock formation circuit 23 is controlled using the CPU clock e and the CRTC clock h.
The phase difference φ between the CRTC clock h can be limited to within 0.5 clocks, and thereby the phase difference φ between the two clocks e and h can always be kept substantially constant. Therefore, the video RAM 3 can be accessed correctly at all times, and there is a practical effect that can overcome the drawbacks of the conventional method, such as causing disturbances in the monitor screen, by just slightly changing the conventional circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram showing an example of a clock control section used in an image display terminal device according to the present invention;
Figure 2 is a waveform diagram to explain its operation, and Figure 3 is a waveform diagram to explain its operation.
System diagram showing an example of a PRESTEL terminal device, No. 4
The figure is a connection diagram showing an example of a conventional clock control section used for this, and FIG. 5 is a waveform diagram for explaining its operation. 1 is line control unit, 2 is decoder, 3 is video
RAM, 4 is a character generator, 10 is a clock control section, 14 is a reference clock generation source, 15, 23
are first and second clock forming circuits, 11 and 12;
is an address forming circuit, 19 is a first AND circuit,
25 and 26 are gate circuits that constitute a clock timing control system, e is a CPU clock, and h is a clock for the CPU.
This is a CRTC clock.

Claims (1)

[Claims] 1. A video device that stores image data and character generator address data in an image display terminal device.
A RAM, a character generator controlled by the data thereof, and a clock control section for controlling addressing of the video RAM, the clock control section having a reference clock generation source;
an address forming circuit for storing data from the CPU for image data processing in the video RAM; an addressing circuit for specifying addresses for the character generator via the video RAM; a first clock forming circuit that forms a clock for the CPU that is output from the reference clock; and a second clock forming circuit that forms a clock for specifying a character from the reference clock that has the same frequency as the clock for the CPU and has a predetermined phase difference therefrom.
and a clock forming circuit, and the clock forming timing of the second clock forming circuit is controlled from the character specifying clock obtained from the second clock forming circuit and the CPU clock. Image display terminal device.