JPS62214478A - Image data storage device - Google Patents

Abstract

PURPOSE:To store image data stably regardless of disturbance of a synchronizing signal by writing data successively with only a timing control circuit and the operation of a D-RAM when data write is started. CONSTITUTION:Image data from an image data output device is stored in a D-RAM 5. The storage of image data in the D-RAM 5 and the output of stored image data are controlled by a timing control circuit 1. The timing control circuit 1 generates a memory access permission signal and a prescribed number of clock pulses in response to the synchronizing signal from the image data output device. While the memory access permission signal is applied, image data from the image data output device is stored in the D-RAM 5 in response to the clock pulse.

Description

[Detailed Description of the Invention] [Summary] Dynamically converts image data from an image data output device.
When storing data in random access memory (D-RAM), the timing control circuit first outputs a memory access enable signal based on the synchronization signal from the image data output device, and then generates a predetermined number of clock pulses. , D-1? Image data is stored in the AM as many times as there are clock pulses.

[Industrial application field]

The present invention relates to an image data storage device.

[Conventional technology]

Image data storage devices are known that accept image data from an image data output device such as a CRT display device, store it digitally, and enable it to be redisplayed via a printer in hard copy or on a display device. . Such an image data storage device is provided with a memory for storing digital data, and is usually realized by a RAM. Static RAM has excellent high speed and operational stability, but
Due to its high cost and large capacity, D-RAM is often used.

The image data sent from the CRT display device to the D-RAM complies with the vertical synchronization signal and horizontal synchronization signal based on the NTSC standard, and the image data is stored in the D-RAM based on these synchronization signals. It is.

[Problem that the invention seeks to solve]

If image data storage in the D-RAM is directly associated with the synchronization signal, if a situation occurs in which the synchronization signal deviates from the NTSC standard due to a disturbance applied between the CRT display device and the D-RAM, the D-RAM I ran into a problem where the data already stored in my computer was destroyed. That is,
The row address select RAS, column address select CAS signals, etc. in D-RAM operate with delicate timing, and if these signals are generated in direct association with the synchronization signal, RAS and CAS will be affected due to the disturbance of the synchronization signal.
The signal is also disturbed, a mode similar to a refresh mode occurs in the D-RAM, and existing data is destroyed.

[Means and effects for solving the problem] The present invention solves the above-mentioned problem related to data destruction,
In the present invention, a dynamic random access memory that stores image data from an image data output device;
and a timing control circuit that controls storage of image data to the memory or output of stored image data,
The timing 1118 circuit generates a memory access enable signal and a predetermined number of clock pulses in response to a synchronization signal from the image data output device, and the memory is activated when the memory access enable signal is applied. An image data storage device is provided, characterized in that the image data storage device stores image data from the image data output device in response to the clock pulse.

〔Example〕

Embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 shows a circuit diagram of a timing control circuit according to an embodiment of the present invention. Timing control circuit 1 is D-RAM
In addition to storing the image data DATA to the output device 5, it also controls the output of the stored image data DAT to the subsequent output device, but the latter is not directly related to the present invention and will therefore be omitted.

The timing control circuit 1 includes a sample clock counter 1
1, horizontal synchronization signal counter 12, gate 13, sample clock generator 14, D-type flip-flops 15 to 20
and address generation counter 21 are connected as shown.

A vertical synchronizing signal V-5YNC and a horizontal synchronizing signal H-SYNC are applied from an image data output device (not shown) to the timing control circuit 1, and the image data DATA to be stored in the D-RAM 5 is directly stored in the D-RAM. 5 is applied. In this embodiment, one image data is stored as 4-bit data.

Vertical synchronization signal V-5 output from the image data output device
The relationship between YNC and horizontal synchronization signal H-SYNC is shown in Figure 2 (
a) Shown in (b). The first vertical synchronization signal VSI and the second
The time interval between vertical synchronization signal VS2 is 16.7+n
a, during which each time interval, e.g.
The horizontal synchronization signal H-5YNC is 25n, and the time between the horizontal synchronization signal H3I and the second horizontal synchronization signal 11s2 is 63.5n.
There are 6 zeros in a row. The above is a case where the resynchronization signal is normal, but from the perspective of the D-RAM side or the timing control circuit side, due to disturbance etc., the horizontal synchronization signal disappears or increases on the way, or it appears before the vertical synchronization signal. A horizontal synchronization signal may appear.

The operation of the control circuit shown in FIG. 1 will be described with reference to FIG. 2 (al-01).

When it is desired to store image data from the image data output device in the image data storage device, the image data storage device is initialized and the reset signal R[ESET is output from the flip-flop 19.
is applied to the preset terminal PR of.

As a result, the flip-flop 19 is pre-centered,
The flip-flop 20 is also preset by the output. The output of the flip-flop 20, that is, the signal VIDEO which enables writing in the D-RAM 5 (enabling memory access) when it is at a low level, is at a high level.

By applying the vertical synchronization signal V-SYNC to the clock terminal GK of the flip-flop 20, the VIDEO signal becomes low level and the D-RAM 5 becomes accessible (FIG. 2(a) (C1)).

The vertical synchronizing signal V-3YNC is applied to the PH1 terminal of the flip-flop 17 via the PR terminal of the flip-flop 15°16.18, the clear terminal CL of the flip-flop 19, the CL terminal of the counter 21, and the gate 3. and preset or clear them.

The first horizontal synchronizing signal 11SI is applied to the (Ji) terminal of the flip-flop 17, and its Q output is applied to the flip-flop 17.
6, the Q output of the flip-flop 16 becomes a low level, that is, a level indicating a horizontal start state, and the horizontal start signal H
-STRT is output (FIG. 2(d)). The H-ST
R? In response to the signal, sample clock generator 14:
A sample clock pulse 5-CLK is generated (FIG. 2(e)). The sample clock pulse 5-CLK is applied to the CK terminals of the flip-flops 15, 16, and 1B and the CK terminal of the counter 12 in order to match the operation timings of the timing control circuit 1.

Also, the sample clock pulse 5-CLK is the counter 11.
is applied to CK@ and counted. Sample clock pulse 5-CLK is CK of address generation counter 2
address count signal A whose frequency is divided by 2
DCNTs are generated (FIG. 2(h)).

D-RAM 5 receives the above VIDEO signal and 5
-CLK.

Generate RAS and CAS signals according to ADCNT,
Write the image data DATA to the memory section (Fig. 2 (i)
U)) The counter 11 counts the sample clock pulses 5-CLK, and when it reaches a predetermined value, outputs the horizontal end signal H-END from the carry terminal CR (
Figure 2(f)). In this embodiment, the maximum number of data per -horizontal direction is 256, and 2 per address count.
sample clock pulses S-CLK are output, so the predetermined value is a maximum of 256X2=512. On the other hand, all 256 data are not saved, and about 240 are 0.
If you want to set the preset value CH of the counter 11 to
(256240) Set it as X2. That is, H
-END signal is output according to the amount of data to be saved per horizontal direction.

The H-END signal is applied to the D terminal of the flip-flop 16, and the H-3TPT signal becomes high level. As a result, the sample clock pulse 5-CLK is stopped with a slight delay. Therefore, data in the horizontal direction will not be saved from then on.

Also, the H-END signal is the enable terminal E of the counter 12.
The value of the counter 12 is incremented by one. The counter 12 receives the vertical synchronization signal V-
By applying 5YNC to the flip-flop 18, its 100 output is applied to the LOAD terminal,
Cv is set, and counts up from this preset value. In other words, this preset also has counter 1
Similar to 1.Bricent, if it is not necessary to save all the data in the vertical direction, set the value corresponding to the number of horizontal lines that do not need to be saved.

The same process as described above is performed when the second horizontal synchronization signal +1s2 is applied. 256th horizontal synchronization signal +13256
When the horizontal direction end signal H-END is applied, the carry-over signal from the counter 12, that is,
A vertical end signal V-END is output (FIG. 2 (bright)).

The V-EN[l signal passes through the flip-flop 19 to preset the flip-flop 20 and sets the VIDEO signal to high level (FIG. 2(C)). As a result, from now on, the D-RAM 5 will not occupy image data until a new vertical synchronization signal arrives.

As mentioned above, data writing starts in response to the synchronization signal.
The IDEO signal is generated, and each data write is performed in synchronization with the sample clock pulse 5-CIJ, and the writing is completed by generating the V-END signal when a predetermined number of sample clock pulses 5-CLK has been counted. Is going. That is, once data writing starts, data writing is performed sequentially only by the operations of the timing control circuit 1 and the D-RAM 5, and even if a synchronization signal is disturbed during the process, it will not be affected.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain an image data storage device that can stably store image data regardless of disturbances in synchronization signals.

[Brief explanation of drawings]

FIG. 1 is a timing M control circuit diagram as an embodiment of the present invention, and FIGS. 2(a) to (J) are signal timing diagrams of the circuit. (Explanation of symbols) 1... Timing control circuit, 5... D-RAM, 11... Sample clock counter, 12
... Horizontal synchronization signal counter, 14 ... Sample clock generator, 15-20 ... D-type flip-flop, 21 ... Address generation counter.

Claims (1)

[Claims] 1. A dynamic random access memory that stores image data from an image data output device, and a timing control circuit that controls storage of the image data to the memory or output of the stored image data. and the timing control circuit generates a memory access enable signal and a predetermined number of clock pulses in response to a synchronization signal from the image data output device, and the memory is configured to generate a memory access enable signal when the memory access enable signal is applied. 2. An image data storage device, wherein the image data storage device stores image data from the image data output device in response to the clock pulse.