JPH0548630B2 - - Google Patents
Info
- Publication number
- JPH0548630B2 JPH0548630B2 JP61000212A JP21286A JPH0548630B2 JP H0548630 B2 JPH0548630 B2 JP H0548630B2 JP 61000212 A JP61000212 A JP 61000212A JP 21286 A JP21286 A JP 21286A JP H0548630 B2 JPH0548630 B2 JP H0548630B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- type semiconductor
- conductivity type
- thyristor
- anode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 claims description 37
- 239000004065 semiconductor Substances 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 12
- 238000002955 isolation Methods 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 230000001681 protective effect Effects 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 108091006146 Channels Proteins 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、プレーナ型サイリスタの製造方法に
関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a planar thyristor.
従来、プレーナ型サイリスタは、次のようにし
て製造されている。先ず、第２図Ａに示す如く、
例えばＮ型半導体基板１の表面及び裏面に所定パ
ターンのマスク２を形成し、このマスク２を介し
て第２図Ｂに示す如く、半導体基板１内にＰ導電
型で環状のアイソレーシヨン層３を形成する。次
いで、第２図Ｃに示す如く、マスクを除去した
後、アイソレーシヨン層３を含む半導体基板１の
主面を保護膜４で覆う。次いで、露出した半導体
基板１の裏面側にＰ導電型の不純物を導入してア
ノード・エミツタ層５を形成する。次いで、第２
図Ｄに示す如く、保護膜４に所定のパターニング
を施しこれをマスクにしてＰ型不純物半導体基板
１内に導入し、ゲート・ベース層６を形成する。
然る後、第２図Ｅに示す如く、ゲート・ベース層
６内にカソード・エミツタ層７を形成すると共
に、半導体基板１内に高濃度のＮ型チヤンネルス
トツパ８を形成してプレーナ型サイリスタ１０を
得る。
Conventionally, planar thyristors have been manufactured as follows. First, as shown in Figure 2A,
For example, a mask 2 with a predetermined pattern is formed on the front and back surfaces of an N-type semiconductor substrate 1, and an annular isolation layer 3 of P conductivity type is formed in the semiconductor substrate 1 through the mask 2, as shown in FIG. 2B. form. Next, as shown in FIG. 2C, after removing the mask, the main surface of the semiconductor substrate 1 including the isolation layer 3 is covered with a protective film 4. Next, P conductivity type impurities are introduced into the exposed back side of the semiconductor substrate 1 to form an anode/emitter layer 5. Then the second
As shown in FIG. D, the protective film 4 is patterned in a predetermined manner, and using this as a mask, a P-type impurity is introduced into the semiconductor substrate 1 to form a gate/base layer 6.
Thereafter, as shown in FIG. 2E, a cathode/emitter layer 7 is formed in the gate/base layer 6, and a highly doped N-type channel stopper 8 is formed in the semiconductor substrate 1 to form a planar thyristor. Get 10 .
このような従来の方法では、アノード・エミツ
タ層５を及びゲート・ベース層６を夫々別の工程
で形成するため、極めて作業性が悪い問題があつ
た。この問題を解消するために、第２図Ｆに示す
如く、ゲート・ベース層６、及びアノード・エミ
ツタ層５を同一の工程で形成することが行われて
いる。しかし、このような方法によるものでは、
半導体基板１の両面に不純物を導入する工程が必
要であり、アノード・エミツタ層５と、ゲート・
ベース層６の表面濃度を変えたい場合、夫々の濃
度で複雑な処理によつて不純物を導入する工程が
必要であつた。更に、近年、半導体基板が厚肉化
しているため、不純物の導入に長時間を要する問
題があつた。 In such a conventional method, since the anode/emitter layer 5 and the gate/base layer 6 are formed in separate steps, there is a problem of extremely poor workability. In order to solve this problem, as shown in FIG. 2F, the gate/base layer 6 and the anode/emitter layer 5 are formed in the same process. However, with this method,
A process of introducing impurities into both sides of the semiconductor substrate 1 is required, and the anode/emitter layer 5 and the gate/emitter layer 5 are
When it is desired to change the surface concentration of the base layer 6, it is necessary to introduce impurities at each concentration through complicated processing. Furthermore, since semiconductor substrates have become thicker in recent years, there has been a problem in that it takes a long time to introduce impurities.
本発明は、写真蝕刻工程及び拡散工程を省略し
て簡略化された工程で容易にプレーナ型サイリス
タを得ることができるプレーナ型サイリスタの製
造方法を提供することをその目的とするものであ
る。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a planar thyristor which can be easily obtained through a simplified process by omitting the photolithography process and the diffusion process.
本発明は、アノード・エミツタ接合を基板接合
技術にて形成するようにしたことにより、写真蝕
刻工程及び拡散工程を省略して簡略化された工程
で容易にプレーナ型サイリスタを得ることができ
るプレーナ型サイリスタの製造方法である。
The present invention provides a planar type thyristor that can easily obtain a planar type thyristor through a simplified process by omitting the photolithography process and the diffusion process by forming the anode-emitter junction using substrate bonding technology. This is a method for manufacturing a thyristor.
以下、本発明の実施例について図面を参照して
説明する。
Embodiments of the present invention will be described below with reference to the drawings.
この実施例は、Ｐゲート型サイリスタの製造に
本発明方法を適用したものである。先ず、例えば
不純物濃度が1015cm-2オーダーで厚さが約150μｍ
のＮ型半導体基板２０と、不純物濃度が1018cm-2
オーダーで厚さが約100μｍのＰ型半導体基板２
１を用意し、夫々の表面に鏡面加工を施す。次い
で、第１図Ａの示す如く、Ｎ型半導体基板２０の
鏡面加工を施した表面全面をレジスト膜２２ａで
覆うと共に、鏡面加工を施していない裏面側を所
定形状のレジスト膜２２ｂで覆う。次いで、レジ
スト膜２２ｂをマスクにしてホウ素を表面濃度が
1017〜1018cm-2程度になるようにしてＮ型半導体
基板２０の裏面から表面にかけて導入し、Ｐ型の
アイソレーシヨン層２３を形成する。ここで、レ
ジスト膜２２ａ，２２ｂの形状をアイソレーシヨ
ン層２３に応じて所定のものとし、Ｎ型半導体基
板２０の両面からホウ素を導入するようにしても
良い。 In this example, the method of the present invention is applied to manufacturing a P-gate type thyristor. First, for example, the impurity concentration is on the order of 10 15 cm -2 and the thickness is about 150 μm.
N-type semiconductor substrate 20 with an impurity concentration of 10 18 cm -2
P-type semiconductor substrate 2 with a thickness of approximately 100μm made to order
1 is prepared, and the surfaces of each are mirror-finished. Next, as shown in FIG. 1A, the entire mirror-finished surface of the N-type semiconductor substrate 20 is covered with a resist film 22a, and the back surface, which has not been mirror-finished, is covered with a resist film 22b having a predetermined shape. Next, using the resist film 22b as a mask, the surface concentration of boron is
It is introduced from the back surface to the front surface of the N-type semiconductor substrate 20 at a concentration of about 10 17 to 10 18 cm −2 to form a P-type isolation layer 23 . Here, the resist films 22a and 22b may have a predetermined shape depending on the isolation layer 23, and boron may be introduced from both sides of the N-type semiconductor substrate 20.
次に、第２図Ｂに示す如く、Ｎ型半導体基板２
０上のレジスト膜２２ａ，２２ｂを除去してその
表面側に新しくレジスト膜２２ｃを形成した後、
Ｎ型半導体基板２０の研磨面２４にＰ型半導体基
板２１の研磨面２５を熱圧着させる。 Next, as shown in FIG. 2B, an N-type semiconductor substrate 2
After removing the resist films 22a and 22b on 0 and forming a new resist film 22c on the surface side,
The polished surface 25 of the P-type semiconductor substrate 21 is bonded to the polished surface 24 of the N-type semiconductor substrate 20 by thermocompression.
次に、第２図Ｃに示す如く、一体化したＮ型半
導体基板２０及びＰ型半導体基板２１に熱処理を
施し、アイソレーシヨン層２３と繋がつたアノー
ド・エミツタ層２６を形成する。この時、Ｎ型半
導体基板２０とＰ型半導体基板２１との接合部に
アノード・エミツタ接合２７が形成される。 Next, as shown in FIG. 2C, the integrated N-type semiconductor substrate 20 and P-type semiconductor substrate 21 are subjected to heat treatment to form an anode/emitter layer 26 connected to the isolation layer 23. At this time, an anode-emitter junction 27 is formed at the junction between the N-type semiconductor substrate 20 and the P-type semiconductor substrate 21.
次に、第２図Ｄに示す如く、レジスト膜２２ｃ
に所定のパターニングを施し、これをマスクにし
てＮ型半導体基板２０内にホウ素を導入して表面
濃度が1018cm-2程度の反対導電型不純物領域から
なるベース層２８を形成する。 Next, as shown in FIG. 2D, the resist film 22c
A predetermined pattern is applied to the substrate, and using this as a mask, boron is introduced into the N-type semiconductor substrate 20 to form a base layer 28 consisting of an impurity region of the opposite conductivity type with a surface concentration of about 10 18 cm -2 .
然る後、第２図Ｅに示す如く、ベース層２８内
にリングを導入して表面濃度が1020cm-2程度でＮ
型半導体基板２０と同じ導電型の同導電型不純物
領域からなるエミツタ層２９を形成すると共に、
Ｎ型半導体基板２０内にチヤンネルストツパ３１
を形成する。次に、アノード・エミツタ層２６の
露出面に取出電極３２を形成する。また、Ｎ型半
導体基板２０の主面を保護膜３３で覆つた後、保
護膜３３に形成したコンタクトホールを介してベ
ース層２８、エミツタ層２９に接続する取出電極
３４，３５を形成する。次いで、取出電極３２，
３４，３５に夫々接続するアノードＡ、ゲート
Ｇ、カソードＫを形成してサイリスタ４０を得
る。 Thereafter, as shown in FIG .
While forming an emitter layer 29 made of an impurity region of the same conductivity type as the type semiconductor substrate 20,
A channel stopper 31 is provided in the N-type semiconductor substrate 20.
form. Next, an extraction electrode 32 is formed on the exposed surface of the anode/emitter layer 26. Further, after covering the main surface of the N-type semiconductor substrate 20 with a protective film 33, lead-out electrodes 34 and 35 are formed to be connected to the base layer 28 and the emitter layer 29 through contact holes formed in the protective film 33. Next, the extraction electrode 32,
A thyristor 40 is obtained by forming an anode A, a gate G, and a cathode K connected to 34 and 35, respectively.
このようにこのプレーナ型サイリスタの製造方
法によれば、アノードエミツタ接合２７をＮ型半
導体基板２０とＰ型半導体基板２１との接合によ
つて形成できるので、長時間を必要とする不純物
拡散によるアノードエミツタ接合形成工程を省略
することができる。また、アノードエミツタ接合
２７をＮ型半導体基板２０とＰ型半導体基板２１
との接合によつて形成するので、基板が厚肉にな
つても短い時間でサイリスタを容易に製造するこ
とができる。 As described above, according to the manufacturing method of this planar type thyristor, the anode-emitter junction 27 can be formed by joining the N-type semiconductor substrate 20 and the P-type semiconductor substrate 21. The anode emitter junction formation step can be omitted. Further, the anode emitter junction 27 is connected to the N type semiconductor substrate 20 and the P type semiconductor substrate 21.
Since the thyristor is formed by bonding with the substrate, the thyristor can be easily manufactured in a short time even if the substrate is thick.
以上説明した如く、本発明にかかるプレーナ型
サイリスタの製造方法によれば、写真蝕刻工程及
び拡散工程を省略して簡略化された工程で容易に
プレーナ型サイリスタを得ることができるもので
ある。
As described above, according to the method for manufacturing a planar thyristor according to the present invention, a planar thyristor can be easily obtained through a simplified process by omitting the photolithography process and the diffusion process.
第１図は、本発明方法を工程順に示す説明図、
第２図は、従来のプレーナ型サイリスタの製造方
法を工程順に示す説明図である。
２０……Ｎ型半導体基板、２１……Ｐ型半導体
基板、２２ａ，２２ｂ，２２ｃ……レジスト膜、
２３……アイソレーシヨン層、２４，２５……研
磨面、２６……アノードエミツタ層、２７……ア
ノードエミツタ接合、２８……ベース層、２９…
…エミツタ層、３１……チヤンネルストツパ、３
２，３４，３５……取出電極、３３……保護膜、
４０……サイリスタ。
FIG. 1 is an explanatory diagram showing the method of the present invention in the order of steps;
FIG. 2 is an explanatory diagram showing a conventional method for manufacturing a planar thyristor in order of steps. 20... N-type semiconductor substrate, 21... P-type semiconductor substrate, 22a, 22b, 22c... resist film,
23... Isolation layer, 24, 25... Polished surface, 26... Anode emitter layer, 27... Anode emitter junction, 28... Base layer, 29...
...Emit layer, 31...Channel stopper, 3
2, 34, 35... Takeout electrode, 33... Protective film,
40...Thyristor.
Claims (1)
その表面から裏面に亙つて反対導電型で環状のア
イソレーシヨン層を形成する工程と、該アイソレ
ーシヨン層の露出面を含む研磨面に反対導電型で
鏡面研磨された第２半導体基板の研磨面を接合す
る工程と、前記アイソレーシヨン層で囲まれた前
記第１半導体基板内にその主面から所定の深さで
延出する反対導電型不純物領域を形成する工程
と、該反対導電型不純物領域内に前記第１半導体
基板と同導電型の同導電型不純物領域をその主面
から所定の深さで延出させる工程とを具備するこ
とを特徴とするプレーナ型サイリスタの製造方
法。1. A step of forming an annular isolation layer of an opposite conductivity type from the front surface to the back surface of a mirror-polished first semiconductor substrate of one conductivity type, and forming a ring-shaped isolation layer on the polished surface including the exposed surface of the isolation layer. a step of bonding polished surfaces of a mirror-polished second semiconductor substrate of opposite conductivity type; forming an impurity region of a conductivity type; and extending an impurity region of the same conductivity type as the first semiconductor substrate to a predetermined depth from a main surface thereof in the impurity region of the opposite conductivity type. A method for manufacturing a planar thyristor, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21286A JPS62158364A (en) | 1986-01-07 | 1986-01-07 | Manufacture of planar type thyristor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21286A JPS62158364A (en) | 1986-01-07 | 1986-01-07 | Manufacture of planar type thyristor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62158364A JPS62158364A (en) | 1987-07-14 |
| JPH0548630B2 true JPH0548630B2 (en) | 1993-07-22 |
Family
ID=11467653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21286A Granted JPS62158364A (en) | 1986-01-07 | 1986-01-07 | Manufacture of planar type thyristor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62158364A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5887870A (en) * | 1981-11-20 | 1983-05-25 | Nec Corp | Manufacture of thyristor |
| JPS58186966A (en) * | 1982-04-23 | 1983-11-01 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49136166U (en) * | 1973-03-23 | 1974-11-22 |
-
1986
- 1986-01-07 JP JP21286A patent/JPS62158364A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5887870A (en) * | 1981-11-20 | 1983-05-25 | Nec Corp | Manufacture of thyristor |
| JPS58186966A (en) * | 1982-04-23 | 1983-11-01 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62158364A (en) | 1987-07-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |