JPH0548545A - Pulse code modulation transmitter - Google Patents

Abstract

PURPOSE:To reduce the deterioration in the signal quality by reducing the production of noise in a signal whose level corresponds to a higher level toward high-order bits. CONSTITUTION:When a 7th bit of a transmission signal has a defect, a parity error detection circuit 32 of a receiver side reception section detects a parity error and outputs a parity error check signal 44 at a high frequency of occurrence. Upon the receipt of the check signal 44 for a prescribed time, a control circuit 34 outputs a test execution signal 42 for a prescribed time. A test data generating circuit of a sender side transmission section generates a test data, a test data error check circuit 33 of the receiver side reception section receives the data to check the test data and the result is reported to the control circuit as test data error information 43, and when the defect of the 7th bit is reported, other bits are discriminated to be normal bits and normal bit location information 41 is outputted. A bit replacement circuit 31 allocates normal bits in a transmission data 12 to bits of an output data 45 upon the receipt of the information 41 and sets logical 0 to a bit 0.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse code modulation transmission device.

[0002]

2. Description of the Related Art In a conventional pulse code modulation transmission apparatus, the input data of a transmitting section is transmitted as it is as transmission data, and the receiving section extracts it as output data. The input data is data representing an amplitude value such as voice data, and is coded so as to correspond to a larger amplitude value in higher bits.

[0003]

Since the above-mentioned conventional pulse code modulation transmission apparatus has a structure in which the higher bits are coded so as to correspond to a larger amplitude value and transmitted, a specific bit of a transmission path is When an abnormality occurs in the signal system, there is a drawback that the noise corresponding to a bit corresponding to a large amplitude value causes a large amount of noise and the quality of transmission data deteriorates.

[0004]

A pulse code modulation transmission apparatus according to the present invention is a pulse code modulation transmission apparatus for inputting input data corresponding to a larger amplitude value to higher bits to a transmission section and obtaining output data from a reception section. In the first bit rearrangement, the transmitting unit receives normal bit position information indicating the position of a normal bit on the transmission line from the partner receiving unit, and arranges the bits from the higher order of the input data in the normal bit on the transmission line. Circuit and a test for transmitting data from the first bit rearrangement circuit, and generating predetermined test data when the test execution signal is received from the receiving section to send the transmission data to the transmission path. A data generating circuit; and a parity generating circuit that receives normal bit position information, generates parity for a normal bit of transmission data, and sends the parity bit to the transmission path, The receiving unit performs a reverse conversion of the received transmission data based on the normal bit position information to the first bit rearranging circuit of the partner transmitting unit and outputs the second bit rearranging circuit as output data. A parity error detection circuit that detects a parity error from the normal bit of the transmission data and the received parity bit by the normal bit position information and generates a parity error detection signal; and a parity error detection circuit when the transmission data is input and a test execution signal is received. When a test data error detection circuit that detects an error in test data bit by bit and outputs test data error information, and a parity error detection signal of a predetermined frequency or more is received from the parity error detection circuit in a preset time. The test execution signal is output to the test data error detection circuit and the partner transmission section for a certain period of time, and the test data error during the test period is incorrect. And a control circuit for sending to the second bit reclassification circuit, the parity error detection circuit and the counterpart transmission unit bit position of the transmitted data as a normal bit position information that has not generated an error in the information.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a transmitting unit in one embodiment of the present invention, and FIG. 2 is a block diagram showing a receiving unit in one embodiment of the present invention.

First, the configuration of the transmitting section in this embodiment will be described with reference to FIG.

Input data 11 input to the input terminal 21
Is 8-bit pulse code modulation data and is supplied to the bit rearrangement circuit 1. Further, the bit rearrangement circuit 1 is supplied with the normal bit position information 15 from the signal separation circuit 4. The normal bit position information 15 is the position number of a normal bit among the eight bits transmitting the transmission data 12 on the transmission path.

In this case, the bit position numbers from the most significant bit to the least significant bit of the data are "7, 6, 5, 4, 3, 2, 1, 0". In addition, these bits will be referred to as "bit 7 to bit 0".

The bit rearrangement circuit 1 rearranges the bits of the transmission data 12 by arranging the input data 11 from the most significant bit at a position higher than the normal bit of the transmission data 12. For example, when the normal bits are bits 6, 4, 3, 2, 1, 0, bits 7, 6, 5, 4, 3, 2 of the input data 11 are respectively bits 6, 4, 3, 2, 1 of the transmission data 12. , 0. At this time, bits 1 and 0 of the input data 11 are not arranged. Bits 1 and 0 of the transmission data 12 have arbitrary values.

The output of the bit rearrangement circuit 1 is supplied to the test data generation circuit 2. The test data generating circuit 2 is a circuit for generating test data in order to check the state of each of the 8 bits of the transmission line for transmitting the transmission data 12.

The test data generating circuit 2 normally allows the data output from the bit rearranging circuit 1 to pass through, and the signal separating circuit 4
When the test execution signal 16 is received from, the test data of a predetermined pattern [“55”, “AA” (hexadecimal number display, etc.)] is output. The output of the test data generation circuit 2 is sent to the transmission line as the transmission data 12 and is supplied to the parity generation circuit 3.

Based on the normal bit position information 15 supplied from the signal separation circuit 4, the parity generation circuit 3 generates even or odd parity for only the normal bits of the transmission data 12 and sends the parity bit 13 to the transmission line. To do.

The signal separation circuit 4 is a circuit for separating the control information 14 transmitted from the receiving section into normal bit position information 15 and a test execution signal 16. This separating operation is performed by the identification information added to the bit position information 15 and the test execution signal 16 by the receiving section.

Next, the configuration of the receiving section in this embodiment will be described with reference to FIG.

Transmission data 12 transmitted from the partner transmission unit
Is input to the bit rearrangement circuit 31, the parity error detection circuit 32, and the test data error detection circuit 33.

The bit rearrangement circuit 31 performs an operation reverse to that of the bit rearrangement circuit 1 of the partner transmission section according to the normal bit position information 41 supplied from the control circuit 34, and then outputs the output as output data 45 as an output terminal 51. Output to. That is, the bits from the higher order of the normal bits of the transmission data 12 are arranged from the most significant bit of the output data 45.

The remaining bits of the output data 45 have a value of logic "0". For example, the normal bit is bit 6,
When 4, 3, 2, 1, 0 Bit 6 of transmission data 12
4, 3, 2, 1, 0 are arranged in bits 7, 6, 5, 4, 6, 5, of output data 45, respectively. At this time, bits 1 and 0 of the output data 45 have a value of logic "0".

The parity error detection circuit 32 is a control circuit 34.
Parity error detection is performed on the normal bit of the transmission data 12 and the parity bit 13 based on the normal bit position information 41 supplied from the above, and a parity error detection signal 44 is output to the control circuit 34 when an error is detected.

The test data error detection circuit 33 detects the error of the test data transmitted from the partner transmission section as the transmission data 12 bit by bit in response to the test execution signal 42 supplied from the control circuit 34. This error detection result is reported to the control circuit 34 as the test data error information 43.

The control circuit 34 includes a parity error detection circuit 3
2 receives the parity error detection signal 44, the test data error detection circuit 33 inputs the test data error information 43, and the bit rearrangement circuit 31, the parity error detection circuit 32, and the signal mixing circuit 35 are tested for the normal bit position information 41. The test execution signal 42 is supplied to the data error detection circuit 33 and the signal mixing circuit 35.

The signal mixing circuit 35 adds these pieces of identification information to the normal bit position information 41 and the test execution signal 42 and sends them as control information 14 to the partner transmission section via the transmission line. When the control circuit 34 receives the parity error detection signal 44 for a certain frequency or more in a certain time, it outputs the test execution signal 42 for a certain time, and during the test period, the test data generating circuit 2 of the partner transmitting section and the test data error detecting circuit 33 of the receiving section. The operation of checking the state of each bit of the transmission path is performed by.

Based on the test data error information 43 supplied from the test data error detection circuit 33 during the test period, the control circuit 34 outputs the position number of the bit in which no error has occurred as the normal bit position information 41 after the test is executed. In addition,
The normal bit position information 41 is output even at the start of communication. In this case, all bits are normal bits.

FIG. 3 shows an example of bit rearrangement in the present embodiment shown in FIGS. 1 and 2, (a) showing a case where all bits of the transmission line are normal, and (b) showing bit 7 of the transmission line. Is a diagram showing a case where is abnormal, and (c) is a diagram showing a case where bits 7 and 5 of the transmission path are abnormal.

Next, a specific operation of this embodiment will be described with reference to FIGS. 1, 2 and 3.

FIG. 3A shows the case where all the bits of the transmission line are normal. In this case, the bits are not rearranged, and the input data 11 is sent to the transmission line as the transmission data 12 as it is.

FIG. 3B shows the case where bit 7 of the transmission line is abnormal. As a result of the occurrence of abnormality, the parity error detection circuit 32 detects a parity error in the receiving section, and the parity error detection signal 44 is generated frequently. Output. When the control circuit 34 receives the parity error detection signal 44 for a certain period of time, it outputs the test execution signal 42 for a certain period of time.

As a result, the test data generating circuit 2 of the transmitting section generates the test data, and the test data error detecting circuit 33 of the receiving section checks the received test data.
This result is used as the test data error information 43 by the control circuit 34.
To be reported to. At this time, an abnormality of bit 7 is reported.
Then, the control circuit 34 causes the bits 6, 5, 4, 3, 2,
Normal bit position information 41 is output with 1, 0 as a normal bit. As a result, bits 7 to 1 of the input data 11 are arranged in bits 6 to 0 of the transmission data 12. Further, the operations of the parity generation circuit 3 of the transmission unit and the parity error detection circuit 32 of the reception unit are thereafter performed on bits 6 to 0 of the transmission data 12.

FIG. 3C shows the case where the bit 5 is further abnormal in the case of FIG. 3B and the bits 7 and 5 are abnormal. In this case, bits 7 to 2 of the input data 11 are arranged in bits 6, 4, 3, 2, 1, 0 of the transmission data 12.

[0030]

As described above, according to the present invention, when an abnormality occurs in a specific bit of a transmission line, the bit arrangement of the input data for the transmission data is changed on the transmission line to change the input data to the normal bit. By arranging from the most significant bit, it is possible to reduce the noise generation of the signal corresponding to the larger amplitude value such as the speech signal such as the higher bit and reduce the signal quality inferiority.

[Brief description of drawings]

FIG. 1 is a block diagram showing a transmitting unit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a receiving unit according to an embodiment of the present invention.

FIG. 3 shows an example of bit rearrangement in the present embodiment shown in FIGS. 1 and 2, (a) showing a case where all the bits of the transmission line are normal, and (b) showing that bit 7 of the transmission line is abnormal. And (c) is a diagram showing a case where bits 7 and 5 of the transmission line are abnormal.

[Explanation of symbols]

 1, 31-bit rearrangement circuit 2 Test data generation circuit 3 Parity generation circuit 4 Signal separation circuit 11 Input data 12 Transmission data 13 Parity bit 14 Control information 15, 41 Normal bit position information 16, 42 Test execution signal 21 Input terminal 32 Parity Error detection circuit 33 Test data error detection circuit 34 Control circuit 35 Signal mixing circuit 43 Test data error information 44 Parity error detection signal 45 Output data 51 Output terminal

Claims (2)

[Claims] 1. A pulse code modulation transmission apparatus in which input data corresponding to a larger amplitude value for higher bits is input to a transmission section and output data is obtained from the reception section, wherein the transmission section has a normal bit position of a transmission path. A normal bit position information indicating the normal bit position information from the other receiving unit, and arranging a bit from the higher order of the input data in the normal bit of the transmission path; and usually from the first bit rearranging circuit. Test data generating circuit for transmitting predetermined data and transmitting the transmission data to the transmission line when the test execution signal is received from the receiving section, and the transmission data for receiving the normal bit position information. And a parity generation circuit for generating a parity for the normal bit and transmitting the parity bit to the transmission line. 2. The second bit set, wherein the receiving section performs reverse conversion on the received transmission data based on the normal bit position information to that of the first bit changing circuit of the partner transmitting section and outputs as output data. A replacement circuit, a parity error detection circuit that detects a parity error from the normal bit of the transmission data and the received parity bit based on the normal bit position information, and generates a parity error detection signal; and input the transmission data and receive a test execution signal. When the error occurs in the received test data, the test data error detection circuit that detects the error for each bit and outputs the test data error information, and the parity error detection circuit from the parity error detection circuit detects the parity error more than a predetermined frequency at a preset time. When a signal is received, the test execution signal is output to the test data error detection circuit and the partner transmission section for a certain period of time during the test period. The test data error information is provided with the bit position of the transmission data in which no error has occurred, as the normal bit position information, the second bit rearrangement circuit, the parity error detection circuit, and the control circuit for sending to the partner transmission unit. The pulse code modulation transmission device according to claim 1, wherein