JPH0547914B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a coding system that is less susceptible to the effects of low-frequency damping characteristics caused by a rotary transformer of a digital magnetic recording/reproducing device.

Conventionally, there is a method called 8-10 conversion as a coding method that is less susceptible to the effects of low frequency discontinuation, in which a DC balanced combination of 10-bit code words is matched to an 8-bit code word. However, it had the disadvantage of having a redundancy of 25% (10÷8=1.25) and requiring an extra recording band. In response, a new modulation method called 8-8 mapping has appeared. When digitizing an analog signal using an A/D converter, a pre-filter is used to digitize the analog signal to 1/1 of the sampling frequency.
It takes advantage of the fact that components of 2 or more are removed, and in principle modulates digital data on the baseband by inverting it at a frequency corresponding to 1/2 of the sampling frequency. be.

In this case, the spectrum of the component that was low frequency on the baseband shifts to near the carrier (1/2 of the sampling frequency), and the spectrum of the component that was near the carrier on the baseband shifts to the low frequency. As mentioned above, the carrier component has already been removed by the pre-filter, so the direct current component is small. However, if the prefilter removes the analog signal at a cutoff frequency that is too lower than the carrier frequency, the transmission band cannot be used effectively, so the cutoff frequency of the prefilter is set very close to the carrier frequency. In this case, some low frequency components will remain, but for example, if DC or disconnection is set to 1/280 of the bit frequency, a sine signal with an amplitude of 1 MSB (most significant bit) at a frequency 16% below the carrier will be generated. If you input waves, there will be a sag of up to 70%.

In addition, since the test bit is just a data string, DC balance cannot be achieved even if the above conversion is performed, and if it is recorded as is, a large sag will occur in this part, and the eye opening ratio during playback including the previous and subsequent data will be affected. deteriorate.

One method is to statistically balance the DC by multiplying random numbers only to the test bits, but
Since the inspection bits are placed at random, the effect is not sufficient.

The present invention eliminates the above-mentioned drawbacks, prevents the DC balance from being disturbed even in the parity section, and also suppresses low frequency components caused by imperfection of 8-8 mapping.

Since it is generally convenient to perform data processing in units of 8 bits, it is assumed here that the code word is transmitted in units of 8 bits. In addition, the check bits are 8-bit CRC to detect errors as finely as possible.
(Cyclic redundancy check code) is used.
Assume that 8 check bits are inserted every 100 to 300 bits. In order to achieve almost DC balance within this added check word, a code word consisting of 10 or more bits is created from the original 8 bits, and only those with DC balance are made to correspond to the additional code. It is good to use it as a word.

On the other hand, in 8-8 mapping, low frequency components appear, but the rate of change is at most 20% for 100 bits.
That's about it. For example, if one test word is attached to 16 words, the total will be 136 bits.

Therefore, in the present invention, in addition to the above-mentioned balanced code word, the difference between the code of "1" and the code of "0" (that is, the weight)
Assign unbalanced code words with positive and negative weights of 2 to 4 to test words, and select and add these test words adaptively so as to reduce the low frequency components generated by 8-8 mapping of data. Use it as a code word. In this way, the imbalance caused by 136 bits is only about 27 bits, so the worst-case low frequency component is reduced to 13
% can be improved. Furthermore, in general 8-8 mapped data, the DC component is about 10%, so the DC component can be improved by about 30%.

If this is insufficient, you can use 12 bits instead of 8 bits. This allows 6 bits to 8
It is possible to improve the bit rate and to have more fine control.

FIG. 1 shows an embodiment of an encoder for realizing the method of the present invention, in which an input image signal 1 is filtered by a pre-filter 2 to remove frequency components of 1/2 or more of the sampling frequency, and an A/D The converter 3 converts the data into digital data. Next, an 8-8 mapping converter 4 converts the data into a data string 5 with approximately DC balance. Next, the data is delayed on the one hand by the delay time associated with this processing in a delay memory to match the timing, and on the other hand, the encoder 7 generates check bits 8.

At the same time, an arithmetic unit 9 that calculates DSV (charge accumulation value) outputs a control signal 10 indicating which direction and how much the DC component has shifted. 8-10 converter 1
1 outputs a 10-bit data output 12 adaptively to the input 8 by means of a control signal 10. If this continues, the data rate will increase where the parity bits are continuous, so the buffer memory 13 is used to adjust the time axis.

Similarly, the data 15 delayed in the memory 6 is connected to the image data part and the inspection bit part by the serial/parallel converter 16, and simultaneously converted into serial data 17 and outputted to the recording amplifier. Needless to say, the DC component (low frequency component) of this signal is suppressed.

Next, playback will be explained. FIG. 2 shows an embodiment of a decoder for recording a code obtained according to the present invention on a recording medium and decoding a signal reproduced from the code. The reproduced signal 18 is converted into parallel data 20 by a shift register 19, and a synchronization signal 22 is generated by a synchronization detector 21, thereby generating a ring counter 23.
is reset, the clock 24 is counted down to 1/8, and a four-phase clock 25 is output.

On the other hand, the counter 26 similarly counts one synchronization period as a cycle to generate the ROM address 27.

The ROM 28 contains four phase selection data 29 from the address 27 and a one-clock inhibit to prevent the phase from jumping when the clock sequentially switches from one phase to four phases and returns from four phases to one phase again. A flag 30 is output, a selected clock 32 is generated by a clock selector 31, and the selected clock 32 is inputted to a latch 33. The serial output 34 of the shift register 19 is converted into 10-bit parallel data 36 by the shift register 35 and latched in parallel by the latch 33. The latched data 37 is converted into original image data 39 by an 8-8 mapping inverse transformer 38, and at the same time, converted into check bits 8 by a 10-8 converter 40, and integrated by a selector 41.

After this, error detection and correction will be performed, but their explanation will be omitted.

As explained above, according to the present invention, the DC balance of the test bits and the
The imperfections of the DC component suppression method can be removed by using statistical properties of data such as -8 mapping. Furthermore, the hardware required for this is relatively simple.

Here, we have described the case where 8-10 block transformation is performed on the inspection points, but in the range of m<n, m,
n is free.

Furthermore, it goes without saying that the same code may be mixed in other than the test points to further improve the low frequency range.

Furthermore, since this redundancy is not sufficient in areas where inspection points are concentrated, processing may be performed so that the inspection points are dispersed in the image data at an average point.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of an encoder according to an embodiment of the present invention, and FIG. 2 is a diagram showing the configuration of an embodiment of a decoder for decoding codes obtained according to the present invention. 1: input image signal, 3: A/D converter, 4: 8
-8 mapping converter, 6: memory, 7: encoder, 9: arithmetic unit, 11: 8-10 converter, 13: buffer memory, 16: serial-parallel converter.

Claims (1)

[Claims] 1 Analog signals are sequentially sampled and converted into a digital signal string of a predetermined word length, and the DC component is converted by code conversion, which includes inverse modulation at a frequency corresponding to an integer fraction of the sampling frequency of the digital signal string. Compression is performed to create a data code string for recording, additional code words containing check bits for error checking are added to each code word of the data code string to form a data block, and the data block is A coding method for recording and reproducing data on a recording medium by sequential serial access, comprising means for detecting a DC component remaining in the data code word string, and the additional code word includes at least a balanced code word and a positive/negative weight. A coding system characterized in that a codeword containing an unbalanced codeword and having a weight that reduces a detected DC component is adaptively selected and added to the data codeword string to form the data block.