KR950011290B1 - Address generating circuit - Google Patents

Abstract

The circuit improves a space efficiency of integrated circuit ; CD-ROM memory, speeds up an operation time without a feedback loop hardware, and easily applies to a double velocity playback mode. The method includes a 1st counting means which counts an encoder in a P/Q modulation, a 2nd counting means which counts a reference symbol position of Q encoder, a 3rd counting means which outputs a relative symbol position, a 1st selection means which selects a counting means, a 2nd selection means which outputs a 2nd counting means output, a 1st addition means which adds output between a 1st selection means and a 2nd selection means, a symbol position generation means which has a compensation means, a shifting addition means which generates two relative addresses, and a modulation address conversion means which has a 2nd addition means.

Description

Address generator

1 is a block diagram of a CD-ROM playback system.

2 is a configuration diagram of data written to the buffer RAM shown in FIG.

3 is a diagram showing a relation between a symbol of an error correction code and a RAM address.

4 to 6 show symbol positions constituting an error correction code.

7 is a block diagram of an address generating circuit.

8 is a block diagram of symbol position generating means.

9 is a circuit diagram according to an embodiment of a codeword counter.

10 is a circuit diagram according to one embodiment of a step-counter.

11 is a circuit diagram according to one embodiment of a 44-counter.

12 is a circuit diagram according to an embodiment of the detecting means.

13 is a block diagram of a modulo correction means.

14 is a circuit diagram according to an embodiment of the comparison means.

15 is a circuit diagram according to an embodiment of a subtraction means.

16 is a block diagram of decoding address conversion means.

17 is a waveform diagram of each part.

The present invention relates to an address generating circuit, and more particularly, to an address generating circuit for generating an address for each symbol during error correction decoding.

In order to correct an error of data recorded on a CD-ROM, buffering of one or more blocks of data recorded in a buffer RAM is required, and address generation according to a predetermined rule is required to decode the buffered data.

Conventional techniques for achieving such functions include a method of generating an address in software using a microcomputer and a table look-up system using a large ROM according to USP 4,715,036. And SANYO patents according to USP 4,901,318. Here, the software method using the microcomputer is theoretically possible, but it is practically impossible because the decoding for error correction must be performed at a very high speed, and the table look-up system requires a large amount of ROM, There is a problem that is too large. In addition, SANYO's patent is implemented with simple hardware for miniaturizing and integrating the address generation circuit. However, due to the feedback loop characteristic of the circuit, that is, the previous address must be calculated in order to calculate the next address. There is a problem that the application according to the system requiring the operation becomes difficult.

It is therefore an object of the present invention to provide an address generator circuit that can accommodate a demand for speedup without using such a feedback loop.

In order to achieve the above object, the address generating circuit of the present invention is a symbol position generating means for generating a symbol position and a decoding address for converting the symbol position into a RAM address, in order to decode symbol data encoded with a P / Q additional Reed Solomon code. An address generating circuit having a converting means, the means for generating a thimble position comprising: first counting means for counting a codeword during P / Q decoding; Second counting means for outputting the relative symbol position of the P codeword determined by the first counting means at P decoding, and outputting the basic symbol position of the Q codeword at Q decoding; Third counting means for outputting a relative symbol position of a Q coder during Q decoding; A first selecting means for selecting a signal of the first counting means for performing P decoding and for generating a symbol position for the parity symbol during Q decoding; otherwise, selecting the signal of the first counting means; ; Second selecting means for selecting predetermined relative symbol positions for each parity symbol when generating symbol positions for parity symbols during Q decoding, and otherwise selecting an output of the second counting means; First adding means for adding outputs of said first selecting means and second selecting means; And a modulo correction means for modulating the output of the first adding means to modulate the maximum symbol position of the information symbol among the Q codewords when generating symbol positions for the information symbols of the Q code. It is done.

Next, the present invention will be described in more detail with reference to the accompanying drawings.

An address generation circuit for the P / Q additional Reed-Solomon code used in the CD-ROM as an example of the error correction code will be described.

First, FIG. 1 is a block diagram of a CD-ROM reproducing system, which comprises a disc 101, a CDP signal processing unit 102, a CD-ROM digital signal processing unit 103, and a host computer 104. The digital signal processing unit 103 uses a synchronization signal detection / descramble circuit 105, a decoding circuit 106, a data transfer unit 107, a buffer RAM 108, and an address generation circuit 109 to the host. It is configured to include.

1 shows a system in which a CD-ROM is used as a computer storage medium. The CDP signal processing unit 102 performs a function performed by a signal processing unit of a general compact disc player. See USP 4,901,318 for more details on this. The CD-ROM digital signal processing unit performs signal processing according to the municipal CD-ROM data standard, that is, error correction for the P / Q additional Reed Solomon code. Here, the data processed by the CDP signal processor 102 are sequentially written to the buffer RAM 108 through the synchronization signal detection / descramble circuit 105, and corresponding symbols are decoded by the decoding circuit 106 for decoding. The address of the stored buffer RAM 108 must be generated. The block which performs such a function is the address generating circuit 109 and the decoded data is transmitted to the host computer through the data transmission unit 107 to the host.

FIG. 2 is a diagram showing the configuration of data written to the buffer RAM 108 shown in FIG. 1. As described above, the buffer RAM 108 may store at least one block of data. Should be The block in the case of a CD-ROM is shown in FIG.

In Fig. 2, the data structure of an arbitrary block will be explained. First, the block synchronization signal is composed of 12 bytes, 2064 bytes of information data, 172 bytes of P parity according to P code, and 104 bytes of Q parity according to Q code. Here, the block synchronization signal plays a role of distinguishing blocks.

3 is a diagram illustrating a relationship between a symbol of an error correction code and a RAM address, wherein a signal applied from the CDP signal processing unit 102 through the synchronous signal detection / descramble circuit 105 is sequentially stored in the buffer RAM. The symbol, which is a basic unit constituting the codeword, is composed of 1 byte. Of the 2352 bytes of 1 block data, 2340 bytes excluding 12 bytes of the block synchronization signal constitute data for decoding of one block. In this case, the data is divided into LSB (Least Significant Bits) and MSB (Most Significant Bits) by 8 bits, that is, 1 byte, so that two planes are formed and decoding is performed for each plane. Therefore, after obtaining the symbol position, it should be converted into the address of the buffer RAM 108. In addition, when the P parity and the Q parity shown in FIG. 2 become 86 symbols and 52 symbols, respectively, the information symbol becomes 1032 symbols.

4 to 6 are diagrams showing symbol positions constituting an error correction code.

4 shows the configuration of symbols according to the P / Q additional Reed Solomon code. Referring to FIG. 4, the encoding process will be described. First, data to be encoded is written in a predetermined memory space according to a symbol position of 0000-1031. Then, as shown in the figure, 24 symbols are selected in the vertical direction, one for every 43 symbols in the horizontal direction, to perform encoding according to the (26, 24) RS code, and 2 × 43 P parity symbols generated according to the symbol Write at positions 1032, 1075-1074, 1117. When encoding according to the P code is completed, encoding according to the Q code is performed using the result as an information symbol. During Q encoding, 43 symbols are selected in diagonal direction, one for every 26 symbols in the vertical direction, to perform coding according to the (45, 43) RS code, and 2 × 26 Q parity symbols generated according to the symbol position (1118). , 1144)-(1143, 1169).

5 shows symbol positions of symbols constituting the P codeword, and FIG. 6 shows symbol positions of symbols constituting the Q codeword N _p and N _q are P codewords and Q code indexes, and M _p and M _q represents a symbol index in one codeword. That is, the symbol position of the 3rd codeword (N _p = 2) and the 4th symbol (Mp = 3) in the _P codeword is 0131, and the 44th ( _Mq = 23) 44th code in the Q codeword (M _q = 43) The symbol position of the symbol is 1141.

Here, symbol positional relational expressions and address translational expressions for decoding codewords having the above characteristics are shown below.

Q decoding;

N _q = 0, 1, 2,... 25

N _q = 0, 1, 2,... 44

Symbol position SL = (43 × N _q + 44 × M _q ) mod 1118; Mq = 0, 1, 2,... , 42... … (One)

= 1118 + N _q ; M _q = 43... … … … … … … … … … … … … … … … … (2)

= 1144 + N _q ; M _q = 44... … … … … … … … … … … … … … … … … (3)

* P decoding;

N _p = 0, 1, 2,... 42

M _p = 0, 1, 2,... 25

Symbol position SL = N _p +43 x M _p ... … … … … … … … … … … … … … … … … … (4)

Address conversion formula;

Address (RA) = … … … … … … … (5)

That is, in Q decoding, there is a difference between a method of generating a symbol position for an information symbol and a method for generating a symbol position for a Q parity symbol. In addition, when generating a symbol position for an information symbol during Q decoding, it can be seen that a modulo operation on 1118, which is the maximum symbol position that an information symbol can have, should be performed.

The address of the buffer RAM 108 corresponding to the symbol position obtained as described above is two, and each of them becomes an address corresponding to the MSB plan and the LSB plan. At this time, BHP (pointer indicating the first memory space where data is stored) is added to convert the address to the actual address on RAM.

7 is a block diagram of an address generating circuit, which comprises a symbol position generating means 701 and a decoding address converting means 702. As shown in FIG. The symbol position generating means 701 inputs the CP-CK which is the clock divided by the number of symbol clocks constituting the symbol clock and the P code and the CQ-CK which is the clock divided by the number of symbol clocks constituting the Q code. A symbol position is generated according to equations (1), (2), (3), and (4), and the decoding address converting means 702 stores the symbol position according to equation (5). RAM 108 to the address of the address. For convenience of explanation, the terms are used as follows. When one codeword consists of a plurality of symbols, the symbol position corresponding to the first symbol is called the basic symbol position of the codeword, and the relative symbol position is subtracted from the symbol position corresponding to the second or more symbols of the codeword. Let's do it.

8 is a block diagram of a symbol position generating means, comprising: a first counting means 814, a second clock selector 806, comprising a first clock selector 801 and a codeword counter 802; A second counting means 815 consisting of a counter 807, a third counting means which is a 44-counter 804, a detector 805, and OR-gates 808 and 809 for generating selection signals. ), An adding means 811, a first selecting means 803, a second selecting means 810, a modulo correction means 812, and the like.

In FIG. 8, the first counting means 814 counts codewords when decoding P / Q. The first-clock selector 801 constituting the first coder 814 has a first code indicating a P codeword and a Q codeword unit. Inputs the clock (CP-CK) and the second coder clock (CQ-CK) signals to select CP-CK for P decoding and CQ-CK for Q decoding, and outputs a codeword counter (802). ) Increases the output signal of the first-clock selector 801 by one step to output a codeword index. The output of the codeword counter 802 is used as a codeword index when generating a symbol position for a parity symbol during Q decoding, and is used as a basic symbol position for a P codeword when decoding.

The second counting means 815 outputs the relative symbol position of the P codeword determined by the first counting means 814 when P decoding, and outputs the basic symbol position of the Q codeword when Q decoding. Do it. The second clock selector constituting the second counting means 815 selects one of a P symbol clock (SP-CK) and a second code clock (CQ-CK) representing a symbol of the P code, and performs Q decoding. When the second coder clock (CQ-CK) is selected, the P-signal clock (SP-CK) is selected and applied to the 43-counter (807). The 43-counter 807 outputs 0, 43, 86, 129, 172, 215, 258,... , 1075, 0, 43,... And the like, and up-counting by 43 whenever a pulse is applied from the second clock selector. In Q decoding, the basic symbol position of the Q codeword is output. In P decoding, the relative symbol position of the P codeword is output. The third counting means, the 44-step counter 804 operates only during Q decoding. When the pulse of the Q symbol clock (SQ-CK) is applied, up-counting is performed by 44 and simultaneously calculated by 1118 module. Do this. Here, 1118 indicates the number of information symbols in the Q code, P symbol is composed of information symbol (1032 symbols) + P parity symbol (86 symbols), Q symbol is information symbol (1118 symbols) + Q parity symbol (52 symbols It consists of That is, the P code is treated as an information symbol in the Q code. Therefore, the step-counter 804 performs a modulo operation, which is a function for calculating the remainder when the number of symbols constituting the P code is greater than or equal to 0, 44, 88,... , 1100, 26, 70, 114,... , 730, 774, 818, 0, 44,... It will cycle as

The detector 805 detects when the output of the 44-counter 804 becomes an output form corresponding to the Q parity symbol of the Q code, that is, 774 and 818. The OR-gate 808 generates a selection control signal for distinguishing between the case corresponding to the Q parity symbol during P decoding and the Q decoding, and outputs it to the first selecting means 803. That is, the output of the detector 805 and the PE signal that is enabled during P decoding are input and logically applied to the first selection means 803 as a selection control signal. The first selection means 803 to which the selection control signal is applied inputs the output of the codeword counter 802 to the I ₀ terminal and the output of the step 44 counter 804 to the I ₁ terminal. When the selection control signal is "1", the signal of I ₀ terminal is selected. When the selection control signal is "0", the signal of I ₁ terminal is selected. When P decoding, the basic symbol position is output. In this case, the relative symbol position is output. In the case of a Q parity symbol, a codeword index is output.

The OR-gate 809 logically sums the output of the detector 805 and outputs the same to the second selecting means 810. The selection control signal of the second selecting means 810 is connected to the OR-gate 809. An output signal S ₁ and a signal S ₀ for detecting the case of 818 among the outputs of the detector 805, and output of the second selection means 810 according to each selection control signal S ₁ , S ₀ . Is shown in the following Table-1.

Table-1

Accordingly, the second selecting means 810 selects the output of the step 43 counter 807 when the Q parity symbol is not the Q parity and applies it to the I ₂ terminal at the first of the Q parity symbols of the Q code. Select the 1118 value, which is the default symbol position, and in the second, select the 1144 value, which is the basic symbol position applied to the I ₃ terminal, and output it.

The adder 811 performs a function of outputting a symbol position by adding outputs of the first selecting means 803 and the second selecting means 810, where modulo operation is performed only in the case of an information symbol in a Q code. Correction is necessary. That is, in the case of the information symbol of the Q code, the basic symbol position is output from the second selecting means 810 and the relative symbol position is output from the first selecting means 803. For example, in the case of Q decoding, a case of the 26th codeword (N _q = 25) and the 20th symbol (M _q = 19) will be described. The relative symbol position 880 is outputted from the selection means 803, which is 1955. However, the symbol position to be output should be 1955 mod 1118 = 827, so correct it. The modulo correction means 812 performs this function.

9 is a circuit diagram according to an embodiment of the codeword counter 802, which is composed of six D-flip flops. This is an up-counter that is incremented by one, and the clock terminal is supplied with the output of the first-clock selector 801 and the reset terminal of each of the six D-flop flops is started with P decoding and Q decoding. Allow the signal RB to be disabled at. In this case, when the signal applied to the reset terminal is " low " enable and the P decoding and the Q decoding are started, the RB signal maintains the " high " level.

FIG. 10 is a circuit diagram according to an embodiment of the step-counter 807, which includes 11 D-flip flops, 5 selectors (MUXs), and a plurality of logic gates. Is enabled and the selector selects the signals applied to the input terminals A and B when the signals applied to S _A and S _B are "high", respectively. In addition, the output of the second clock selector is applied to the clock terminal of each D-flop flop, and the P decoding and Q decoding same as those applied to the reset terminal of the first counting means 814 of FIG. Apply a signal RB that is disabled at the start of. The step 43 counter 807 configured as described above is incremented by 43 each time a pulse is applied to the clock terminal.

FIG. 11 is a circuit diagram according to an embodiment of the 44-step counter 804 which is the third counting means. The 43-step counter includes 11 D-flip flops, 5 selectors (MUX), and a plurality of logic gate combinations. As in 807, the reset terminal of each D flip-flop is enabled when " low ". That is, when the operation is "high", the operation is performed so that the RB signal applied to the codeword counter 802 or the step 43 counter RB is applied to the reset terminal. In addition, a Q symbol clock (SQ-CK) in which pulses are generated for each symbol of the Q code is applied to each clock terminal so that the output increases by 44 steps for each symbol and is simultaneously calculated by the 1118 module.

FIG. 12 is a circuit diagram of the detector 805, which is composed of a combination of a plurality of logic gates, and D1 becomes a "high" level when the output of the 44-step counter 804 is 774, and D2 is a 44-step 804 counter. If the output of 818 is "high" level.

FIG. 13 is a block diagram of a modulo correction means including a subtraction means, a comparator and a third selector.

In Fig. 13, the subtracting means subtracts the maximum symbol position of the P codeword from the output of the adder 811. Figs. The comparator compares the output of the adder 811 with the maximum symbol position of the P codeword. In other words, 1118 is subtracted from the output of the adder 811.

The comparator 1304, the OR-gate 1305 and the inverter 1306 become means 1303 for generating a selection control signal for application to the third selection means. The comparator compares the maximum symbol position of the information symbol during Q decoding from the adder 811, and the OR-gate 1305 is used when the output of the adder 811 is less than 1118 or Q parity symbol during Q decoding. Outputs the enabled signal and inverter 1306 inverts the output of OR-gate 1305. The comparator 1304 is designed to be " low " when the output of the adder 811 is 1118 or more, and " high "

Since the output of the comparator 1304 is always " high " at the time of P decoding, the third selecting means 1301 is " high " applied to S _A of the selection control terminals, and the output of the adder 811 is selected accordingly. In the case of Q parity symbols during Q decoding, the output of the OR-gate 1305 becomes "high", so that the output of the adder 811 is selected. On the other hand, in the case of the information symbol during Q decoding, the adder 811 is selected or the output of the subtracting means 1302 is selected according to the output of the comparator. That is, the third selecting means 1301 selects the output of the subtracting means when the symbol position for the information symbol during Q decoding is larger than the maximum symbol position of the P codeword, and otherwise outputs the first adding means. Will be selected.

FIG. 14 is a circuit diagram of the comparison unit, which is composed of a combination of logic gates, and compares an input of 11 bits excluding LSB 1 bit of the output of the adder 811 with 1118 = (10001011110) ₂ .

FIG. 15 is a circuit diagram of a subtracting means consisting of a combination of logic gates including three 2: 1 selectors, subtracting 1118 = (10001011110) ₂ from an 11-bit input excluding the MSB 1 bit of the output of the adder 811. It plays a role. 1118 = (10001011110) ₂ denotes the number of symbols constituting the P code in one block.

Fig. 16 is a block diagram of the decoding address converting means, which comprises a shifting adding means 1601 and an adder 1602.

In FIG. 16, the shifting adding means 1601 inputs an 11-bit symbol position output from the third selecting means 1301, shifts it one bit higher, and then puts "0" and "1" in the least significant bit, respectively. Write two to output two relative addresses for one symbol position. The adder 1602 adds BHP, which is the first RAM address value in which data to be decoded in the block is stored, and outputs an address RA in the buffer RAM. That is, it performs a function of adding BHP to the output of the shifting adding means 1601.

FIG. 17 is a waveform diagram of input and output signals and symbol positions SL shown in FIG. 7 divided into Q decoding and P decoding. As described above, the RBs are converted from the reset-enable state to the reset-disable state at the start of each correction section (at the time of P decoding or Q decoding). CP-CK and CQ-CK are codeword clocks used for P decoding and Q decoding, respectively. In each decoding section, the correction section reads one codeword and generates a syndrome to generate error data. The interval for determining whether there is no error and performing the correction is indicated. Only after the correction period is completed will the next codeword be read and the above process repeated.

As described above, since the present invention does not use a large-capacity ROM, the area efficiency is high when the integrated circuit is implemented, and since the operation is performed only by the hardware excluding the feedback loop, the speed is very fast, and at the same time, it is easily applied to the double speed playback mode. Will be.

Claims (6)

An address generating circuit for decoding symbol data encoded with a P / Q additional Reed Solomon code, comprising: first counting means for counting codewords during P / Q decoding, and determined by the first counting means for P decoding; A second counting means for outputting the relative symbol position of the P code to be output, and at the time of Q decoding, the second counting means for outputting the basic symbol position of the Q code, and a third counting means for outputting the relative symbol position of the Q coder for Q decoding; First selection means for selecting a signal of the first counting means for decoding and for generating a symbol position for the parity symbol during Q decoding; otherwise, Q for selecting a signal of the third counting means; If the symbol positions for the parity symbols are to be generated during decoding, predetermined relative symbol positions for each parity symbol are selected. Otherwise, the output of the second counting means is determined. Selecting second selecting means, first adding means for adding outputs of the first selecting means and second selecting means, and outputting of the first adding means when generating symbol positions for information symbols of Q code. Symbol position generating means comprising a modulo correction means for performing a modulo calculation on the maximum symbol position of the information symbol in the Q code; And when the decoding address is N bits, a signal of N-1 bits is input from the symbol position generating means, which is the upper bit and the least significant bit is 0/1, respectively, to output two relative addresses for one symbol position. A shifting address converting means comprising shifting addition means for generating a second adding means for adding a BHP, which is a first RAM address value of data to be decoded in a block, to convert the relative address into an absolute address. The method of claim 1, wherein the first counting means counts the P-coded clock (CP-CK) at P decoding and counts the Q-coded clock (CQ-CK) at Q code. Address generating circuit. The method of claim 1, wherein the second counting means has a coefficient of ascending step by step according to the P symbol clock during P decoding, and at the same time, the second counting means is calculated as a module with respect to the maximum symbol position included in the P codeword. An address generation circuit, characterized in that it is modulated by the maximum symbol position with respect to the maximum symbol position included in the P code at the same time in accordance with the code clock (CQ-CK). 2. The apparatus of claim 1, wherein the modulo correction means is configured to subtract the maximum symbol position of the P code from the output of the first adding means, and compares the output of the first addition means and the maximum symbol position of the P code. A third selecting means for selecting the output of the subtracting means if the symbol position for the information symbol during Q decoding is larger than the maximum symbol position possessed by the P code; otherwise, selecting the output of the first adding means. And an address generating circuit comprising: 2. The symbol position generating means according to claim 1, wherein the symbol position generating means includes a detector for detecting a predetermined bit pattern indicating that an output of the second selecting means is intended to generate a symbol position for a parity symbol of a Q code. Address generating circuit. The address generating circuit according to claim 1, wherein the third counting means is incrementally counted by a predetermined step according to the symbol clock during Q decoding, and simultaneously calculated as a module with respect to the tooth symbol position included in the P code.