JPH0547622A - Large scale integrated circuit - Google Patents

Abstract

PURPOSE:To produce a large-chip-scale integrated circuit available for a memory or the like with almost equal masks in number to that of subchips, by classifying a large chip into a plurality of subchips that is small enough to be exposed with one mask, and using a common mask to the subchips in almost all steps. CONSTITUTION:For instance, a large scale chip 10 measures W1 by h1, and is too large to be exposed with one mask when a conventional exposure apparatus is used. The chip 10 is classified into three regions a1, b1, and b2, and the regions a1 and b1 are assumed to have an equal or almost equal pattern and the region b2 has a quite different pattern from these two patterns. Then, the regions a1 and b1 are grouped into one subchip B, and the regions b2 and a20 into one subchip A. The region a20 is not essentially necessary, but is added in order to make the shapes of chips A and B in common. A common pattern is used for both the chips A and B in almost all steps from the beginning, and a differentmask is only used for last few wiring-system steps.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern design of a large scale integrated circuit having a large chip size.

[0002]

2. Description of the Related Art The degree of integration of large-scale integrated circuits is increasing year by year. Taking dynamic memory (DRAM) as an example,
In almost three years, high integration has been achieved at a rate of 4 times. The microfabrication technology progresses with each generation, and the occupied area of the memory cell is reduced to about 1/2 to 1/3, but the degree of integration is quadrupled, so the chip area is increased. For example, the chip area of 16 Mbits is about 150 mm ² , 64 Mbits is about 200 m
m ² and the future 256 Mbit is 300 to 350 m
expected to increase to m ² . On the other hand, a reduction projection exposure apparatus is used in the photolithography process of transferring a pattern onto a wafer, but there is a limit to the chip size that can be exposed with one mask due to the restriction of the lens aperture. For example, the chip size that can be exposed by the current 5: 1 reduction projection exposure apparatus is limited to about 20 mm × 20 mm, and the future 256
It is not possible to expose a large area chip of Mb or more with one mask.

In order to manufacture a chip larger than 20 mm × 20 mm, it is necessary to divide one chip into smaller sub chips and prepare a mask for each sub chip. A conventional mask division method will be described with reference to FIGS. Figure 2 shows a large chip dynamic memory (DR
It is a chip top view of AM) 10. MS as described below
A is a memory cell, a sense amplifier, and a precharge circuit 1
It is a group. The peripheral circuit includes an address buffer, a decoder, a word driver, a main amplifier, an output circuit and a control circuit. It is assumed that the width w1 of the ten chip dimensions w1xh1 is larger than 20 mm. In order to fabricate this with a conventional exposure apparatus, as shown in FIG. 3, the mask is simply fabricated by dividing the chip 10 into two sub-chips A and B at the central portion. The long dimension of the sub chip (the larger w1 / 2 or h1) is smaller than 20 mm. The wiring over both sub-chips allows the patterns of the two masks to overlap slightly to ensure reliable connection. However, in this method, the two masks are obviously different in the shape of the pattern, so that it is necessary to make two sets of masks for all the steps. However, recent highly integrated DR
The number of masks used in all steps of AM is more than 30, and
Furthermore, if two sets of these are prepared, the mask manufacturing cost will be doubled and the mask will be replaced twice in each exposure step, increasing the number of steps and making it difficult to apply to mass production of wafers.

[0004]

SUMMARY OF THE INVENTION According to the present invention, a large-scale integrated circuit having a large chip size that cannot be exposed with one mask is provided.
This is for easily manufacturing with the same number of masks as the number of integrated circuits having a small chip size that can be exposed by the mask. The method proposed below is particularly effective when applied to a chip having a high pattern regularity such as a memory or a gate array.

[0005]

The present invention specifically devises a method of dividing a large chip that cannot be exposed by one mask into a plurality of sub chips that can be exposed by one mask, and most of the steps are performed between the plurality of sub chips. A common mask can be used, and only masks for a small number of steps are separately prepared for the sub chips.

[0006]

As described above, a large-scale integrated circuit having a large chip size can be manufactured with high precision and at a relatively low cost by using the conventional exposure apparatus and almost the same number of masks as the conventional one.

[0007]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 1 shows a basic first embodiment of the present invention, which is manufactured by using a sub-chip mask obtained by dividing a large-sized chip into two parts. The large-sized chip 10 has a chip size w1 × h1, and is set to a size that cannot be exposed by a single mask in the present exposure apparatus. First, 10 is the area a
Divide into 1, b1, and b2. The patterns a1 and b1 are completely the same or almost the same. b2 is a pattern that is significantly different from a1 and b1. b1 and b2 are combined to form a sub chip B. Subchip A with a1 and a20 combined
And Although a20 is an originally unnecessary circuit area outside the chip, it is added to A in order to make the masks of A and B as common as possible. The dimensions of a1 and b1 + b2 are w
Different from 2xh1 and w3xh1. Where w1 = w2 + w
3, w2 <w3. The dimensions of the divided sub-chips A and B are both w3 × h1, which is within the range that can be exposed with high precision by the existing exposure apparatus. In most of the first steps, a mask common to A and B is used. Different masks are used for A and B only for the partial mask of the last wiring system. Therefore, the diffusion layer patterns of a1 and b1, and a20 and b2 are equal. The wiring layer patterns of a20 and b2 are different. Double the number of chips per wafer, w3xh
Sub-chip exposure is repeated at a pitch of 1. In this way, even a large chip can be manufactured using an existing exposure apparatus with a mask number almost equal to that of a small chip. By the way a2
A portion corresponding to 0 can be formed as a boundary with an adjacent chip. Although this is an ineffective region which is unnecessary for the circuit operation of the chip, it is considered that this area ratio on the wafer is small. However, this area is used as a scribe area for chip cutting.

FIG. 4 shows a second basic embodiment of the present invention, in which a large-sized chip is also manufactured using a sub-chip mask which is also divided into two parts. The large-sized chip 10 has a chip size w1 × h1 and is so large that one mask cannot expose it. The chip 10 in the areas a1, a3,
Divide into b1 and b2. a1 and b1 are exactly the same,
The patterns are almost the same. The patterns a3 and b2 are significantly different from the patterns a1 and b1. Sub-chip A is a1, a3
And an invalid area a20. Sub chip B is b1, b2
And an invalid area b30. Here, a20 and b30 are originally unnecessary areas outside the chip, but are added because A and B have the same size w4xh1. The feature of this embodiment is shown in FIG.
Different from the invalid area in addition to the left side a20 of the sub chip A,
This is also on the right side b30 of the sub chip B. a1 +
The dimensions of a3 and b1 + b2 are w2xh1 and w3x, respectively.
Different from h1. Here, w1 = w2 + w3 and w2 <w3. The dimensions of the divided sub chips A and B are both w4.
xh1 is a size within a range that can be exposed with high precision by the existing exposure apparatus. In most of the first steps, a mask common to A and B is used. Different masks are used for A and B only for the partial mask of the last wiring system. Therefore, a1 and b
1, a20 and b2, a3 and b30 have the same diffusion layer pattern. The wiring layer patterns of a20 and b2 and a3 and b30 are different. Sub-chip exposure is repeated four times as many times as the number of chips per wafer at a pitch of w4 × h1. In this way, even a large chip can be manufactured using an existing exposure apparatus with a mask number almost equal to that of a small chip. A region where a20 and b30 are combined can be a boundary with an adjacent chip. Although this is an ineffective region which is unnecessary for the circuit operation of the chip, it is considered that this area ratio on the wafer is small. However, this area is used as a scribe area for chip cutting. The difference between FIG. 4 and FIG. 1 is due to the difference in the dividing positions of the sub chips A and B. 1 corresponds to dividing at the boundary between the peripheral circuit and the MSA in FIG. 2, and FIG. 4 corresponds to dividing in the peripheral circuit in FIG. The size of the invalid area is almost the same in FIGS. 1 and 4. However, it can be said that the method of FIG. 4 in which the peripheral circuit having a relatively coarse pattern and a large number of divisions is used is more practical. FIG. 5 shows a basic third embodiment of the present invention, in which a large-sized chip is made with a mask divided into four parts. The chip size of the chip 10 is w1 × h1, and both w1 and h1 exceed 20 mm. Unlike FIG. 1, the large-sized chip 10 is vertically divided into two and horizontally divided into two, that is, a total of four. The divided four areas are a1, b1 + b2, c1 + c4, d1 + d2 + d4 +.
It is d5. W2xh2, w3xh2, w2x respectively
The dimensions are h3 and w3xh3. Where w1 = w2 + w
3, h1 = h2 + h3, w2 <w3, h2 <h3. Since most of the above four areas are made with the same mask,
Sub-chips A, B, and C whose dimensions are matched to the largest D (≡d1 + d2 + d4 + d5) in the four regions are formed. The sub chip A includes a1 and invalid areas a20, a40, and a50. The sub chip B has b1 and b2 and invalid areas b40 and b5.
It consists of zero. Sub-chip C has c1 and c4 and invalid area c2
It consists of 0 and c50. Sub chips D are d1, d2, d
4 and d5, there is no invalid area. Where a2
0, a40, a50, b40, b50, c20, c50
Is an unnecessary area outside the chip, but A, B, and C are D
Is added so that the dimension is equal to w3xh3. These sub-chips have a size within a range in which exposure can be performed with high precision using an existing exposure apparatus. Repetition pitch during reduction projection exposure is w
3xh3, repeat exposure 4 times as many as the number of chips 1
The resist for the wafer is exposed. Similarly to FIG. 1, in the first diffusion layer process, a common mask is used for A, B, C, and D, and only a partial mask of the last wiring system is used for A, B, C, and
D uses different masks. Therefore, a1 and b1 and c
1 and d1, a20 and b2, c20 and d2, a40 and b4
The diffusion layer patterns of 0 and c4 and d4, a50, b50, c50 and d5 are equal to each other. a20, b2, c20 and d
2, a40 and b40 and c4 and d4, a50 and b50 and c
The wiring layer patterns of 50 and d5 are different patterns. In this way, it is possible to manufacture a large chip vertically and horizontally with the same number of masks as a small chip by using the existing exposure apparatus. a20, a40, a50, b40, b50,
A combined area of c20 and c50 is formed between adjacent chips, and this becomes an ineffective area on the wafer. However, this area contribution on the wafer is considered small.

FIG. 6 shows a specific embodiment in which the two-division principle of FIGS. 1 and 4 is applied to the mask design of a highly integrated DRAM.
Further, FIG. 7 shows D for explaining the contents of each block in FIG.
It is a principal part circuit diagram of RAM. As shown in FIG. 6, M including a memory cell array, a sense amplifier, and a precharge circuit
Eight SAs and four sets of X decoders / word drivers are arranged in four corners. Other peripheral circuits are arranged in the center of the cross. A control circuit, a main amplifier, an output circuit, etc. are arranged in the peripheral circuit 1 in the horizontal direction, and an address buffer, an internal voltage generating circuit (a substrate voltage generating circuit, a voltage limiter), etc. are arranged in the peripheral circuit 2 in the vertical direction. It has a composition. Each M
Since the data line is further divided in SA, there are many combinations of the memory cell array and the sense amplifier, the precharge circuit, and the read / write circuit as shown in FIG. In FIG. 6, the X decoder and the word driver are horizontally arranged between the MSAs, and the Y decoder is vertically arranged at one end of the MSA. It is assumed that the word line W is vertically arranged and the data line D is horizontally arranged. The Y decoder output YS runs in the MSA parallel to the data lines and controls a number of read / write circuits. A large number of bonding pads are laterally arranged in the central portion, and the LOC (Lead on) disclosed in JP-A-61-241959 is disclosed.
Chip) package. Since the peripheral circuit is placed in the center as described above, the signal wiring delay time between the bonding pad, the peripheral circuit and the memory cell array can be reduced. As shown in FIG. 6, this whole chip is A1, B1 or A2,
Divide into B2. Here, 20 and 30 indicate division positions. Dividing left and right at the boundary 20 between the MSA and Y decoder corresponds to the basic embodiment of FIG. 1, and dividing at 30 in the peripheral circuit corresponds to the basic embodiment of FIG. Both of the two divided masks include half of the memory cell, the X decoder, the word driver, the control circuit, and the main amplifier. Most masks such as diffusion layer masks are Ai, Bi (i = 1 to 2)
Commonize with. The mask of the wiring layer is changed by Ai and Bi. The wiring connection at the boundary between Ai and Bi has a loose rule (width and space are wider than the inside of the mask) to ensure reliable connection even if mask misalignment occurs. For this purpose, it is better to divide the mask in the peripheral circuit portion such as 30. This is because this peripheral circuit is a so-called indirect peripheral circuit and has a loose layout irrespective of the repeating pitch of the memory cells. On the other hand, in the case of mask division by 20, the MSA composed of the memory cell array and the sense amplifier and the Y decoder are exposed with different masks. Since the line connected by both is a line having a high density and arranged at the memory cell repetition pitch like the Y decoder output line YS, it is difficult to take measures to widen the connection portion. Therefore, it is better to separate at 30. Repeated exposure of the Ai and Bi sub-chip masks causes one invalid area of width w10 corresponding to the Y decoder and the peripheral circuit 2 for each chip. Since this ineffective area causes a substantial increase in chip size, it is necessary to reduce the circuits in this area. To this end, it is necessary to devise that only the Y decoder is placed in the vertical peripheral circuit 2 and the address buffer and the like are placed in the horizontal peripheral circuit 1. It should be noted that the number of chips to be obtained from the wafer can be increased even if the guard ring wiring for supplying the substrate voltage is used or the scribing is performed using the ineffective region. Thus, most of the masks are shared by the left and right sub-chips, and only two partial masks for wiring need to be provided. An integrated DRAM can be manufactured.

FIG. 8 shows a state in which, for example, a 256 Mb DRAM chip is repeatedly printed on a wafer by using the DRAM embodiment of FIG. 6 described above. One chip is divided into two sub-chips. L is a common mask group for the diffusion layer and the partial wiring layer, and about 28 of the 30 masks can be shared. MA is a wiring layer mask for the right sub-chip, and M
B is a wiring layer mask for the left sub chip, which has a slightly different pattern. The masks that need to be separated from MA and MB may be a part of the wiring mask, that is, about 2 of the 30 masks. A single chip, 256Mb DRAM, whose functions are completed, is created by connecting two sub chips. Therefore, the number of masks required can be almost equal to that of a 128 Mb DRAM having a half chip size, but as a side effect, one invalid region appears for each chip. This invalid area occurs at the place where the vertical peripheral circuit is placed as described in FIG. Since this invalid area can be used as a chip cutting scribe area, it is not necessary to provide a new scribe area.

FIG. 9 shows two wafers having different degrees of integration on one wafer.
Types of chips, eg 256Mb DRAM and 128Mb
The state where the DRAM is burned in. The 128 Mb chip is used as a sub chip, and the 256 Mb is manufactured by mounting it.
L is a mask group for the diffusion layer and the partial wiring layer common to the two sub chips, and MA and MB are masks having different patterns for the two sub chips. If two masks MA and MB are continuously connected as shown in FIG. 8, 256 MbDRA
It becomes M. 128 using only one mask MA
It becomes MbDRAM. This makes it less susceptible to edge chipping, which inevitably occurs at the periphery of round wafers. That is, from FIG. 8 which aims at 256 Mb in total, it is possible to increase the number of chips that can fully operate by aiming at 128 Mb in the peripheral part from the beginning.

In each of the above embodiments, an invalid area is formed at the boundary of one chip. In FIG. 6, an invalid region having a total area of the vertical Y decoder and the peripheral circuit 2 is generated. Next, FIG. 1 shows an example of a DRAM chip configuration in which the area of the invalid region is small.
It shows in 0. In this example, the address buffer (AB) is placed at the center of the sub chips A and B and between the Y decoders (YDEC). Reference numeral 30 is a division position of the sub chips A and B. As is well known, a large number of address buffers exist in a chip, but since the X-system and Y-system have the same number and the same circuit, half each can be embedded in both sub-chips. Other circuits, for example, a circuit such as a clock driver, which requires only one circuit in the chip, may be divided into two and the circuit constant may be halved to be distributed to both sub chips. In this way, the invalid area can be reduced. Although the number of Y decoders is larger than that in FIG. 6, the load capacity of the Y decoder output YS is about ½ of that in FIG. 6, so that the MOS size of the Y decoder can be small and the required area of the Y decoder for the entire chip is as shown in FIG. Almost unchanged The invalid area in FIG. 10 is only the pattern area for adjusting the sub-chip end portion.

Although the above embodiments have been described by taking the DRAM as an example, the present invention can be applied to a static memory (SRAM) or a gate array. The present invention is also applied to a gate array chip having tens of thousands of gates, divided into a plurality of sub chips, a large number of masks such as a diffusion layer are shared between the sub chips, and only the wiring layer mask is different between the sub chips. Good. FIG. 11 specifically applies the 4-division basic embodiment described in FIG. 5 to a large-scale gate array 10 (dimension w1xh1) having a cross-shaped wiring channel portion in the central portion of the chip. The dimensions shown in FIG. 11 use the same symbols as in FIG. A mask including a logic gate group and a channel region and having a sub-chip D of dimension w3xh3 as a basic unit is formed, and this is repeated four times to expose one chip. Most of the diffusion layer masks can be shared.

In the above description, it is stated that two kinds of partial masks for the wiring system are provided. In the two-layer aluminum system, this mask is preferably the first layer aluminum, the second layer aluminum, or both. Two types of through-hole masks for connecting the two-layer aluminum may be required. It is not particularly necessary to newly provide wiring in another process, for example, a third layer aluminum in order to connect a plurality of sub chips. First with both sub-chip masks
If the patterns are such that the layer aluminum or the second layer aluminum connecting portions overlap each other, they can be connected to each other. Then, both masks can bring together the function of one chip.

[0016]

As described above, according to the present invention, a large-scale integrated circuit having a large chip size can be formed in the same exposure apparatus as the conventional one.
Since it can be manufactured with almost the same number of masks as an integrated circuit having a small chip size, a large-scale integrated circuit can be manufactured at low cost with high accuracy. The present invention is particularly effective when applied to an integrated circuit having a highly regular pattern such as a memory or a gate array.

[Brief description of drawings]

FIG. 1 Two-division basic embodiment

[Figure 2] Large-sized chip plan view

FIG. 3 Conventional mask division

FIG. 4 is a second two-division basic example.

FIG. 5: Basic example of 4-division

FIG. 6 is an example of dividing a DRAM mask.

FIG. 7 is a circuit diagram of a main part of DRAM.

FIG. 8: Wafer baking state diagram of 256 Mb chip

FIG. 9: Wafer baking state diagram of 256 Mb / 128 Mb chips

FIG. 10 is a DRAM chip configuration with a small invalid area when dividing a mask.

FIG. 11 is an example of mask division in a gate array.

[Explanation of symbols]

10 ... Large-sized chip, 11, 12 ... Adjacent large-sized chips, A, B, C, D ... Divided sub-chips drawn with one mask, 20, 30 ... Dividing position into sub-chips, w
1 to w4 ... lateral size of chip or sub chip, h1 to h3
... Vertical dimension of chip or sub-chip, MSA ... Block consisting of memory cell, sense amplifier, precharge circuit, read / write circuit, AB ... Address buffer, XD
EC & WD ... X decoder and word driver, YDEC ...
Y decoder.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yoshiki Kawajiri, Yoshiki Kawajiri, 1-280, Higashi Koikekubo, Kokubunji, Tokyo, Central Research Laboratory, Hitachi, Ltd. (72) Takeda Akiba, 3681, Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. (72) Inventor Norio Hasegawa 1-280, Higashi Koigokubo, Kokubunji City, Tokyo Central Research Laboratory, Hitachi, Ltd. (72) Inventor Hisashi ▲ Rei ▼ Tokuo, 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi Central Inside the laboratory (72) Inventor Kazuhiko Sagara 1-280, Higashi Koikeku, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Shoji Sukuri 1-280, Higashi Koikeku, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Takashi Nishida, Kokubunji, Tokyo Koigakubo 1-chome 280 address Hitachi, Ltd. center within the Institute

Claims (4)

[Claims] 1. A pattern exposure for manufacturing a large-scale integrated circuit having a predetermined function and a large chip size is performed by repeatedly using a sub-chip mask smaller than the one chip, so that the area exposed by the sub-chip mask is exposed. Since one part includes a circuit area unnecessary for the one chip, all sub-chip masks are masks for exposing circuit areas of the same size,
And the mask for the majority of the manufacturing process uses a mask for the sub-chip common between the sub-chips, and only the mask for the small number of manufacturing processes uses the mask for the sub-chip with different patterns between the sub-chips, and the exposure by the mask for the sub-chip is adjusted. A large scale integrated circuit characterized in that one chip is manufactured. 2. The large scale integrated circuit according to claim 1, comprising a memory, and the circuits adjacent to each other among the plurality of sub chips are:
A large-scale integrated circuit characterized by being an indirect peripheral circuit in which the repeating pitch is unrelated to the memory cells among the memory peripheral circuits. 3. A large scale integrated circuit according to claim 1, wherein the plurality of sub chips for forming the one chip includes a divided memory cell array having an equal number of bits. Scale integrated circuit. 4. A large-scale integrated circuit according to claim 1, wherein one chip of the large-scale integrated circuit is cut from the wafer chip by chip on a circuit area unnecessary for the one-chip.