JPH053298A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent lowering of mutual conductance of a transistor forming a peripheral circuit and to prevent lowering of velocity of write/read operation and generation of malfunction by adding a dummy wiring region having a layout pattern which is practically the same as a bit line balancing circuit. CONSTITUTION:A memory cell array region 4, a line decoder 5, a bit line balancing circuit 3, bit line electric potential supply circuits 1, 2, etc., are formed in a semiconductor chip 6. A dummy wiring region 7 is further provided to the outside of the memory cell array region 4 of the bit line electric potential supply circuit 1. Patterns of three wirings 10, 21 having the same wiring width and pitch are formed of the dummy wiring region 7 outside and inside a semiconductor chip 6 with a pattern of gate electrode 8a, 9a and polysilicon wirings 8b, 9b in the middle thereof. According to this symmetry, irregularities are not generated in light diffraction during mask pattern exposure for polysilicon layer formation and a width of the gate electrode 8a, etc., is prevented from exceeding a designed objective value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device, and more particularly to the structure of a peripheral circuit of a static random access memory (SRAM).

[0002]

2. Description of the Related Art Generally, a semiconductor memory device such as an SRAM comprises a memory cell array region, a decoder circuit adjacent to the memory cell array region, and peripheral circuits such as a bit line potential supply circuit. Of these peripheral circuits, specific peripheral circuits such as a bit line balancing circuit that balances the bit line pairs forming the memory cell array to the same potential and a bit line potential supply circuit that supplies a potential to the bit line pairs are bit lines. Must be installed in pairs. Therefore, these specific peripheral circuits are arranged along one side of the rectangular memory cell array region, that is, adjacent to one side of the peripheral portion of the memory chip. The gate electrodes of transistors (FETs, the same applies hereinafter) that form these specific peripheral circuits are generally formed of a polysilicon film, and the pattern density is extremely high.

[0003]

However, as described above, in the conventional semiconductor memory device including the above-mentioned specific peripheral circuit having such a configuration, the wiring is formed in a predetermined pattern from the memory cell array region to the other peripheral circuits. They are closely arranged. However, the circuit arranged on the outermost side of the peripheral circuits, that is, the circuit arranged on the outermost peripheral part of the memory chip (generally a part of the above-mentioned bit line potential supply circuit) has a lot of wiring arranged on one side. Not touching the outer periphery of the memory chip. At that portion, the wiring pattern changes from dense to sparse, and the regularity of the pattern is disturbed.

The width of the wiring near the region where the regularity of the formation pattern is disturbed in this way becomes larger than the design target value as compared with the wiring in the other regions whose dimension is kept regular. The inventors of the present invention have found that there is a tendency.
If the width of the wiring, particularly the wiring of polysilicon that becomes the gate electrode of the transistor becomes larger than the design target value, as a result, the channel length of the transistor becomes longer than the design target value. For example, when the design target value of the wiring width of polysilicon is 0.8 μm, the design target value of 0.06 μm
The width of the wiring becomes thicker by about m, and the channel length of the transistor using the wiring as a gate electrode becomes longer.

One of the reasons why the width of the wiring becomes thicker than the design target value is considered to be as follows. If the regularity of the wiring formation pattern is disturbed,
In the lithography process for selectively removing the polysilicon film, that is, in the process of applying a photoresist and then exposing with a predetermined mask pattern, the disordered part of the regularity affects the diffraction of light, It will change the conditions. That is, the exposure condition changes in such a direction that the width of the selectively left polysilicon film becomes larger than the design target value.

As described above, it is the circuit arranged at the outermost peripheral portion of the memory chip that the wiring width becomes thicker than the design target value, and it is generally a part of the bit line potential supply circuit. If the channel length of the transistor forming the potential supply circuit becomes long, the transconductance of the transistor is reduced, and as a result, the potential supply capability to the bit line is reduced.

The decrease in the potential supply capability for the bit line is caused by
Since the potential change of the bit line at the time of reading or writing a signal is delayed, not only the read / write speed of the semiconductor memory device is significantly lowered, but also a malfunction occurs.

Therefore, an object of the present invention is to provide a semiconductor memory device in which the reduction of the transconductance of the transistors forming the peripheral circuit is prevented, and the reduction of the writing / reading speed and the occurrence of malfunction are prevented.

[0009]

In a semiconductor memory device of the present invention, a memory cell array region formed in a substantially rectangular shape on the surface of a semiconductor substrate and a predetermined side of the memory cell array region are arranged adjacent to each other. A bit line balancing circuit having a first wiring pattern, a bit line potential supply circuit having a predetermined second wiring pattern arranged outside the bit line balancing circuit when viewed from the memory cell array region, and this bit. A first dummy wiring region having a pattern substantially similar to the first wiring pattern and arranged further outside the line potential supply circuit.

Further, the semiconductor memory device of the present invention further includes second dummy wiring regions arranged at both ends of each of the bit line potential supply circuits and having the second wiring pattern.

Preferably, the first and second dummy wiring regions are formed in the same manufacturing process as the wiring patterns of the bit line balancing circuit and the bit line potential supply circuit.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.
Referring to FIG. 1, a semiconductor chip 6 constituting a semiconductor memory device according to an embodiment of the present invention includes a memory cell array region 4 in which memory cells are arranged in an array and a row decoder for selecting a word line according to an input address. 5, a bit line balancing circuit 3 for balancing the bit line pair to the same potential, and bit line potential supply circuits 1, 2 for supplying a potential to the bit line pair. Although the circuit is also provided, those other circuits are omitted for convenience of description).

Since the bit line balancing circuit 3 and the bit line potential supply circuits 1 and 2 are connected to the bit line pairs forming the memory cell array region 4, they are arranged adjacent to the memory cell array region 4. Specifically, the bit line balancing circuit 3 is arranged along one side of each of the memory cell array regions 4, and the bit line potential supply circuits 1, 2 are located outside the memory cell array region 4 of the bit line balancing circuit 3. Are placed.

Further, a dummy wiring region 7 is provided outside the memory cell array region 4 of the bit line potential supply circuit 1. The dummy wiring region 7 is formed of a polysilicon wiring layer having a shape similar to the polysilicon wiring of the bit line balancing circuit 3, as will be described later.

Next, referring also to FIG. 2, a plurality of memory cells MC are arranged in an array to form a memory cell array region 4. 1 for each memory cell MC
Two word lines WL and two bit line pairs La, BLb (in FIG. 2, only the rightmost column has a bit line pair BLa, BLa,
BLb) are connected to each other. The number of bit line pairs is equal to the number of columns of memory cells forming memory cell array region 4. Each of these bit line pairs is connected to the bit line balancing circuit 3 and the bit line potential supply circuits 1 and 2, respectively.

The bit line balancing circuit 3 has a transistor M whose source / drain paths are connected to the bit lines BLa and BLb and whose gate is connected to the wiring 10 for supplying the control signal φ.
P30 is included in the number of bit line pairs.

The bit line potential supply circuits 1 and 2 have sources,
A plurality of transistors MP whose drain paths are connected to the power supply terminal Vcc and the bit line BLa and whose gates are connected to the ground power supply.
10 and a plurality of transistors MP20 whose source / drain paths are connected to the power supply terminal Vcc and the bit line BLb and whose gates are connected to the ground power supply. Since the chip surface area is restricted in the arrangement of the transistors MP10 and MP20, a plurality of transistors M
The region in which P10 is formed is the bit line supply circuit 1 and the region in which a plurality of transistors MP20 are formed is the bit line supply circuit 2 which are formed in an interlaced manner as shown in the figure.

The dummy wiring region 7 is arranged further outside adjacent to the bit line potential supply circuit 1 as described above.

In the read operation of this semiconductor memory device, one word line WL selected by row decoder 5 is activated. The storage contents of the plurality of memory cells MC connected to the word line WL are supplied to each bit line pair. Bit lines BLa and BLb forming a bit line pair
Either one of them has a potential lower than the power supply potential according to the stored contents of the memory cell MC, and the other bit line remains at the power supply potential. A potential difference between the two bit lines is amplified by a sense amplifier (not shown) and sent out to an output circuit (not shown) through one bit line pair selected by a column decoder (not shown) to obtain one bit line. The read operation for the stored contents is completed. Then, before the next reading, the control signal φ is set to the active level to electrically connect the bit lines BLa and BLb, and the bit line potential supply circuits 1 and 2 further connect the bit lines BLa and Bb.
Both Lb restore the power supply potential.

In this way, the bit line potential supply circuits 1, 2
The bit line balancing circuit 3 restores the potentials of the two bit lines forming the bit line pair to the power source potential, and then the next read operation is performed.

FIG. 3 is a plan view showing the bit line potential supply circuits 1 and 2, the bit line balancing circuit 3 and the dummy wiring region 7 of the semiconductor memory device shown in FIG. The same components as those in FIG. 2 are denoted by the same reference numerals.

The transistor MP10 is formed in the diffusion layer forming region 13, the gate electrode made of the polysilicon layer 8a is integrally formed with the polysilicon wiring 8a, and the source region is made of a plurality of contacts to the bit line BLa made of an aluminum film. The drain region is connected to the power supply wiring 11 made of an aluminum film through a plurality of contact holes 12b.

The transistor MP20 forming the bit line potential supply circuit 2 is also formed in the diffusion layer forming region 13,
The gate electrode made of the polysilicon layer 9a is formed integrally with the polysilicon wiring 9b, the source region is connected to the bit line BLa made of an aluminum film through a plurality of contact holes 12a-2, and the drain region is common to the transistor MP10. It is formed of a drain region and is connected to the power supply wiring 11 made of an aluminum film through a plurality of contact holes 12b.

The transistor MP30 forming the bit line balancing circuit 3 is formed in the diffusion layer forming region 16 and its gate electrode is composed of three polysilicon wirings 10.
The source and drain regions are connected to the bit lines BLa and BLb through the contact holes 15, respectively.

The dummy wiring region 7 is a polysilicon wiring 10
And the bit line potential supply circuit 2 and the bit line balancing circuit 3 are separated from the bit line supply circuit 1 by a distance equal to the distance between the bit line potential supply circuit 2 and the bit line balancing circuit 3. There is.

Next, the manufacturing process of this embodiment will be described. The surface of the semiconductor substrate is selectively oxidized to partition the memory cell array region 4, the diffusion layer forming regions 13 and 16, and the like.
Next, a gate oxide film is formed in the diffusion layer forming regions 13 and 16, and a phosphorus-doped polysilicon film having a thickness of 350 to 400 nm is deposited. Next, a positive photoresist film is deposited and the pattern on the photomask is transferred to the photoresist film. By this step, the dummy wiring region 7 together with the gate electrode 8a of the bit line potential supply circuit 1, the polysilicon wiring 8b, the gate electrodes 9a and 9b of the bit line potential supply circuit 2, the gate electrode 10 of the bit line balancing circuit 3 and the like. Are also formed at the same time.

The polysilicon film is patterned by plasma etching using the photoresist film to which a predetermined pattern is transferred as a mask to form gate electrodes 8a and 9a, polysilicon wirings 8b and 9b, and dummy wiring region 7.

FIG. 4 shows a wiring pattern of the polysilicon film formed in this same step. As shown in the figure, by providing the dummy wiring region 7, the gate electrodes 8a and 9
A pattern of three wirings 10 and 20 having the same wiring width and pitch is formed on the outer side and the inner side of the semiconductor chip 6 centering around the pattern of a and the polysilicon wirings 9a and 9b. With this configuration,
Gate electrodes 8a, 9a and polysilicon wirings 9a, 9
b, the dummy wiring region 7 can be formed in a pattern symmetrical with respect to a line (CL in FIG. 4) passing through the centers of the gate electrodes 8a and 9a.

Next, using the gate electrode 8a and the polysilicon wiring 8b as a mask, ions are implanted into the diffusion layer forming regions 13 and 16 to form source and train regions, thereby forming transistors MP10, MP20 and MP30.

Deposition of interlayer insulating film, contact holes 12, 1
After the formation of 3 and 14, the aluminum film is deposited to form the power supply wiring 11 and the bit lines BLa and BLb.

Through the above steps, the semiconductor memory device according to this embodiment is formed.

Referring to FIG. 5, the number of the gate 8a counted to the left with the gate electrode 8a-1 at the right end of FIG. 4, that is, the chip end as 1 is taken on the horizontal axis, and the gate width L of the gate electrode 8a of each number is taken. In the graph in which the vertical axis is taken as the vertical axis, the value of the width L of the gate electrode of the transistor MP10 of the bit line potential supply circuit 1 obtained by the present embodiment is indicated by a black dot, and the width L of the gate electrode by the conventional technique is indicated by X. Has been done. In this embodiment, the width L of the gate electrode 8a is 0.8 mμ.
m (A in FIG. 5), and the pitch of the electrodes 8a is 5 μm.

As is apparent from FIG. 5, the width of the gate electrode of the semiconductor memory device according to the prior art is the design target value 0.
8 .mu.m is increased from 0.05 .mu.m to 0.06 .mu.m, the difference between the two is 0.
It is less than 03 μm. As described above, the reason why the width of the gate electrode can be prevented from becoming larger than the design target value is that the formation pattern of the polysilicon layer including the gate electrodes 8a and 9a and the polysilicon wirings 8b and 9b is This is because the dummy wiring region 7 has the above-mentioned symmetry (see FIG. 4), so that the above-mentioned unevenness does not occur in the diffraction of light during the mask pattern exposure for forming the polysilicon layer.

As described above, when the width of the gate electrode becomes large and the channel length becomes long, the transconductance of the transistor decreases.

Referring to FIG. 6 in which the horizontal axis represents time t and the vertical axis represents the potential of the bit line and the read output in order to more quantitatively show the adverse effect of the decrease in the mutual conductance of the transistor, etc. The decrease in mutual conductance of the transistor MP10 forming the line potential supply circuit is
Since the potential change of the bit line changes from the solid line (1) a to the dotted line (1) b and causes a delay, the delay of the read output of the semiconductor memory device from the solid line (2) a to the dotted line (2) b ( In the above conventional example, about 2 to 3 nsec) is generated.
These problems were solved by this embodiment.

In the above embodiment, the dummy wiring area 7
The wiring pattern 20 has a shape similar to that of the polysilicon wiring pattern 10, that is, it is described as a polysilicon wiring in which the number of stripes, the width and the pitch are substantially the same. It does not have to be exactly the same as 10, and it is sufficient if the above-mentioned symmetry is substantially maintained.

Apart from increasing the width of the polysilicon wiring layers of the bit line potential supply circuit 1 arranged in the peripheral portion of the memory chip, which is the object of the improvement of the first embodiment, the wiring patterns of these polysilicon wiring layers are The inventor of the present invention has observed that the width of the wiring increases at both ends of each. This second embodiment provides a solution to this problem.

More specifically, the increase in the width of the polysilicon wiring layer is generated not only in the bit line potential supply circuits 1 and 2 near the peripheral portion of the memory chip as viewed from the memory cell array region but also in the bit line potential supply. Since the same can be seen in the respective lengthwise end portions of the polysilicon wiring patterns of the circuits 1 and 2, in order to cope with this, in the second embodiment, each of the bit line potential supply circuits 1 and 2 is treated. Dummy wiring regions 17 are provided at both ends of the (see FIG. 7). In the second embodiment, the constituent elements other than the dummy wiring area 17 are common to the first embodiment, and therefore, in FIG. 7, the constituent elements are indicated by common reference numerals and the description thereof is omitted. To do.

FIG. 8 is a plan view showing the bit line potential supply circuits 1 and 2, the bit line balancing circuit 3 and the dummy wiring region 17 of the semiconductor memory device of FIG.

The pattern configurations of the transistors MP10 and MP20 forming the bit line potential supply circuits 1 and 2 and the transistor MP30 forming the bit line balancing circuit 3 are the same as those in FIG.

The dummy wiring region 17 is constituted by the same pattern as the pattern constitution of the gate electrode 8a made of a polysilicon layer and the polysilicon wiring 8b constituting the bit line potential supply circuits 1, 2, and the bit line supply circuits 1, 2 are formed. Are provided at both ends of. As is clear from FIG. 9 in which only the polysilicon wiring pattern is taken out from this pattern configuration, the polysilicon layers 8a at the end portions of the circuits 1 and 2 are
Polysilicon wiring layer 18a integrally with the pattern of 8b,
18b is arranged. In this embodiment, the dummy wiring area 1
Reference numeral 7 denotes two polysilicon wirings 18a and these wirings 18a.
and a wiring 18b connected to a.

As shown in the graph of FIG. 10 in which the same physical quantity as in FIG. 5 is plotted on the horizontal axis and the vertical axis on the same scale, the effect of the dummy wiring region 17 of the bit line potential supply circuits 1 and 2 according to the present embodiment is the same as that of the conventional one. This is remarkable compared to the case of using technology (indicated by X). In this graph, the width of the gate electrodes 8a is 0.8 mμm (A in FIG. 10) and the pitch between the 8a is 5 μm, as in FIG.

As is apparent from FIG. 10, the width L of the polysilicon wiring is the second from the end of the pattern (the right end of the circuit pattern of FIG. 7), that is, the two wirings 18a-2 in the dummy wiring region 17. Although it is larger than the design target value, there is not much difference from the design target value in the third and subsequent polysilicon wirings, that is, the gate electrodes 8a-1 and 8b. Therefore, the present embodiment suppresses the increase in the width of the gate electrodes of the transistors forming the bit line potential supply circuits 1 and 2, and prevents the reduction of the mutual conductance of the transistors.

In this embodiment, the dummy wiring region 17 is composed of two polysilicon wirings 18b. If the number of the polysilicon wirings 18b is three or more, the gate electrode 8a,
The difference between the width of 8b and the design target value becomes smaller.

Further, the gate electrode 10 of the transistor MP30 forming the bit line balancing circuit 3 is also the dummy wiring region 1
7 to the lower side as shown in FIG. 8, it is possible to further suppress variations in design target values for the gate electrode 8a and the polysilicon wiring layers 8b and 10.

Also in this embodiment, as in the first embodiment, the wirings 18a and 18b forming the dummy wiring area 17 are formed.
It is not necessary that the values of the wiring width, the pitch width, etc. of the gate electrodes 8a and 8b are exactly the same as those of the gate electrodes 8a and 8b. For example, the effects described above can be obtained.

By carrying out the second embodiment in combination with the first embodiment, the transistors in both the vertical and horizontal directions of FIG. 3 or 8 as viewed from the memory cell area of the bit line potential supply circuits 1 and 2. It will be apparent to those skilled in the art that it becomes possible to eliminate the nonuniformity of the gate width and improve the effect of preventing a decrease in writing and reading speeds and a malfunction.

Further, in the above-mentioned first and second embodiments, the case where the gate electrode of the transistor is made of polysilicon has been described, but the case where these gate electrodes are made of other materials such as aluminum is also used. It will be clear that the invention has similar applicability.

Further, the present invention is not limited to the SRAM constructed by the first and second embodiments, but may be a DRAM (dyna).
micRAM), mask ROM, PROM (progr
amableread only memory),
EPROM (erasable PROM), EEPROM
(Electrically erasable PR
It will be apparent to those skilled in the art that OM), etc. are equally applicable.

[0050]

As described above, the semiconductor memory device of the present invention can prevent the reduction of the mutual conductance of the transistors forming the peripheral circuit, and the speed of writing and reading operations of the semiconductor memory device can be reduced and the erroneous operation can be prevented. It has become possible to prevent

[Brief description of drawings]

FIG. 1 is a plan view schematically showing an entire semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific circuit configuration of the semiconductor memory device shown in FIG.

3 is a plan view schematically showing a wiring pattern of a part of a bit line potential supply circuit and a bit line balancing circuit of the semiconductor memory device shown in FIG.

FIG. 4 is a plan view showing a wiring pattern of only a polysilicon wiring layer of the wiring patterns shown in FIG.

FIG. 5 is a graph showing variations in gate width with respect to design target values in the semiconductor memory device according to the present embodiment and the prior art.

FIG. 6 is a waveform diagram showing a voltage level waveform and an output waveform of a bit line of a semiconductor memory device.

FIG. 7 is a plan view schematically showing an entire semiconductor memory device according to a second embodiment of the present invention.

8 is a plan view schematically showing part of a wiring pattern of a bit line potential supply circuit and a bit line balancing circuit of the semiconductor memory device shown in FIG. 7. FIG.

9 is a plan view showing a wiring pattern of only a polysilicon wiring layer among the wiring patterns shown in FIG. 7. FIG.

FIG. 10 is a graph showing variations in gate width with respect to a design target value in semiconductor memory devices according to the present embodiment and the prior art.

[Explanation of symbols]

1, 2 bit line potential supply circuit 3-bit line balancing circuit 4 Memory cell array area 5 row decoder 6 semiconductor chips 7 Dummy wiring area

Claims (4)

[Claims] 1. A memory cell array region formed in a substantially rectangular shape on the surface of a semiconductor substrate, and a bit line balancing circuit having a first circuit layout pattern arranged adjacent to a predetermined side of the memory cell array region. A bit line potential supply circuit having a second circuit layout pattern arranged outside the bit line balancing circuit as seen from the memory cell array region, and the first layout pattern arranged further outside the bit line supply circuit. And a first dummy wiring region having substantially the same circuit layout pattern as the semiconductor memory device. 2. A memory cell array region formed in a substantially rectangular shape on a surface of a semiconductor substrate, and a bit line balancing circuit having a first circuit layout pattern disposed adjacent to a predetermined side of the memory cell array region. A bit line potential supply circuit having a second circuit layout pattern, which is arranged outside the bit line balancing circuit as viewed from the memory cell array region, and arranged at both ends of the bit line potential supply circuit, and each of which is the first line. And a second dummy wiring region having a circuit layout pattern substantially the same as the second circuit layout pattern. 3. The semiconductor memory device according to claim 1, wherein the first dummy wiring region is provided in the same manufacturing process as a predetermined wiring of the bit line potential supply circuit. 4. The semiconductor memory device according to claim 3, wherein the predetermined wiring of the bit line potential supply circuit is a polysilicon film.