JP2752817B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a structure of a multilayer wiring layer in a memory cell array region of a random access memory (hereinafter referred to as a RAM).

[0002]

2. Description of the Related Art In general, a semiconductor memory device generally includes a memory cell array region and a decoder circuit, a selection circuit, and the like adjacent thereto. Among these components, the memory cell array region is formed by regularly arranging MOS transistors forming the memory cells.

Referring to FIG. 5, which shows a circuit diagram of a conventional SRAM including a memory cell formed by an nMOS transistor, the SRAM has a memory cell S1 in both a column and a row direction.
1 / S12 and S21 / S22 are arranged in an array to form a memory cell array region. Word lines W1 and W2 extending in the row direction are connected to memory cells S11 / S12 and S21 / S22, respectively. A pair of digit lines D1 and D2 extending in the column direction are connected to each of these memory cells. Have been. Digit lines D1 and D2 are connected to transistors T1 and T2, respectively.
And a balancing circuit consisting of a transistor T3 receiving a signal φ at its gate electrode. Further, the switching transistors T4 and T5 connected to the digit line pairs D1 and D2, respectively, so as to form a column selection circuit, and the switching transistors T4, T5 connected to these column selection circuits so as to amplify a potential difference between the selected digit line pairs. And a sense amplifier SAMP.

[0004] Memory cells S11 / S12, S21 / S2
, A flip-flop circuit formed by cross-coupling a first inverter circuit including a transistor M1 and a resistor R1, and a second inverter circuit including a transistor M2 and a resistor R2, A circuit between one input / output terminal (ie, the node of the first inverter circuit) C and the digit line D1 and another input / output terminal (ie, a node of the second inverter circuit) D and the digit line D2. Source / drain electrodes are connected between them, and the transfer gate transistors M3 and M4 whose gates are commonly connected to the word line W1.

Whether the data stored in one memory cell is 0 or 1 depends on whether the potentials of the nodes C and D are a high-low combination or a low-high combination. I have decided.

At the time of reading from this SRAM, a selected word line (for example, W1) is activated, and transfer gate transistors M3 and M4 are turned on to connect nodes C and D to digit lines D1 and D2, respectively. Either of the potentials of these two digit lines falls according to the data stored in the memory cell, that is, the potentials of the nodes C and D, and a potential difference occurs between the two. This potential difference is amplified by the sense amplifier SAMP and sent to an output circuit (not shown).

At the time of a write operation, a potential difference corresponding to write data is applied to digit lines D1 and D2 to turn on transfer gate transistors M3 and M4.
Set the potential of.

Referring to FIG. 6, which shows a circuit pattern of a part of the memory cell array region of the SRAM shown in FIG. 5 with the same reference numerals assigned to the same components as in FIG. 5, a thin solid line is a field oxide film formed by selective oxidation. Indicating a partitioned active area,
The hatched region indicates a polycrystalline silicon region above the active region, the cross-hatched region indicates a direct contact region between the polycrystalline silicon region and the active region,
The thick solid line indicates an aluminum wiring layer further above the polycrystalline silicon region.

The transistor M1 is provided in the active region 1, and its gate electrode G1 is made of a polycrystalline silicon film.
The drain region d2 (node D) of the transistor M2 is connected by the direct contact 7, the source region sc1 is connected to the polysilicon wiring 11 by the direct contact 10, and the drain region d1 of the transistor M2 made of a polysilicon film. Gate electrode G2
(Node C) via a direct contact 8.

The transistor M2 is provided in the active region 2 and its source region scS2 has a direct contact 1
2 is connected to the polycrystalline silicon wiring 11 and connected to the ground line GND made of aluminum wiring by the contact hole 4.

The transistor M3 is provided in an active region 3a which is an extension of the active region 3, and its source and drain have a contact hole 5 (node A) connected to a digit line D1 and a gate electrode G2 of the transistor M2.
The gate electrode G3 is formed by an intersection region between a word line W1 made of polycrystalline silicon wiring and the active region 3a.

The transistor M4 is an extension of the active region 2 and is provided in an active region 2a running parallel to the length direction of the active region 3a. The source and the drain of the transistor M4 are provided in a contact hole 6 connected to the digit line D2. (Node B) and a direct contact 7 (node D) connected to the gate electrode G1 of the transistor M1. The gate electrode G4 is formed between the word line W1 made of polysilicon wiring and the active region 2a. It is formed by the intersection area.

Although the load resistors R1 and R2 and the power supply line Vcc are not shown in FIG. 6, both of them are formed by a well-known process in a polycrystalline silicon film different from the polycrystalline silicon film forming the transistor. And is formed in the memory cell array region.

The transistor M formed by the above process
The memory cell S11 is configured by 1 to M4, the load resistors R1 and R2, and the wiring between these circuit elements.
Memory cell S1 having the same circuit configuration as memory cell S11
Since the formation of 2, S21, and S22 is simultaneously performed in the same step as that of the cell S11, only the corresponding circuit elements are shown in FIG. 6, and detailed description is omitted.

Generally, in a memory cell array region of an SRAM, a power supply line Vcc or a ground power supply line GND is drawn in from a peripheral portion at a rate of one for every six to twelve memory cells, and is arranged between the memory cells. SRAM shown in FIG.
Then, a ground power supply line GND extending in the vertical direction (FIG. 5) between memory cells S11 and S21 and between memory cells S12 and S22 is formed of an active region or an aluminum wiring layer above the polycrystalline silicon layer. It is arranged.

As described above, in a memory cell array region in which memory cells are arranged in an array in both column and row directions, most of the polycrystalline silicon regions forming word lines and gate portions of transistors maintain regularity. It is formed with a circuit pattern. That is, in the example of FIG. 6, the polycrystalline silicon regions forming the transistors M1, M2, M3 and M4 are formed with a regular wiring pattern in the memory cell array region.

[0017]

Referring to FIG. 7, which shows only a wiring pattern of a polycrystalline silicon layer in a conventional memory cell array region over a region 200 surrounded by a dotted line in FIG. 6, a transistor M1 The wiring pattern of the polysilicon layer forming the gate electrodes G1 and G2 of M2 and M2 maintains regularity in the memory cell array region not shown in FIG. However, since power supply lines GND (shown by dotted lines in FIG. 7) are arranged in the memory cell array region by the upper aluminum wiring layer, transistors around the region where these power supply lines GND are arranged are: The arrangement regularity is disturbed.

That is, as described above with reference to FIG. 6, a ground power supply made of an aluminum layer extending in the column direction (FIG. 5) is provided between memory cells S11 and S21 and between memory cells S12 and S22. Since line GND is arranged, a polycrystalline silicon region forming gate electrode G2 of transistor M2 of one memory cell, for example, cell S11, and a polycrystalline silicon forming gate electrode G2 of transistor M2 of cell S12 adjacent to this memory cell The spacing GP (FIG. 7) from the silicon wiring region becomes wider than the spacing between the other polysilicon regions, and the regularity of the spacing in the wiring pattern of the polysilicon region is disturbed in this portion.

Referring to FIG. 8 showing a sectional view taken along line XX of FIGS. 6 and 7, the active region 2 on the P-type silicon substrate 40 is shown.
Diffusion regions sc2 and d2 serving as source and drain regions of the transistor M2 of the cell S11 are formed therein,
A gate electrode G2 made of polycrystalline silicon is formed on oxide film 41 serving as a gate insulating film of this transistor. The source and drain regions and the gate electrode of the transistor M2 of the cell S12 are also formed in the same process as the corresponding region of the transistor M2 of the cell S11. The width of the gate electrode G2 of these transistors M2 is the gate length L. After the gate electrode wiring G2 is formed, the entire chip is covered with an insulating layer 42, and a plurality of digit lines D1 formed of an aluminum wiring layer extending in the same direction as the gate electrode G2 and the same pair of these digit lines D1 are formed thereon. Power supply line GND made of aluminum wiring layer extending in the direction
Are arranged respectively. Since no polysilicon wiring is formed below the ground power supply line GND, the cell S1
As described above, the distance GP between the gate electrode G2 of the first transistor M2 and the gate electrode G2 of the corresponding transistor M2 of the cell S12 is wider than other portions, and the regularity of the polysilicon wiring pattern is disturbed.

In order to show the influence of the disorder of the regularity on the dimension design value of the polycrystalline silicon layer, the distance D (μm) from the end of the polycrystalline silicon region to the ground power supply line GND is plotted on the horizontal axis, and the transistor M2 Referring to FIG. 9 in which the measured values are plotted with black points with the gate length L (μm) (FIG. 8) of FIG. 8 as the vertical axis, the difference between these measured values and the design value GL of the gate length L is clear. That is, as shown in FIG. 9, the difference (ΔL1) from the design value GL increases as the width L of the polycrystalline silicon layer defining the gate length of the transistor M2 becomes closer to the ground power supply line GND. For example,
When the design value GL is 0.8 μm, the maximum value of ΔL1 is 0.
025 μm.

A gate length L larger than the design value causes the following problem. That is, the abscissa represents the gate length L (μm), the drain current I (mA) represents the ordinate, and the gate voltage 3 V is used as a parameter. As shown in FIG. 10, the gate length L is ΔL1 from the design value GL (0.8 μm).
(Μm), the drain current I (mA) is Δ
Decrease by I (mA). Therefore, for example, in a device designed to have a required drain current of 0.648 mA, if the gate length L deviates from the designed value by 0.025 μm to the larger value, the drain current becomes 0.0324 mA, that is, 5% of the required value. Will also decrease. as a result,
The rise of the read output from the memory cell is delayed, which not only greatly reduces the corresponding speed of the memory, but also causes a read error in some cases.

That is, as shown in FIG. 11 in which time is plotted on the horizontal axis and voltage (mA) is plotted on the vertical axis, the above-mentioned performance degradation of the transistor is caused by the potential change of the digit line connected to the transistor. A delay is caused in (1) (change from the solid line to the dotted line), and a delay is caused in the output (2) of the sense amplifier that amplifies the potential difference of the digit line. As a result, the data output time (3) of this SRAM is delayed (approximately 1.7 nsec), not only remarkably lowering the performance but also causing read / write errors.

Variations in the size of the active region that cause these problems are caused by the disorder in the regularity of the wiring pattern, and the lithography process for selectively removing the polycrystalline silicon film.
In other words, after applying the photoresist film, the step of exposing with a predetermined mask pattern affects light diffraction and changes exposure conditions. Changes in the exposure conditions cause variations in the dimensions of the polycrystalline silicon regions that are selectively left, and consequently impair the uniformity of the gate length.

Accordingly, an object of the present invention is to provide a semiconductor memory device which prevents an increase in the gate length of a transistor in the power supply line arrangement portion in a memory cell array region, thereby preventing a reduction in the mutual conductance, a reduction in response speed, and a malfunction. To provide.

[0025]

A semiconductor memory device according to the present invention has an electrode region and a wiring region on an upper conductor layer and a lower wiring layer formed on a semiconductor substrate with an insulator layer interposed therebetween. A memory cell array including a plurality of transistors and including a plurality of memory cells arranged in an array in both column and row directions, and a selection for electrically selecting the memory cells and the array in the column and row directions through the conductor layer Means and a data transfer means for controlling data transfer to and from the selected memory cell, wherein the random access memory includes at least one of the selection means and the data transfer means in a part of the memory cell array. In a semiconductor memory device in which constituent parts are arranged adjacent to each other, first and second memory cells of the memory cell array in the adjacent arranged part are arranged. The electrode region and the wiring region of the transistor constituting each of the memory cell arrays are formed in the lower conductive layer, and the dummy wiring region that is not electrically connected to the electrode region and the wiring region is formed by the first and second memories. Formed on the lower conductor layer between the cells of the array,
At least one of the selection means and the data transfer means is formed in the upper wiring layer between the first and second memory cell arrays, and the dummy wiring and the selection means are electrically connected. I have.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.
FIG. 6 is a circuit pattern diagram similar to FIG.
Referring to FIG. 1 showing a RAM, the conventional nMO
Memory cells S11 / S12, S2 by S transistors
Components common to the SRAM including 1 / S22,... Are denoted by the same reference numerals.

In contrast to the conventional example shown in FIG.
Two transistors M2 adjacent to the ground power supply line GND
(Each transistor M2 of cells S11 and S12)
The dummy region 100 is arranged between the gate electrodes G2 made of the polycrystalline silicon film and just below the ground power supply line GND.

Referring to FIG. 1 and also to FIG. 2 showing the same polycrystalline silicon wiring pattern as in FIG. 7, the structure of this embodiment will be described in more detail. Polycrystalline silicon wiring layer which is a wiring layer one layer below the wiring layer including the line GND (FIG. 2)
At the same time as the gate electrodes G2 (shown in the XX line portion in FIG. 2 and the right center portion in FIG. 8) of each of the two transistors, an upper layer ground between these electrodes G2. The dummy region 100 is formed immediately below the power supply line GND via an insulating layer (described later). These dummy areas 1
00 through the contact hole 14
D is connected.

Referring to FIG. 3, which is a sectional view taken along line XX of FIGS. 1 and 2, the active region 2 is formed by the field insulating film 43 formed on the P-type silicon substrate 40 by the field oxidation process. And a region where the transistor M2 of the cell S12 is formed. Diffusion regions sc2 and d2 serving as source / drain regions of transistor M2 are formed in each active region 2 of cells S11 and S12, and a polycrystalline silicon wiring is formed on oxide film 41 forming a gate oxide film of the transistor. The gate electrode G2 is formed.

Further, on the field insulating film 43, that is,
Between two gate electrodes G2, a dummy region 1 of polycrystalline silicon formed in the same process as these gate electrodes G2
00 is formed. An insulating layer 41 is formed to cover the two gate electrodes G2 and the dummy region 100, and a pair of aluminum digit lines D1 and a ground power supply line GND extending in the same direction are disposed on the insulating layer 41, respectively. In the configuration of this embodiment, the ground power supply line GND
Since there is a dummy region 100 of polycrystalline silicon formed in the same step as the electrodes G2 between the gate electrodes G2 of the pair of transistors M2 adjacent to the above, regularity of the polycrystalline silicon wiring pattern can be maintained. The problem of the device structure according to the prior art can be solved.

That is, similarly to FIG.
The distance D from the end of the polysilicon region 2 to the ground power supply line GND is plotted on the horizontal axis, and the gate length L is plotted on the vertical axis. It is clear that there is. Therefore, according to the present invention, a decrease in the transconductance of the transistors in the memory cell array region due to an increase in the gate length is prevented, and accordingly, problems such as a reduction in the response speed of the SRAM and a read error are solved. You.

In the above-described embodiment, the S
Although the present invention is a RAM, the present invention is also applicable to an SRAM configured by pMOS. In that case, the ground power supply line GND in the circuit pattern of FIG. 1 may be set to the power supply line Vcc connected to the power supply voltage Vcc.

Further, the present invention will be apparent to those skilled in the art,
A memory including not only an SRAM but also a memory cell array in which memory cells are regularly arranged, that is, a DRAM (dy)
nativeRAM), PROM (programmab)
le read only memory), EPROM
(Erasable PROM), EEPROM (el
electricallyly erasable PRO
M), a shift register, a CCD memory, and the like.

[0034]

As described above, according to the semiconductor memory device of the present invention, a reduction in the transistor performance can be prevented by suppressing the variation in the gate length of the transistor in the memory cell array region, and the data output time of the semiconductor memory device can be reduced. It has become possible to prevent performance degradation and malfunction of the semiconductor memory device due to the delay.

[Brief description of the drawings]

FIG. 1 is a circuit diagram similar to FIG. 6 of an SRAM according to an embodiment of the present invention.

FIG. 2 is a circuit pattern diagram of a polycrystalline silicon wiring layer forming a part of a memory cell array region of this embodiment.

FIG. 3 is a sectional view taken along line XX of FIGS. 1 and 2;

FIG. 4 is a graph showing a correspondence relationship between a design value and a measured value of a gate length in an FET included in the SRAM of FIG. 1;

FIG. 5 is a circuit diagram of an example of a conventional SRAM.

6 is an FE in a memory cell array region of the SRAM of FIG. 5;
It is a circuit pattern diagram which shows T and other circuit elements.

FIG. 7 is a plan view showing a wiring pattern of a polycrystalline silicon wiring layer forming a part of the memory cell array region of FIG. 6;

FIG. 8 is a sectional view taken along line XX of FIG. 6;

FIG. 9 is a grab showing a correspondence between a design value of a gate length and an actually measured value of a FET included in the SRAM of FIG. 6;

FIG. 10 is a graph showing a relationship between a gate length and a drain current of the FET described above.

FIG. 11 is a waveform diagram showing a voltage applied to a digit line and a read voltage of the SRAM of FIG. 9;

[Explanation of symbols]

 S11, S12, S21, S22 Memory cell W1, W2 Word line M1, M2, M3, M4 Transistor A, B, C, D node G1, G2, G3, G4 Gate electrode GND Ground power supply line 100 Dummy area

Claims (7)

(57) [Claims] An upper conductor layer and a lower wiring layer formed on a semiconductor substrate with an insulating layer interposed therebetween include a plurality of transistors each having an electrode region and a wiring region, and arrayed in both column and row directions. Memory cell array composed of a plurality of memory cells arranged in a matrix, selecting means for electrically selecting the memory cells and the array in the column and row directions through the conductor layer, and data to the selected memory cells A random access memory including data transfer means for controlling transfer, wherein at least one component of the selection means and the data transfer means is arranged adjacent to a part of the memory cell array; Transformers constituting each of the first and second memory cell arrays among the memory cell arrays in the adjacent arrangement portion The electrode region and the wiring region of the transistor are formed in the lower conductor layer, and the dummy wiring region that is not electrically connected to the electrode region and the wiring region is formed between the cells of the first and second memory arrays. And at least one of the selection means and the data transfer means is formed in the upper wiring layer between the first and second memory cell arrays, and an electric connection is provided between the dummy wiring and the selection means. A semiconductor memory device characterized by being connected in a series. 2. The dummy region according to claim 1, wherein the electrode region and the wiring region of the transistor constituting each of the cells of the first and second memory cell arrays and the dummy region have a similar shape. Semiconductor storage device. 3. The semiconductor memory device according to claim 1, wherein said dummy wiring region and said lower wiring layer are formed simultaneously in the same step. 4. The semiconductor memory device according to claim 1, wherein said lower wiring layer is made of polycrystalline silicon. 5. A first and a second in said adjacent arrangement part.
Wherein said memory cell arrays are arranged adjacent to each other with a power supply line interposed therebetween, and transistors corresponding to each of the cells of said memory cell array are symmetrically arranged with respect to said power supply line. 2. The semiconductor memory device according to 1. 6. The transistor according to claim 1, wherein the transistor constituting the memory cell is a MOS transistor.
13. The semiconductor memory device according to claim 1. 7. A MOS transistor forming first and second memory cell arrays arranged adjacent to the power supply line, and M transistors forming corresponding portions of the cells.
A gate electrode of the OS transistor is arranged adjacent to the power supply line, and a distance between the gate electrode and the dummy wiring region is such that the distance between the gate electrode and the gate electrode of the MOS transistor in the cell is substantially uniform. 7. The semiconductor memory device according to claim 6, wherein: