JPH054750B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to a drive device for an optical pickup used in a CD (compact disc) playback device, and particularly relates to a drive device for an optical pickup used in a CD (compact disc) playback device. The present invention relates to a driving device for an optical pickup, which stops the operation of the driving device when a certain number of errors are included.

(b) Prior art On pages 133 to 138 of the "Illustrated Compact Disc Reader" published on June 20, 1985,
A tracking servo mechanism for a CD playback device is described. This tracking servo mechanism
As shown in the figure, an optical pickup 101 optically detects a signal written on a CD, an error detection circuit 102 generates a tracking error signal using the output signal of the pickup 101, and an error detection circuit 102 generates a tracking error signal using the output signal of the pickup 101. It includes an amplifier circuit 103 for amplifying, a tracking coil 104 for partially driving the pickup 101 to adjust tracking, and a feed motor 105 for driving the entire pickup 101 in the radial direction of the CD to adjust tracking. ing. Normally, during CD playback, the tracking coil 104 is operated in response to the error signal output from the error detection circuit 102 to perform tracking adjustment, and the feed motor 1
05 is operated to move the optical pickup in the radial direction of the CD.

Furthermore, in the CD system, in order to correct errors in information, CIRC (cross-interleaved Reed-Solomon code) is used to record and reproduce information. The signal recorded on a CD is
A 28-block Reed-Solomon code is created by adding 4-block correction code (Q parity) to a 24-block signal with 8 bits as one block.
It is created by interleaving the 28 blocks of Reed-Solomon codes and then adding 4 blocks of correction code (P parity) to create a 32-block Reed-Solomon code. Therefore, in the playback device, it is necessary to decode the signal read from the CD (32-block Reed-Solomon code) in the reverse order of recording to obtain the original information. Decoding in a playback device is usually performed by calculating syndromes. In this case, a check ( _C1 check) using P parity is first performed, and error correction for up to two blocks is performed. Therefore, in _C1 check,
"No error", "1 error correction", "2 error correction",
Four types of results are obtained: "Uncorrectable." C ₁
The checked signal is deinterleaved in the opposite manner to that during recording, converted into a 28-block Reed-Solomon code, and then subjected to a check using Q parity ( _C2 check). In that case as well, up to two blocks of error correction are performed, so just like the _C1 check, four types of results can be obtained: "No error", "1 error correction", "2 error correction", and "uncorrectable". . For information on correcting this error, please refer to the above-mentioned "Illustrated Compact Disc Reader" No. 103.
Detailed information is provided on pages 110 to 110.

(c) Problems to be solved by the invention However, dust and dirt may adhere to the CD,
If the CD becomes eccentric, the optical pickup 1
01 cannot be normally picked up, and the output error signal of the error detection circuit 102 becomes large. Furthermore, the number of times that "correction is not possible" occurs in the error correction circuit also increases. Then, the error detection circuit 102
When the output error signal of the feed motor 10 becomes large,
If the feeding state of the optical pickup 101 caused by the optical pickup 5 is abnormal and is severe, skating of the optical pickup 101 will occur.

(d) Means for solving the problem The present invention has been made in view of the above-mentioned points, and utilizes the fact that the tracking error state and the correction state of the correction circuit have a correlation. a signal generation circuit that generates a corresponding signal, a latch circuit that latches the signal, a first conversion circuit that converts the output signal of the latch circuit into a pulse train, and a first conversion circuit that converts the output pulse train of the conversion circuit into a DC voltage. 2 conversion circuit and a level detection circuit for detecting the level of the DC voltage, and the drive of the optical pickup is stopped by the output signal of the level detection circuit.

(E) Effect According to the present invention, a pulse train generated according to the correction state of the error correction circuit is converted into a DC voltage, and when the DC voltage exceeds a predetermined value, an optical pickup is sent in the radial direction of the CD. Since the feeding operation is stopped, abnormal feeding of the optical pickup can be prevented.

(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention.
106 is an error correction circuit for correcting errors in the signal picked up by the optical pickup 101;
107 outputs an "H" signal to the first output terminal when the error correction circuit 106 corrects one error;
When error correction is performed, “H” is output to the second output terminal.
a signal generating circuit that generates an "H" signal at a third output terminal when the signal becomes uncorrectable;
08 is a latch circuit that latches the output signal of the signal generation circuit 107, 109 is a first conversion circuit that generates a pulse train according to the output signal of the latch circuit 108, and 110 is a DC converter for the output signal of the first conversion circuit 109. A second conversion circuit converts the voltage into a voltage, and a level detection circuit 111 detects the level of the output DC voltage of the second conversion circuit 110 and stops the feed operation of the feed motor 105. In addition, in Figure 1,
Circuits that are the same as those in FIG. 2 are denoted by the same reference numerals, and explanations thereof will be omitted.

If the optical pickup 101 is picking up signals normally, the output of the error detection circuit 102 for detecting a tracking error is generated normally, and after being amplified by the amplifier circuit 103, the output is output from the tracking coil 104 and It is applied to the feed motor 105. Therefore, optical pickup 101 is a CD
accurately follow the track. Further, the information signal in the output signal of the optical pickup 101 is corrected by CIRC in the error correction circuit 106.
At that time, a signal indicating the correction state of the error correction circuit 106 is generated from the signal generation circuit 107 and latched by the latch circuit 108.
The output signal is converted into a pulse train by the first conversion circuit 109. In that case, if 1 error correction is performed, a pulse train containing 1 pulse within a predetermined time will be processed, and if 2 error correction is performed, a pulse train containing 2 pulses will become 3 pulses when it becomes uncorrectable. Since a pulse train including the number of pulses is generated, a DC voltage corresponding to the number of pulses included in the pulse train is generated at the output terminal of the second conversion circuit 110. Then, since the level of the DC voltage is detected by the level detection circuit 111, correction becomes impossible, and when the level of the DC voltage becomes large, an output signal is generated from the level detection circuit 111, and the feed motor 105 operates. to stop.

FIG. 3 shows a specific circuit example of the latch circuit 108 and the first and second conversion circuits 109 and 110. In FIG. 3, 1 is an error correction circuit;
2 is an "H" signal to the output terminal 1E when the error correction circuit 1 has corrected one error, an "H" signal to the output terminal 2E when it has corrected two errors, and a "H" signal to the output terminal 2E when correction is no longer possible. "H" to output terminal NG
Signal generation circuits for generating signals, 3 to 5
6 to 8 are first to third latch circuits that hold the results of the C ₁ check obtained from the signal generation circuit 2, and fourth to sixth latch circuits 6 to 8 hold the results of the C ₂ check obtained from the signal generation circuit 2. Latch circuit, 9
10 is a first pulse generation circuit that generates a pulse train according to the output signals of the first to third latch circuits 3 to 5, and 10 is the fourth to sixth latch circuits 6 to 8.
11 is a NOR gate that allows the outputs of the first and second pulse train generation circuits 9 and 10 to pass through; 12 is a flip-flop circuit that is set by the output of the NOR gate 11; , and 13 are low-pass filters for smoothing the output pulses of the flip-flop circuit 12.

Here, the timing signal will be explained. The operation for error correction is performed at six timings, as shown in FIG. T ₁ in Figure 4
The _C1 check signal is read into the error correction circuit 1 at the timing of , the C1 syndrome is calculated at the timing of _T2 , and the _C1 syndrome is calculated at the timing of _T3 .
C ₁ error correction is performed. Similarly, the _C2 check signal is read into the error correction circuit 1 at the timing _T4 , the C2 syndrome is calculated at the timing _T5 , and _{the C2} error correction is performed at the timing _T6 . Then, at the timing _T2 , the result of the number of _C1 error corrections is obtained, and at the timing _T5 , the result of the number of _C2 error corrections is obtained. still,
In order to determine each timing, timing signals shown in FIG. 5 _T1 to _T6 are generated.

In the present invention, the T ₁ to T ₆ timing signals that determine the operation timing of the error correction circuit 1 are used to generate a pulse train according to the error correction state. As mentioned earlier, since the result of the number of _C1 error corrections is obtained at the timing of _T2 , by applying the next timing signal _T3 to the AND gate 14, the _C1 check output from the signal generation circuit 2 can be corrected. The results are sent to the first to third latch circuits 3 to 5.
It can be kept in In that case, if the result of the _C1 check is "1 error correction", the output of the third latch circuit 5 becomes "H", and if the result of "2 error correction", the output of the second latch circuit 4 becomes "H". Become,
If it is "uncorrectable", the output of the third latch circuit 3 becomes "H". If the result of the _C1 check is "1 error correction", the output of the third latch circuit 5 becomes "H" and is applied to one input of the NAND gate 16 via the NOR gate 15. Therefore, when the timing signal _T6 is applied from the terminal 17, the output of the NAND gate 16 becomes "H", the output of the NOR gate 18 becomes "L", the output of the NOR gate 11 becomes "H", and the flip-flop circuit 12
is set. The reset signal of the flip-flop circuit 12 applied to the terminal 19 is generated at approximately the middle position of each timing, so when the result of the _C1 check is "1 error correction", the reset signal of the flip-flop circuit 12 is applied to the terminal 19. The output is generated as shown in FIG. 6A. If the result of the _C1 check is "2 error correction", the output of the second latch circuit 4 becomes "H" and the outputs of the NOR gates 20 and 15 become "L". Therefore, when the timing signal _T5 is applied from the terminal 21, the NAND gate 22
The output of the NOR gate 18 is "H", the output of the NOR gate 18 is "L",
The output of NOR gate 11 becomes "H", flip-flop circuit 12 is set, and then reset by application of a reset signal. Furthermore, by applying the timing signal _T6 , the flip-flop circuit 12 is set as in the case of "1 error correction". Therefore, the signal shown in FIG. 6B is generated at the output terminal of the flip-flop circuit 12. If the result of _C1 check is "uncorrectable", then
The output of the first latch circuit 3 becomes "H", and the outputs of the inverter 23 and NOR gates 20 and 15 all become "L". Therefore, when the timing signal _T4 is applied from the terminal 24, the output of the NAND gate 25 becomes "H", the output of the NOR gate 18 becomes "L", the output of the NOR gate 11 becomes "H", and the flip-flop circuit 12 is set. Ru. Similarly, flip-flop circuit 12 is set by applying timing signal _T5 , and flip-flop circuit 12 is set by applying timing signal _T6 .
Therefore, the signal shown in FIG. 6C is generated at the output terminal of the flip-flop circuit 12.

On the other hand, since the result of the number of _C2 error corrections is obtained at the timing _T5 , by applying the next timing signal _T6 to the AND gate 26, the result of the _C2 check output from the signal generation circuit 2 is outputted at the fourth timing. It can be held in the sixth to sixth latch circuits 6 to 8. In that case, if the result of _C2 check is "1 error correction", the output of the sixth latch circuit 8 will be "H".
If it is "2 error correction", the output of the fifth latch circuit 7 becomes "H", and if "correction is not possible", the output of the fourth latch circuit 6 becomes "H". Fourth
Similarly to the first to third latch circuits 3 to 5, the outputs of the sixth to sixth latch circuits 6 to 8 set the flip-flop circuit 12 in accordance with the timing signals T ₁ , T ₂ and T ₃ , but the operation thereof is as follows. , first to third
As in the case of latch circuits 3 to 5, the description is omitted and only the results will be shown below. First, if the result of the _C2 check is "1 error correction", the output "H" of the sixth latch circuit 8 is applied to the flip-flop circuit 12 in accordance with the timing signal _T3 , and the output of the flip-flop circuit 12 is occurs as shown in Figure 4D. Further, if the result of the _C2 check is "2 error correction", the output "H" of the fifth latch circuit 7 is applied to the flip-flop circuit 12 in accordance with the timing signals _T2 and _T3 , and the flip-flop circuit 12 outputs are generated as shown in FIG.
Furthermore, if the result of the _C2 check is "uncorrectable", the output "H" of the fourth latch circuit 6 is applied to the flip-flop circuit 12 in accordance with the timing signals _T1 , _T2 and _T3 , and the corresponding The output of the flip-flop circuit 12 is generated as shown in FIG. Note that the AND gates 14 and 26, like the NAND gates 28 to 33, operate in accordance with the timing clock applied to the terminal 27.

Therefore, if the circuit of FIG. 3 is used, one of the circuits A to C of FIG. 6 and one of the circuits D to C of FIG. It is possible to obtain an output pulse train corresponding to the correction state of the error correction circuit 1 in combination with one of the above, and by smoothing the output signal of the flip-flop circuit 12 with the low-pass filter 13, the correction state of the error correction circuit 1 can be obtained. It is possible to obtain the appropriate DC voltage. The DC voltage reaches a very high level when a state in which the results of the C ₁ and C ₂ checks become "uncorrectable" occurs continuously.

FIG. 7 is a specific circuit example showing a drive circuit for the level comparison circuit 111, the tracking coil 104, and the feed motor 105. Output terminal 34 in Figure 3
The DC voltage obtained is applied to the input terminal 35 and compared with a reference voltage in the comparison circuit 36. When the level of the DC voltage is low, no output is generated from the comparison circuit 36 and the control transistor 37 is turned off. Therefore, the tracking error signal generated from the first amplifier circuit 38 is transmitted to the tracking coil 1.
04 as well as the second amplifier circuit 39, the tracking coil 104
Then, the feed motor 105 is driven, and tracking servo is performed. Note that the feed motor 105 is also controlled by a control signal applied to the terminal 40 from the microcomputer. Therefore, in order to initialize or track jump the optical pickup, a control signal may be applied to the terminal 40.

Now, in response to the result of "uncorrectable", the level of the DC voltage applied to the input terminal 35 increases and exceeds the reference voltage of the comparator circuit 36, the output of the comparator circuit 36 becomes "H", and the control Transistor 37 is turned on. Therefore, the first amplifier circuit 3
8 is cut off by the control transistor 37, and the output of the motor 10 is cut off by the tracking error signal.
5 control is no longer performed. Therefore, abnormal feeding of the optical pickup is prevented. The DC voltage applied to the input terminal 35 changes linearly depending on the error correction state. Therefore, the error correction state can be detected with high precision using the DC voltage.
In conjunction with setting the reference voltage, control of the feed motor with a high degree of freedom is achieved.

(G) Effects of the Invention As described above, according to the present invention, when the error correction circuit becomes in a state where the result is "uncorrectable", the feed operation of the feed motor is stopped. Abnormal feeding of optical pickup can be prevented. Further, according to the present invention, since the signal indicating the error correction state is converted into a pulse train and then converted into a DC voltage, it is possible to reduce the number of terminal pins when integrating the circuit. Furthermore, according to the present invention, it is possible to obtain a DC voltage that accurately indicates the error correction state, and the cutoff level of the tracking servo can be set simply by setting the threshold level of the comparator circuit, which increases the degree of freedom in design. can provide a driving device for a large optical pickup.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional optical pickup driving device, FIG. 3 is a circuit diagram showing a specific example of the circuit shown in FIG. 1, and FIG. 5, and 6 are waveform diagrams for explaining the operation, and FIG. 7 is a circuit diagram showing another specific example of the circuit shown in FIG. 1. 106...Error correction circuit, 107...Signal generation circuit, 108...Latch circuit, 109...First
Conversion circuit, 110... Second conversion circuit, 111...
Level comparison circuit.

Claims (1)

[Claims] 1. In an optical pickup driving device that drives an optical pickup in response to a tracking error signal and correctly sets the relative position between the disk and the optical pickup, one error output and two error outputs are output depending on the correction state of the error correction circuit. A signal generation circuit that generates an error output and an uncorrectable output, a latch circuit that latches each of the signals, a first conversion circuit that converts the output signal of the latch circuit into a number of pulse trains corresponding to the output signal, and the first conversion circuit. a second conversion circuit that converts the output pulse train of the second conversion circuit into a DC voltage, and a level detection circuit that detects the level of the DC voltage obtained from the second conversion circuit. 1. A drive device for an optical pickup, characterized in that driving of the optical pickup is stopped when the value exceeds a predetermined value.