JPH0546693A - Circuit diagram generation system - Google Patents
Circuit diagram generation systemInfo
- Publication number
- JPH0546693A JPH0546693A JP3207663A JP20766391A JPH0546693A JP H0546693 A JPH0546693 A JP H0546693A JP 3207663 A JP3207663 A JP 3207663A JP 20766391 A JP20766391 A JP 20766391A JP H0546693 A JPH0546693 A JP H0546693A
- Authority
- JP
- Japan
- Prior art keywords
- circuit diagram
- circuit
- signal name
- symbol
- wire bound
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は回路図発生方式に関し、
特に指定部のみの回路に対応する回路図を発生する方式
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit diagram generation system,
In particular, it relates to a method of generating a circuit diagram corresponding to a circuit having only a designated portion.
【0002】[0002]
【従来の技術】従来、指定部の回路図を得る場合は、回
路図上でその部分だけをトレースするか、回路図エディ
タ上で不用な部分を人手で削除するようにしている。2. Description of the Related Art Conventionally, when obtaining a circuit diagram of a designated portion, only that portion is traced on the circuit diagram, or an unnecessary portion is manually deleted on the circuit diagram editor.
【0003】[0003]
【発明が解決しようとする課題】上述した従来の回路図
発生方式では、指定部の回路が切り離されていないた
め、回路のトレースが困難であり、指定部のみの回路を
切り離そうとする莫大な工数を要するという欠点があっ
た。In the above-described conventional circuit diagram generation method, since the circuit of the designated portion is not separated, it is difficult to trace the circuit, and it is enormous to try to separate the circuit of only the designated portion. There was a drawback that it required a lot of man-hours.
【0004】[0004]
【課題を解決するための手段】本発明の回路図発生方式
は、回路図情報全体を入力する入力手段と、必要とする
回路の一部に含まれる信号名を指定する信号名指定手段
と、指定されていない信号名に相当する回路図上の結線
を削除する結線削除手段と、結線の無くなったシンボル
を削除するシンボル削除手段と、指定部のみの回路図を
出力する出力手段とを有することを特徴とする。The circuit diagram generation system of the present invention comprises an input unit for inputting the entire circuit diagram information, a signal name designating unit for designating a signal name included in a part of a required circuit, It has a connection deletion means for deleting the connection on the circuit diagram corresponding to the unspecified signal name, a symbol deletion means for deleting the symbol with no connection, and an output means for outputting the circuit diagram of only the specified part. Is characterized by.
【0005】[0005]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【0006】図1は本発明の一実施例の構成図である。FIG. 1 is a block diagram of an embodiment of the present invention.
【0007】入力手段2は論理回路図情報1を入力し、
信号名指定手段3はトレースが必要な部分の回路に含ま
れる信号の信号名を指定し、結線削除手段4に渡す。The input means 2 inputs the logic circuit diagram information 1,
The signal name designating means 3 designates the signal name of the signal included in the circuit of the portion where tracing is required, and passes it to the connection deleting means 4.
【0008】結線削除手段4は、入力された回路図情報
中で指定されている信号名に対応する結線を削除し、シ
ンボル削除手段5は接続を持たないシンボルを削除す
る。出力手段7は以上の回路図情報を論理回路図情報7
として出力する。The connection deleting means 4 deletes the connection corresponding to the signal name specified in the input circuit diagram information, and the symbol deleting means 5 deletes the symbols having no connection. The output means 7 converts the above circuit diagram information into the logic circuit diagram information 7
Output as.
【0009】図2〜図4は本実施における回路図情報の
変化を示している。2 to 4 show changes in circuit diagram information in this embodiment.
【0010】図2は初期回路の回路図情報であり、図3
は図2からCLK+……という信号名に対応する結線を
削除した回路図情報であり、図4は未接続のシンボルを
削除した回路図情報である。FIG. 2 is circuit diagram information of the initial circuit, and FIG.
2 is circuit diagram information in which connection lines corresponding to the signal name CLK + ... Are deleted from FIG. 2, and FIG. 4 is circuit diagram information in which unconnected symbols are deleted.
【0011】[0011]
【発明の効果】以上説明したように本発明は、全体回路
の指定部のみの回路に対応する回路図を自動的に発生す
ることにより必要部分の回路のトレースが容易になると
いう効果がある。As described above, the present invention has the effect of facilitating the tracing of the necessary parts of the circuit by automatically generating the circuit diagram corresponding to the circuit of only the designated part of the whole circuit.
【図1】図1は本発明の構成図である。FIG. 1 is a block diagram of the present invention.
【図2】図1に示した実施例を設定するための初期回路
の回路図情報例を示す。FIG. 2 shows an example of circuit diagram information of an initial circuit for setting the embodiment shown in FIG.
【図3】図2に示す回路図情報のうちの一部の信号名に
対応する結線を削除した回路図情報を示す。FIG. 3 shows circuit diagram information in which connection lines corresponding to some signal names in the circuit diagram information shown in FIG. 2 are deleted.
【図4】図3に示う回路図情報から、結線が削除された
シンボルを削除した回路図情報を示す。FIG. 4 shows circuit diagram information obtained by deleting the symbols whose connection is deleted from the circuit diagram information shown in FIG.
1 論理回路図情報 2 入力手段 3 信号名指定手段 4 結線削除手段 5 シンボル削除手段 6 出力手段 7 論理回路図情報 1 Logic Circuit Diagram Information 2 Input Means 3 Signal Name Designating Means 4 Connection Deleting Means 5 Symbol Deleting Means 6 Output Means 7 Logic Circuit Diagram Information
Claims (1)
名指定手段と、 指定されていない信号名に相当する回路図上の結線を削
除する結線削除手段と、 結線の無くなったシンボルを削除するシンボル削除手段
と、 指定部のみの回路図を出力する出力手段とを有すること
を特徴とする回路図発生方式。1. An input means for inputting the whole circuit diagram information, a signal name designating means for designating a signal name included in a part of a required circuit, and a circuit diagram corresponding to a signal name not designated. A circuit diagram generation method comprising: a connection deletion unit for deleting a connection; a symbol deletion unit for deleting a symbol with no connection; and an output unit for outputting a circuit diagram of only a designated section.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3207663A JPH0546693A (en) | 1991-08-20 | 1991-08-20 | Circuit diagram generation system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3207663A JPH0546693A (en) | 1991-08-20 | 1991-08-20 | Circuit diagram generation system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0546693A true JPH0546693A (en) | 1993-02-26 |
Family
ID=16543499
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3207663A Pending JPH0546693A (en) | 1991-08-20 | 1991-08-20 | Circuit diagram generation system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0546693A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08180090A (en) * | 1994-12-26 | 1996-07-12 | Nec Corp | Wiring display system for multilayer printed circuit board |
-
1991
- 1991-08-20 JP JP3207663A patent/JPH0546693A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08180090A (en) * | 1994-12-26 | 1996-07-12 | Nec Corp | Wiring display system for multilayer printed circuit board |
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