JPH0545078B2 - - Google Patents

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Publication number
JPH0545078B2
JPH0545078B2 JP62000654A JP65487A JPH0545078B2 JP H0545078 B2 JPH0545078 B2 JP H0545078B2 JP 62000654 A JP62000654 A JP 62000654A JP 65487 A JP65487 A JP 65487A JP H0545078 B2 JPH0545078 B2 JP H0545078B2
Authority
JP
Japan
Prior art keywords
layer
type
conductivity type
mesa portion
striped mesa
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62000654A
Other languages
Japanese (ja)
Other versions
JPS63169085A (en
Inventor
Tomoki Murakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP65487A priority Critical patent/JPS63169085A/en
Publication of JPS63169085A publication Critical patent/JPS63169085A/en
Publication of JPH0545078B2 publication Critical patent/JPH0545078B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体レーザに関し、特に2重チヤネ
ル型プレーナ埋込み構造半導体レーザに関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor lasers, and more particularly to dual-channel planar buried structure semiconductor lasers.

〔従来の技術〕[Conventional technology]

第2図に示す従来の2重チヤネル型プレーナ埋
込み構造半導体レーザは、InPからなるN型半導
体基板1上にInPからなるN型クラツド層2、
InGaAsPからなる活性層3、InPからなるP型ク
ラツド層4をエピタキシヤル成長させたのち、1
対の溝11を形成し、さらに溝11ではさまれた
ストライプ状メサ部12上を除く表面にInPから
なるP型ブロツク層6、InPからなるノンドープ
層7、InPからなるN型ブロツク層8を形成し、
しかるのち、表面全面にInPからなるP型半導体
層9、P型InGaAsPからなるキヤツプ層10を
形成した構造を有していた。したがつて、P型半
導体層9、N型ブロツク層8、P型ブロツク層
6、N型クラツド層2はPNPNサイリスタを構
成することとなり、電流の流れを阻止する効果が
あり、これにより、電流を活性層発光部(ストラ
イプ状メサ部の活性層3)に有効に注入すること
ができる。さらに、溝領域外では、禁制帯幅の小
さい活性層3が、P型クラツド層4との間にポテ
ンシヤルの障壁を作り、N型クラツド層2よりP
型クラツド層4へ注入される電子の割合を低減化
し、サイリスタのターンオンがしずらくなつてい
る。
The conventional dual-channel planar buried structure semiconductor laser shown in FIG. 2 includes an N-type semiconductor substrate 1 made of InP, an N-type cladding layer 2 made of InP,
After epitaxially growing the active layer 3 made of InGaAsP and the P-type cladding layer 4 made of InP, 1
A pair of grooves 11 are formed, and a P-type block layer 6 made of InP, a non-doped layer 7 made of InP, and an N-type block layer 8 made of InP are formed on the surface except for the striped mesa portion 12 sandwiched between the grooves 11. form,
Thereafter, a P-type semiconductor layer 9 made of InP and a cap layer 10 made of P-type InGaAsP were formed over the entire surface. Therefore, the P-type semiconductor layer 9, the N-type block layer 8, the P-type block layer 6, and the N-type cladding layer 2 constitute a PNPN thyristor, which has the effect of blocking the flow of current. can be effectively injected into the active layer light emitting part (the active layer 3 in the striped mesa part). Furthermore, outside the trench region, the active layer 3 with a small forbidden band width creates a potential barrier between the active layer 3 and the P-type cladding layer 4, and the
The proportion of electrons injected into the type cladding layer 4 is reduced, making it difficult to turn on the thyristor.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

第2図に示す従来素子では、溝11領域中では
禁制帯幅の小さな活性層3は形成されておらず、
N型クラツド層2よりP型ブロツク層6への電子
の注入は比較的容易に行われ得る。したがつて、
従来素子ではレーザ発振後印加電圧を増加させる
に従い、第2図に示す活性層発光部以外を流れる
いわゆる漏れ電流のうち溝11において、P型半
導体層9、N型ブロツク層8、ノンドープ層7、
P型ブロツク層6及びN型クラツド層2を通つて
流れる電流が増加してしまい、すなわち、P型半
導体層9よりP型クラツド層4のうちのストライ
プ状メサ部12を通り、P型ブロツク層6へ流入
する電流がPNPNサイリスタのゲート電流とし
て働き、印加電圧を増加させたとき、9,8,
6,2で構成されるサイリスタがターンオンして
しまい漏れ電流が増加した。この結果、素子の微
分量子効率が悪化してしまう不具合が生じた。
In the conventional device shown in FIG. 2, the active layer 3 with a small forbidden band width is not formed in the groove 11 region.
Injection of electrons from the N-type cladding layer 2 to the P-type blocking layer 6 can be performed relatively easily. Therefore,
In the conventional element, as the applied voltage is increased after laser oscillation, the P-type semiconductor layer 9, the N-type block layer 8, the non-doped layer 7,
The current flowing through the P-type block layer 6 and the N-type cladding layer 2 increases, that is, the current flowing through the P-type semiconductor layer 9 passes through the striped mesa portion 12 of the P-type cladding layer 4, and the current flows through the P-type block layer 6. When the current flowing into 6 acts as the gate current of the PNPN thyristor and increases the applied voltage, 9, 8,
The thyristor composed of 6 and 2 was turned on and the leakage current increased. As a result, a problem occurred in that the differential quantum efficiency of the device deteriorated.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の2重チヤネル型ブレーナ埋込み構造半
導体レーザは、第1導電型半導体基板上に第1導
電型クラツド層、活性層および第2導電型クラツ
ド層の少なくとも3層が順次に積層された多層膜
基板の表面に少なくとも前記活性層を突き抜ける
深さの互いに平行な1対の溝が形成されてなるス
トライプ状メサ部、前記ストライプ状メサ部の表
面を除く部分に順次に積層して設けられた、前記
活性層より禁制帯幅の大きい第2導電型障壁層お
よび第1導電型障壁層と、前記各クラツド層の少
なくともいずれか一方と同じ半導体からなる第2
導電型ブロツク層及び第1導電型ブロツク層と、
前記ストライプ状メサ部表面及び前記第1導電型
ブロツク層表面を覆う第2導電型半導体層とを含
み、前記第2導電型ブロツク層が前記ストライプ
状メサ部で前記第2導電型クラツド層に接して設
けられ、前記ストライプ状メサ部に選択的に電流
を注入するようにしたものである。
The double-channel type buried-brainer structure semiconductor laser of the present invention is a multilayer film in which at least three layers, a first conductivity type cladding layer, an active layer, and a second conductivity type cladding layer, are sequentially laminated on a first conductivity type semiconductor substrate. a striped mesa portion in which a pair of mutually parallel grooves having a depth penetrating at least the active layer are formed on the surface of the substrate; a portion of the striped mesa portion excluding the surface thereof is provided in a sequentially laminated manner; a second conductivity type barrier layer and a first conductivity type barrier layer having a larger band gap than the active layer; and a second conductivity type barrier layer made of the same semiconductor as at least one of the cladding layers.
a conductive type block layer and a first conductive type block layer;
a second conductivity type semiconductor layer covering a surface of the striped mesa portion and a surface of the first conductivity type block layer, wherein the second conductivity type block layer is in contact with the second conductivity type cladding layer at the striped mesa portion. A current is selectively injected into the striped mesa portion.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して
説明する。
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の実施例に関連する2重チヤネ
ル型プレーナ埋込み構造半導体レーザの主要部を
示す半導体チツプの断面図である。
FIG. 1 is a sectional view of a semiconductor chip showing the main parts of a dual channel type planar buried structure semiconductor laser related to an embodiment of the present invention.

この2重チヤネル型プレーナ埋込み構造半導体
レーザは、InPからなるN型半導体基板1上に積
層され、InPからなるN型クラツド層2、ノンド
ープin0.65Ga0.35As0.79P0.21からなる活性層3及び
InPからなるN型クラツド層4を少なくとも含む
ヘテロ接合構造体の表面に設けられ活性層3より
深い1対の溝11で挟まれたストライプ状メサ部
12の表面を除く部分に設けられた、活性層3よ
り禁制帯幅の大きいN型In0.76Ga0.24As0.55P0.45
らなる障壁層5、各クラツド層2,3と同じInP
からなるP型ブロツク層8及びN型ブロツク層8
と、ストライプ状メサ部12表面及びN型ブロツ
ク層8表面を覆うP型半導体層9とを含み、スト
ライプ状メサ部12に選択的に電流を注入するよ
うにしたものである。
This double channel type planar buried structure semiconductor laser is laminated on an N-type semiconductor substrate 1 made of InP, an N-type cladding layer 2 made of InP, an active layer 3 made of non-doped in 0.65 Ga 0.35 As 0.79 P 0.21 , and
An active active layer is provided on the surface of the heterojunction structure including at least the N-type cladding layer 4 made of InP, except for the surface of the striped mesa portion 12, which is sandwiched between a pair of grooves 11 deeper than the active layer 3. Barrier layer 5 is made of N-type In 0.76 Ga 0.24 As 0.55 P 0.45 , which has a larger forbidden band width than layer 3, and InP is the same as each cladding layer 2 and 3.
P-type block layer 8 and N-type block layer 8 consisting of
and a P-type semiconductor layer 9 covering the surface of the striped mesa portion 12 and the surface of the N-type block layer 8, and current is selectively injected into the striped mesa portion 12.

次に、この2重チヤネル型プレーナ埋込み構造
半導体レーザの製造方法について説明する。
Next, a method for manufacturing this double channel type planar buried structure semiconductor laser will be explained.

まずInPからなるN型半導体基板1上に、厚さ
3μm、不純物濃度5×1017cm-3のN型InP層2、
厚さ0.1μmのノンドープIn0.65Ga0.35As0.79P0.21
3、厚さ1μm、不純物濃度1×1018cm-3のP型
InP層4を形成したのち活性層3の位置よりも深
い1対の深さ4μm、幅8μmの溝11を形成し、
さらに1対の溝11ではさまれた幅1.5μmのスト
ライプ状メサ部12上と、溝11のうち活性層3
の位置より上方の領域を除いた表面に厚さ1μm、
不純物濃度1×1018cm-3のN型In0.76Ga0.24As0.55
P0.45層5を形成したのち、ストライプ状メサ部1
2上を除く厚さ1μm、不純物濃度1×1018cm-3
P型InP層6、厚さ0.5μmのノンドープInP層7、
厚さ1.1μm、不純物濃度1×1018cm-3のN型InP
層8を形成し、しかるのち、表面全面にP型InP
層9、P型InGaAsP層10を形成する。
First, on an N-type semiconductor substrate 1 made of InP, a thickness of
N-type InP layer 2 with a thickness of 3 μm and an impurity concentration of 5×10 17 cm -3 ;
Non-doped In 0.65 Ga 0.35 As 0.79 P 0.21 layer 3 with a thickness of 0.1 μm, P type with a thickness of 1 μm and an impurity concentration of 1×10 18 cm -3
After forming the InP layer 4, a pair of grooves 11 with a depth of 4 μm and a width of 8 μm deeper than the position of the active layer 3 are formed,
Furthermore, the active layer 3 is placed on the striped mesa portion 12 with a width of 1.5 μm sandwiched between the pair of grooves 11, and on the active layer 3 of the grooves 11.
1 μm thick on the surface excluding the area above the position.
N-type In 0.76 Ga 0.24 As 0.55 with impurity concentration 1×10 18 cm -3
After forming P 0.45 layer 5, striped mesa part 1
A P-type InP layer 6 with a thickness of 1 μm and an impurity concentration of 1×10 18 cm -3 excluding the top layer 2, a non-doped InP layer 7 with a thickness of 0.5 μm,
N-type InP with a thickness of 1.1 μm and an impurity concentration of 1×10 18 cm -3
Layer 8 is formed, and then P-type InP is formed on the entire surface.
A layer 9 and a P-type InGaAsP layer 10 are formed.

この2重チヤネル型プレーナ埋込み構造半導体
レーザは、活性層3より禁制帯幅の大きい障壁層
5が溝11領域に設けられているのでN型クラツ
ド層2よりP型ブロツク層6へ注入される電子の
割合がヘテロ接合面におけるポテンシヤル不連続
の存在により従来例より少なくなり、溝11領域
中でのサイリスタのターンオン電流を抑えること
により、9,8,7,6,5,2を通つて流れる
漏れ電流は従来例の1/3以下に低減される。又、
4,6,5,2を通つて流れる漏れ電流(溝の外
側から溝内へ流れ込む電流)は障壁層5の禁制帯
幅が活性層より大きく光の吸収がないので殆んど
変らない。このように漏れ電流が少なくなる結
果、外部微分量子効率η(%)は従来例のものη0
(%)に比べ5%以上の向上した(η≧η0+5)。
In this double channel type planar buried structure semiconductor laser, since the barrier layer 5 having a larger forbidden band width than the active layer 3 is provided in the trench 11 region, electrons are injected from the N-type cladding layer 2 into the P-type blocking layer 6. The proportion of leakage flowing through 9, 8, 7, 6, 5, 2 is reduced by suppressing the turn-on current of the thyristor in the groove 11 region. The current is reduced to less than 1/3 of the conventional example. or,
The leakage current flowing through 4, 6, 5, and 2 (current flowing into the trench from outside the trench) hardly changes because the forbidden band width of the barrier layer 5 is larger than that of the active layer and there is no absorption of light. As a result of this reduction in leakage current, the external differential quantum efficiency η (%) is lower than that of the conventional example η 0
(%), an improvement of 5% or more (η≧η 0 +5).

第3図は本発明の一実施例の主要部を示す半導
体チツプの断面図である。
FIG. 3 is a sectional view of a semiconductor chip showing the main parts of an embodiment of the present invention.

この実施例は、溝11の深さが4.4μm、障壁層
の厚さ0.7μm、不純物濃度1×1018cm-3のIn0.76
Ga0.24As0.55P0.45からなるN型障壁層5aと厚さ
0.7μm、不純物濃度1×1018cm-3のIn0.76Ga0.24
As0.55P0.45からなるP型障壁層5bとからなつて
いる以外は第1の実施例と同じである。したがつ
て、P型InP層6、N型InGaAsP層5a、P型
InGaAsP層5b、N型InP層2はPNPNサイリス
タを構成することとなり、P型InP層4から上述
のPNPNサイリスタを構成する各成長層を通つ
て流れる漏れ電流は従来素子の1/5以下となつた。
一方、P型InP層9、N型InP層8、ノンドープ
InP層7、P型InP層6、N型InGaAsP層5a、
P型InGaAsP層5b、N型InP層2を通つて流れ
る漏れ電流は、PNPNPN接合を流れること及び
P型InP層6とN型InGaAsP層5bとのポテンシ
ヤル障壁の効果により、従来素子の1/5以下とな
つた。この結果、本実施例の素子の外部微分量子
効率は従来素子に比べ8%以上の向上(η≧η0
8)を実現できた。
In this example, the depth of the groove 11 is 4.4 μm, the thickness of the barrier layer is 0.7 μm, and the impurity concentration is In 0.76 of 1×10 18 cm -3 .
N-type barrier layer 5a consisting of Ga 0.24 As 0.55 P 0.45 and its thickness
In 0.76 Ga 0.24 with impurity concentration of 1×10 18 cm -3
The second embodiment is the same as the first embodiment except that it includes a P-type barrier layer 5b made of As 0.55 P 0.45 . Therefore, the P-type InP layer 6, the N-type InGaAsP layer 5a, the P-type
The InGaAsP layer 5b and the N-type InP layer 2 constitute a PNPN thyristor, and the leakage current flowing from the P-type InP layer 4 through each growth layer constituting the above-mentioned PNPN thyristor is less than 1/5 of that of the conventional element. Ta.
On the other hand, P-type InP layer 9, N-type InP layer 8, non-doped
InP layer 7, P-type InP layer 6, N-type InGaAsP layer 5a,
The leakage current flowing through the P-type InGaAsP layer 5b and the N-type InP layer 2 is reduced to 1/5 of that of the conventional element due to the fact that it flows through the PNPNPN junction and the effect of the potential barrier between the P-type InP layer 6 and the N-type InGaAsP layer 5b. It became the following. As a result, the external differential quantum efficiency of the device of this example is improved by more than 8% compared to the conventional device (η≧η 0 +
8) was achieved.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、溝領域中に障壁
層を挿入することにより、第2導電型ブロツク層
とのヘテロ接合によるポテンシヤル障壁を設け、
第1導電型ブロツク層より第2導電型ブロツク層
へ注入されるキヤリアの注入率を低下させること
により、漏れ電流を少なくして素子の外部微分量
子効率を向上できる効果がある。
As explained above, the present invention provides a potential barrier by a heterojunction with the second conductivity type block layer by inserting a barrier layer into the groove region,
By lowering the injection rate of carriers injected from the first conductivity type block layer into the second conductivity type block layer, leakage current can be reduced and the external differential quantum efficiency of the device can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第3図はそれぞれ本発明の実施例に
関連する2重チヤネル型プレーナ埋込み構造半導
体レーザ及び一実施例の主要部を示す半導体チツ
プの断面図、第2図は従来の2重チヤネル型プレ
ーナ埋込み構造半導体レーザの主要部を示す半導
体チツプの断面図である。 1……N型半導体基板、2……N型クラツド
層、3……活性層、4……P型クラツド層、5,
5a,5b……障壁層、6……P型ブロツク層、
7……ノンドープ層、8……N型ブロツク層、9
……P型半導体層、10……キヤツプ層、11…
…溝、12……ストライプ状メサ部。
1 and 3 are cross-sectional views of a dual-channel planar buried structure semiconductor laser and a semiconductor chip showing the main parts of one embodiment, respectively, related to an embodiment of the present invention, and FIG. 1 is a cross-sectional view of a semiconductor chip showing the main parts of a planar buried structure semiconductor laser; FIG. DESCRIPTION OF SYMBOLS 1... N-type semiconductor substrate, 2... N-type cladding layer, 3... Active layer, 4... P-type cladding layer, 5,
5a, 5b...barrier layer, 6...P type block layer,
7... Non-doped layer, 8... N-type block layer, 9
...P-type semiconductor layer, 10...cap layer, 11...
...Groove, 12...Striped mesa part.

Claims (1)

【特許請求の範囲】[Claims] 1 第1導電型半導体基板上に第1導電型クラツ
ド層、活性層および第2導電型クラツド層の少な
くとも3層が順次に積層された多層膜基板の表面
に少なくとも前記活性層を突き抜ける深さの互い
に平行な1対の溝が形成されてなるストライプ状
メサ部、前記ストライプ状メサ部の表面を除く部
分に順次に積層して設けられた、前記活性層より
禁制帯幅の大きい第2導電型障壁層および第1導
電型障壁層と、前記各クラツド層の少なくともい
ずれか一方と同じ半導体からなる第2導電型ブロ
ツク層及び第1導電型ブロツク層と、前記ストラ
イプ状メサ部表面及び前記第1導電型ブロツク層
表面を覆う第2導電型半導体層とを含み、前記第
2導電型ブロツク層が前記ストライプ状メサ部で
前記第2導電型クラツド層に接して設けられ前記
ストライプ状メサ部に選択的に電流を注入するよ
うにしたことを特徴とする2重チヤネル型プレー
ナ埋込み構造半導体レーザ。
1. On the surface of a multilayer film substrate in which at least three layers, a first conductivity type clad layer, an active layer, and a second conductivity type clad layer are sequentially laminated on a first conductivity type semiconductor substrate, a layer with a depth that penetrates at least the active layer is formed. a striped mesa portion formed by a pair of grooves parallel to each other; and a second conductivity type having a wider forbidden band width than the active layer, the striped mesa portion being sequentially laminated on a portion other than the surface of the striped mesa portion. a barrier layer and a first conductivity type barrier layer; a second conductivity type block layer and a first conductivity type block layer made of the same semiconductor as at least one of the cladding layers; a second conductive type semiconductor layer covering a surface of the conductive type block layer, the second conductive type block layer being provided in contact with the second conductive type cladding layer in the striped mesa portion and selected in the striped mesa portion. 1. A dual-channel planar buried structure semiconductor laser, characterized in that a current is injected selectively.
JP65487A 1987-01-05 1987-01-05 Double channel type planar buried structure semiconductor laser Granted JPS63169085A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP65487A JPS63169085A (en) 1987-01-05 1987-01-05 Double channel type planar buried structure semiconductor laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP65487A JPS63169085A (en) 1987-01-05 1987-01-05 Double channel type planar buried structure semiconductor laser

Publications (2)

Publication Number Publication Date
JPS63169085A JPS63169085A (en) 1988-07-13
JPH0545078B2 true JPH0545078B2 (en) 1993-07-08

Family

ID=11479702

Family Applications (1)

Application Number Title Priority Date Filing Date
JP65487A Granted JPS63169085A (en) 1987-01-05 1987-01-05 Double channel type planar buried structure semiconductor laser

Country Status (1)

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JP (1) JPS63169085A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11354886A (en) 1998-06-10 1999-12-24 Nec Corp Semiconductor laser and its manufacturing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5957486A (en) * 1982-09-27 1984-04-03 Nec Corp Buried type semiconductor laser
JPS6175585A (en) * 1984-09-20 1986-04-17 Nec Corp Buried semiconductor laser

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5957486A (en) * 1982-09-27 1984-04-03 Nec Corp Buried type semiconductor laser
JPS6175585A (en) * 1984-09-20 1986-04-17 Nec Corp Buried semiconductor laser

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JPS63169085A (en) 1988-07-13

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