JPH0542176B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field The present invention relates to an analog-to-digital converter,
In particular, the present invention relates to an automatic range switching analog-to-digital converter that automatically selects an appropriate range depending on the magnitude of an input analog signal and performs analog-to-digital conversion.

(b) Prior art and problems When using a digital computer to process the output of a gas chromatograph, etc., where the range of variation in the analog output is very wide, a fixed range analog-to-digital converter (hereinafter referred to as A- Due to constraints imposed by the number of bits used during conversion, D converters cannot perform digital conversion with sufficient accuracy depending on the output range, and must be expressed as approximate values that include an acceptable level of conversion error. There were some inconveniences.

Also, when various analog signals with various full scale values are input one after another, and these are digitized while being time-divided according to the input time,
In order to move the digital conversion accuracy to a level within a guaranteed significant figure range for each input signal, the individual gains must be switched so that the level of each input signal can be amplified commensurate with its full-case value. It was also incredibly complicated.

In order to solve these problems, various automatic range switching A-D converters have been proposed. For example, the patent application filed by the inventor of the present application
There are "automatic gain switching A-D converters" published in Japanese Patent Publication No. 005671 and "automatic range switching A-D converters" published in Japanese Patent Application Laid-open No. 53-008045. Both of these A-D converters are simple circuits. The feature was that the input range could be determined quickly.

However, in the case of conventional A-D converters, changes in the analog signal (rapid rise or fall in the positive or negative direction) after the input range determination point
For example, if there is a rise in the positive direction after the input range is determined, the analog value at the time of A-D conversion will exceed the maximum allowable value of the determined range, and the waveform will be suppressed at the upper limit. There was a risk that it would be converted from A to D. Also, if the analog signal value becomes too small in absolute value,
Due to the finite number of bits required for digital representation during A-D conversion, the number of significant digits is insufficient, and A-D conversion cannot be performed with sufficient accuracy.
It also had the disadvantage of not being able to perform D conversion.

FIG. 1 is an explanatory diagram of the principle of A-D conversion according to the prior art, and figure a shows the input range determination time of an analog sine wave, the analog amount at that determination time, and the sample time and time of the sine wave. The analog waveform showing the analog amount at , and the gain at which the analog signal should be amplified for the input range are shown. The plot waveform after conversion is shown. In the figure, 1 is an analog sine wave, 2 is a plot waveform after A-D conversion, and G1
~G4 is the gain set to the amplifier for each input range, t is the sampling time, and the time with a single digit subscript is A-
The sample time of the analog value to be D-converted and the time of the two-digit subscript indicate the sample time of the analog value for input range determination, respectively.

In the same figure a, the amplification factor of gain G is the analog quantity
When the range is 1.0 to 0.5, the gain G1 (1x) is 0.5
When the range is ~0.25, the gain G2 (2x) is 0.25
When the range is ~0.125, the gain G3 (4 times),
It is set so that the gain G4 (8 times) is obtained in the range of 0.125 to 0.0, and therefore the display range after amplification for each of them is a half scale value of 0.5.
The full scale value is 1.0.

Therefore, for example, the input range is determined at time _t11 , the gain G1 (1x) at that time is determined, and then the analog amount (0.707) at time _t2 is amplified to 1x, and then A- The input range is then determined at time _t21 , and the gain G1 (1x) at that time is
Then, the analog quantity (0.923) at time _t3 is amplified by a factor of 1, and then the A-D conversion is performed while successively determining the gain G.

Here, a problem arises when the analog amount at the sample time after the gain G is determined moves within the range of a different gain G.

In figure a, this effect appears at time _t1 and time _t7 , and as shown in figure b, waveform distortion appears at these two times.

Among these, time t ₁ is due to scale over due to excessive amplification factor, and the other time t ₇ is due to the influence of a conversion error that causes half scale due to insufficient amplification factor.

To explain in more detail, if the value of the input signal sampled at time t ₀₁ is 0.17, the range of 0.125 to 0.25, that is, the gain G3 (4 times) is determined, and then the input signal is sampled at time t ₁ . The gain G3 (4 times) is unconditionally applied to the analog value (0.382).
is applied, 0.382×4=1.528＞1.0(=0.25×
4), the full scale is suppressed to 0.25, and the plot waveform of A-D conversion is at time t ₁ in b of the same figure.
The waveform becomes distorted as shown by the solid line.

On the other hand, the value sampled from the input signal at time t _b1 is
If it is 0.52, the range is 0.5 to 1.0, that is, the gain G1
(1x), and then the gain G1 (1x) is unconditionally applied to the analog value (0.382) obtained by sampling the input signal at time _t7 ,
0.382×1=0.382<0.5 (=0.25×2), resulting in less than half scale.

In this way, when n bits are used for A-D conversion, they are quantized intermittently with a size of 2 ^{- n} , and there is a conversion error due to the lack of effective number of bits. Distortion similar to the plot waveform of ₇ occurs.

As described above, automatic range switching according to the prior art has the drawback that if the rate of change of the input waveform is rapid, the amplification factor becomes inappropriate, resulting in waveform distortion after AD conversion. Moreover, this drawback stems from the fact that after determining the input range, it takes a finite amount of time to amplify the signal according to that determination, so it is not possible to deal with changes in the input signal during that time. It was a fundamentally unsolvable problem.

(c) Purpose of the Invention In order to solve the above-mentioned problems, the present invention provides a new automatic range switching system A that predicts the analog value at the sampling time from the analog value sampled at the input range determination time and determines the appropriate input range. −
The purpose is to provide a D converter.

(d) Structure of the Invention The structure of the present invention that achieves the above-mentioned object is to hold continuously input analog signals in analog signal holding means configured in multiple stages at each stage with a time difference. The holding output from the holding means is input to a number of calculation means corresponding to the number of stages of the holding means, and a predicted value of the continuously input analog signal after a predetermined time is calculated, and each calculated analog signal value is Converts it into a digital value consisting of multiple bits weighted for each bit position and outputs it serially.
The number of successive predetermined bit values at the output weighted bit positions is counted, and the amplification factor of the continuously input analog signal after the predetermined time is determined by multiplying the counted value by a power of 2. This feature is characterized in that the settings are made based on the following.

(e) Examples of the invention The details of the present invention will be explained below using the figures.

FIG. 2 is a diagram explaining the principle, where the horizontal axis is time t, and the vertical axis is the magnitude y of the analog signal 3 and its predicted value.

It is possible to predict the next sample value to some extent from the past sample value because analog signals have redundancy, and for this reason, the sampling frequency for A-D conversion is limited by the sampling theorem (sampling frequency is the signal frequency 2
(The analog signal cannot be reproduced unless it is at least twice as fast.)

The method of predicting the next sample point using several sample values for time-series data is a well-known technique, and it is also well-known that a linear or non-linear prediction formula can be used as a prediction formula. The invention focuses on this point.

In Figure 2, t _o-4 to _{t o+3} are sample times taken at equal intervals, y _o-4 to _{y o+3} are analog values corresponding to the sample times, and the prediction formula used is the primary prediction or Third-order prediction level (of course, the prediction formula is not limited to this)
Then, predict _o from y _o-2 , y _o-1 y _o-3 , y _o-2 , y Predict _o from _o-1 y _o-4 , y _o-3 , y _o-2 , y In each case of predicting _o from _o-1 , the sampling time intervals are made equal, and the first prediction... _o = −y _o-2 +2y _o-1 (1) The second prediction... _o = y _o-3 −3y _o-2 +3y _o-1 (2) Third prediction... _o =-y _o-4 +4y _o-3 -6y _o-2 +4y _o-1
(3) becomes.

FIG. 3 is a block diagram showing an embodiment of the present invention based on the cubic prediction of equation (3), in which 30 is a programmable gain amplifier (PGA), 31 is a switch (SW), and 32 is an analog-to-digital converter (ADC), 4
0 is a control unit, 41 to 45 are sample and hold circuits (SHA, SHB, SHC, SHD, SHE), 51 and 52 are operational amplifiers, R1 to R7 are resistors,
ANAIN is an input analog signal, ADS is an A-D conversion start command signal, SC is a switching command signal, Gi is a gain specification code, GA to GE are hold command signals,
V _o-4 to V _o-1 and V _o and _o indicate the voltage, respectively.

The input analog signal ANAIN input to the PGA 30 is a gain designation code from the control unit 40.
Gi, the output is held by SHE45 controlled by hold command signal GE and input to SW31, while hold command signal GA is exclusively output from hold command signal GE. SHA41 to SHD44 in GD to GD
is controlled and the output voltages V _o-4 to V _o-1 are held and output. From within this hold output voltage
V _o-3 and V _o-1 are input to the negative terminal of the operational amplifier 51 via resistors R1 and R2, respectively, and V _{o-4 from the output voltage and hold output voltage from the operational amplifier 51 is inputted to the negative terminal of the operational amplifier 51 through resistors R1 and R2,} respectively. and V _o-2 are respectively input to the negative terminal of the operational amplifier 52 via resistors R4, R5, and R6, and the predicted voltage _o is outputted, and SW
31.

SW3 which has either the output voltage V _o or the predicted voltage ^V _o switched by the switching command signal SC
1, the ADC 32 performs A/D conversion in response to an A/D conversion start command signal ADS, and outputs it as a digital value.

This digital value is output (OUTPUT) as it is to a subsequent stage (not shown) when the output voltage V _o is A-D converted. Also, the predicted voltage _o is A-D
When converted, determine the input range range as shown in Figure 5 below, and enter the gain specification code Gi.
PGA30.

FIG. 4 is an operation time chart when the configuration shown in FIG. 3 is used. The operation of this time chart is based on the resistance R shown in Figure 3, which is selected as R3 = 4xR1 = 4xR2, R7 = R4 = R5 = 6xR6 to match the coefficients of equation (3) above. be.

In the figure, the sample hold times are t _o-4 , t _o-3 ,
t _o-2 and t _o-1 , and the sample and hold circuits SHA41, SHB42, and SHC are activated at this time.
43, hold command signals GA, GB to SHD44,
Apply GC and GD. That is, by applying the hold command signal GD to the SHD 44, the voltage V _o-4 held at time t _o-4 is outputted, and by applying the hold command signal GC to the SHC 43, it is outputted at the time t _o-3.
Output the voltage V _o-3 held by SHB42
By applying hold command signal GB to
Output the voltage V _o-2 held by t _o-2 and SHA
By applying a hold command signal GA to 41, the voltage V _o-1 held at time t _o-1 is outputted.

These output voltages are input to operational amplifiers 51 and 52 between time t _{o -1} and time t ₁ , and predicted voltage _o appears at the output terminal of operational amplifier 52 . here _o
is the predicted voltage at time t _o , which is input to the ADC 32 from SW 31, which has been switched to the predicted voltage _o input side by the switching command signal SC in advance, and is
A/D conversion is performed from time _{t 1 to} time t ₂ by the A/D conversion start command signal ADS applied at t 1 . If this output is input to the control unit 40 as a serial bit output and the gain designation code Gi is calculated, the A-D
The value of the gain specification code Gi can be determined when the conversion is completed, and the value of the gain specification code Gi is immediately converted to PGA.
30. Therefore, at time _to , the hold command signal GE is applied to the SHE45, and the PGA30 receives the input analog signal according to the value of the gain designation code Gi.
Amplify ANAIN and make the output voltage V _o of SHE45,
SW31 is switched to the sample output side using the switching command signal SC, input to ADC32, and A-D
A-D conversion is performed by applying a conversion start command signal ADS at time _to .

In this way, the input analog signal ANAIN can be A-D converted with an appropriate amplification factor commensurate with the input range.

FIG. 5 is a block diagram for calculating the above gain designation code Gi, where a shows the circuit diagram and b shows the amplification factor. In the figure, 60 is a counter (CT),
P0 is a parallel output, S0 is a serial output, and other symbols that are the same as those in FIG. 3 are the same. Here, for convenience of explanation, the configuration of ADC32 is
MSB (Most Significant Bit) to LSB (Least Significant Bit)
up to 8 bits, 1 bit for sign + 7 bits for numerical value (bit configuration is arbitrary), full scale value is +
From 10160mV to -10240mV, the gain of PGA30 is ^20
27 can be specified according to the output of the CT 60, and b in the figure shows the amplification factor under this condition.

In order to determine the input range, first the control unit 40
Gain specification code Gi (count value) of CT60 from
is set to 0, and therefore the gain (2 ^Gi ) of the PGA 30 is set to 1. The output of the ADC 32 is in two's complement format, and serial output S0 is used sequentially from MSB to LSB.

Therefore, range determination can be made in the following two ways.

If the MSB is "0" (positive), check the serial output S0 from the ADC 32 and count the number of "0"s until a "1" appears.

If the MSB is "1" (negative), check the serial output S0 from the ADC 32 and count the number of "1"s until a "0" appears.

The counted number here is the gain designation code Gi, and the amplification factor of the PGA30 shows an appropriate amplification factor as shown in figure b, and according to this result,
Amplify the input analog signal ANAIN.

Incidentally, time _t2 in FIG. 4 is also the predicted sampling start time for the next A/D conversion.

In addition, in one embodiment of FIG. 3, A of the predicted voltage _o
-D converter and A-D converter with sample-and-hold amplified output voltage V _o are used in the common ADC 32, but for the predicted voltage _o , due to its necessity, the above-mentioned A-D converter is used. For example, a higher speed A/D converter different from the above may be used, for example, by connecting directly to the output side of the operational amplifier 52 and inputting it to the control section 40.

As an application of one embodiment of the present invention, the operation shown in the time chart of FIG. 6 is obtained.

The difference between FIG. 6 and the time chart in FIG. 4 is that the predicted voltage _o +1 at time t _{o+ 1} is calculated instead of the predicted voltage o at time t _o . For this purpose, the coefficients of equation (3) above should be set to the third-order prediction... _o+1 = −4y _o-4 +15y _o-3 −20y _o-2 +10y _o-1 (4) , and the resistance R1 in Figure 3 is
Regarding the resistor R7, it is sufficient to set it as R3=10xR2=15xR1, R4=R7=20xR6=4xR5.

The advantage of using this equation (4) is that the A-D conversion time for predicting the input range and the time for amplifying the input analog signal ANAIN with the amplification factor according to the calculation result are shown in Figure 4. Since the time chart can be longer than the time chart shown, it is possible to use a low-speed A-D converter or an amplifier with a slow settling time.

FIG. 7 is a block diagram of another embodiment of the present invention. In the figure, the symbols used are the same as those used in Figure 3, and the difference between Figure 7 and Figure 3 is the sample and hold circuits SHA41 and SHB4.
2. Input analog signal to SHC43 and SHD44
The point is that it is connected in series to ANAIN.

Although the embodiments of the present invention have been described above using cubic prediction, it goes without saying that the application of the present invention is not limited to this.

For example, as a prediction formula, in order to check the suitability of input range determination for each of the primary prediction, secondary prediction, and tertiary prediction, the input analog signal is a sine wave and the prediction error is calculated as shown in Figure 8. In the figure, a is a waveform diagram, and b is a goodness of fit, which is the true value y ₀ to y ₈ and error when sampled at every 22.5° obtained by dividing one wavelength of the sine wave into 16. According to the figure, although the third-order prediction is the best in terms of fitness, it can be seen that the effects of the present invention can be expected to a considerable extent even with the first-order prediction.

On the other hand, range determination using this prediction formula has the advantage in principle of being able to sample the analog signal at equal intervals, but it is a predicted value and the output from the operational amplifier contains errors. Therefore, there is an unavoidable risk that the actual value will fall into a range different from the amplification factor of the predicted value, but this risk can be easily avoided by multiplying the predicted value by a coefficient of 1 or more. For example, by setting the value of resistor R7 in Figure 3 to 1.1, the automatic range switching range will be reduced to about 0.45 to 0.91, but if the prediction error is within 10%, overflow will not occur. .

(f) Effects of the invention As stated above, when a digital computer processes the output from something with a very wide variation range of output analog quantity, fixed range analog-to-digital (A-D) conversion is required. Even if it is a vessel,
This has the remarkable effect of being able to eliminate the constraints imposed by the number of bits used during conversion, and allowing digital conversion to be performed with sufficient accuracy.

In addition, even when many types of analog signals with various full-scale values are input one after another and are digitized while being time-divided according to the input time, the accuracy after digital conversion can be determined for each input signal. Since this can be guaranteed, the level of each input signal can be amplified to match the full scale value, which has a great effect.

[Brief explanation of the drawing]

Fig. 1 is a diagram of waveform distortion generation in conventional automatic range switching A-D conversion, Fig. 2 is a diagram explaining the principle of predicted voltage calculation, Fig. 3 is a block diagram of an embodiment of the present invention, and Fig. 4 is FIG. 3 is a time chart, FIG. 5 is a block diagram when calculating the amplification factor, FIG. 6 is a different time chart from FIG. 3, FIG. 7 is a block diagram of another embodiment of the present invention, and FIG. It is an explanatory diagram of the goodness of fit of the prediction formula, in which 30 is a programmable gain amplifier PGA, 31 is a switch SW, and 32 is an A
-D converter ADC, 40 is a control unit, 41 to 45 are sample and hold circuits SHA, SHB, SHC,
SHD, SHE, 50 and 51 are operational amplifiers, 60 is a counter CT, ANAIN is an input analog signal, R
1 to R7 are resistors, V _o-4 to _{V o-1} are output voltages, _o is predicted voltage, Gi is gain specification code, ADS is A-D
Conversion start command signal, SC is switching command signal, GA
~GE is the hold command signal, S0 is the serial output,
P0 each indicates a parallel output.

Claims (1)

[Claims] 1. A continuously input analog signal is held in a multi-stage analog signal holding means at each stage with a time difference, and the number of holding outputs from the multi-stage holding means is determined according to the number of stages of the holding means. calculates the predicted value of the continuously input analog signal after a predetermined time, and converts the calculated analog signal value into a digital value consisting of a plurality of bits weighted for each bit position. Serially output, count the consecutive number of predetermined bit values at the output weighted bit positions, and calculate the amplification factor of the continuously inputted analog signal after the predetermined time by using the counted value as a power value. An automatic range switching analog-to-digital conversion method that sets the range based on the power of 2.