JPH0542027B2 - - Google Patents

Info

Publication number
JPH0542027B2
JPH0542027B2 JP6101087A JP6101087A JPH0542027B2 JP H0542027 B2 JPH0542027 B2 JP H0542027B2 JP 6101087 A JP6101087 A JP 6101087A JP 6101087 A JP6101087 A JP 6101087A JP H0542027 B2 JPH0542027 B2 JP H0542027B2
Authority
JP
Japan
Prior art keywords
cpu
cpus
lock control
identifier
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP6101087A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63228367A (ja
Inventor
Yoshiichi Mori
Tadashi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6101087A priority Critical patent/JPS63228367A/ja
Publication of JPS63228367A publication Critical patent/JPS63228367A/ja
Publication of JPH0542027B2 publication Critical patent/JPH0542027B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
JP6101087A 1987-03-18 1987-03-18 主記憶アクセス方式 Granted JPS63228367A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6101087A JPS63228367A (ja) 1987-03-18 1987-03-18 主記憶アクセス方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6101087A JPS63228367A (ja) 1987-03-18 1987-03-18 主記憶アクセス方式

Publications (2)

Publication Number Publication Date
JPS63228367A JPS63228367A (ja) 1988-09-22
JPH0542027B2 true JPH0542027B2 (de) 1993-06-25

Family

ID=13158933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6101087A Granted JPS63228367A (ja) 1987-03-18 1987-03-18 主記憶アクセス方式

Country Status (1)

Country Link
JP (1) JPS63228367A (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0424862A (ja) * 1990-05-18 1992-01-28 Nec Corp 処理装置間の障害検出方式
JP5093755B2 (ja) * 2007-12-06 2012-12-12 三浦工業株式会社 連携制御方法

Also Published As

Publication number Publication date
JPS63228367A (ja) 1988-09-22

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