JPH0540574Y2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to a muting signal generation circuit, and more particularly to a muting signal generation circuit suitable for use in the front stage of a stereo multiplex circuit of a radio receiver.

(b) Prior Art A muting signal generating circuit as disclosed in Japanese Patent Publication No. 58-41694 is used in radio receivers for the purpose of removing various noises. As shown in FIG. 2, the mutating signal generation circuit includes a first differential amplifier circuit 3 for outputting an input signal supplied from an input signal source 1 to an output terminal 2;
a second differential amplifier circuit 5 for deriving the DC voltage from the DC power supply 4 to the output terminal 2; and a transistor 6 whose collector constitutes the first differential amplifier circuit 3.
and a third differential amplifier circuit 12 consisting of a transistor 8 connected to the common emitter of transistors 9 and 7, and a transistor 11 whose collector is connected to the common emitter of transistors 9 and 10 forming the second differential amplifier circuit 5; The third differential amplifier circuit 12 includes a switch 13 connected to the base of the transistor 11 constituting the third differential amplifier circuit 12. However, the switch 1
3 schematically represents the application of a muting signal; when the switch 13 is on, the muting state is entered, and when the switch 13 is off, the muting state is released.

If the switch 13 is now off, the transistor 8 of the third differential amplifier circuit 12 is on and the transistor 11 is off. Therefore, the first differential amplifier circuit 3 becomes active, the second differential amplifier circuit 5 becomes inactive, and the input signal from the input signal source 1 is output to the output terminal 2.
Further, if the switch 13 is on, the transistor 8 of the third differential amplifier circuit 12 is turned off, the transistor 11 is turned on, the first differential amplifier circuit 3 becomes inactive, and the 2 differential amplifier circuit 5 becomes operational. Therefore, the transmission of the input signal is stopped, and the DC voltage from the DC power source 4 is led out to the output terminal 2, resulting in a muting state.

(c) Problems to be solved by the invention The mutating signal generation circuit shown in FIG.
There is no problem with the audio output operation, but
The drawback was that it was unable to prevent the harsh popping sound that occurs in relation to the detuning of the FM tuner. That is, since the muting control signal that controls the switch 13 is the same as the muting control signal for performing the detuning muting, the muting of the muting signal generation circuit of FIG. 2 is also canceled at the same time as the detuning muting is canceled. However, it was not possible to prevent pop noises caused by fluctuations in the DC voltage when the detuning mute was released.

(d) Means for solving the problem The present invention was created in view of the above points, and consists of a first transistor to which a muting control signal is applied, and a second transistor to which a delay capacitor is connected to the base. , comprising a charging transistor that charges the delay capacitor according to the collector current of the first transistor, and an output circuit that generates a muting signal according to the collector current of at least one of the first and second transistors. be.

(E) Effect According to the present invention, the muting circuit is brought into operation at the same time as the muting control signal is generated,
Muting can be started and the muting circuit can be made inactive after a certain period of time has passed after the mutating control signal has stopped, and mutating can be canceled, thereby preventing pop noises caused by DC changes in the preceding stage circuit. be able to.

(F) Embodiment Figure 1 is a circuit diagram showing an embodiment of the present invention.
14 is a first transistor with a switch 15 connected to its base, and 16 is a delay capacitor 17 at its base.
a second transistor 18 connected to the first transistor;
A third transistor differentially connected to the transistor 14; 19 a fourth transistor differentially connected to the second transistor 16; 20 a diode 2;
1 and a charging transistor 22, the first
a charging circuit that charges the delay capacitor 17 according to the collector current of the transistor 14;
consists of a first output transistor 24 that generates a muting signal in response to the collector current of the first transistor 14 and a second output transistor 25 that generates a muting signal in response to the collector current of the second transistor 16; 1
and an output circuit that generates a muting signal at an output terminal 26 connected to the common collector of the second output transistors 24 and 25.

Now, if there is no muting control signal and the switch 15 is off, the first transistor 14 is turned off, and the third transistor 18 is turned on by the action of the DC power supply 27, and the first transistor 14 is turned off.
When the transistor 14 is turned off, the charging transistor 22 of the charging circuit 20 and the first output transistor 24 of the output circuit 23 are also turned off. Further, when the charging transistor 22 is turned off, the delay capacitor 17 is not charged, the second transistor 16 also remains off, and the second output transistor 25 also remains off accordingly. Therefore, in the muting release state where the switch 15 is open,
No muting signal is generated at the output terminal 26.

Next, when the muting control signal is present and the switch 15 is turned on, the voltage of the DC power supply 28 higher than the voltage of the DC power supply 27 is applied to the first transistor 1.
4, the first transistor 14 is turned on and the third transistor 18 is turned off. When the first transistor 14 is turned on,
A current flows through the diode 21, and the diode 21
The charging transistor 22 and the first output transistor 24, which are connected in a current mirror manner to the first output transistor 24, are turned on. When the charging transistor 22 is turned on, charging of the delay capacitor 17 is started, and the delay capacitor 1
When the terminal voltage of the transistor 7 reaches a predetermined value, the second transistor 16 is turned on and the fourth transistor 19 is turned off. As mentioned earlier, switch 15 is turned on,
When the first transistor 14 is turned on, the first output transistor 24 is immediately turned on, and a muting signal is generated at the output terminal 26. Then, after a certain period of time has elapsed, when the terminal voltage of the delay capacitor 17 reaches a predetermined value, the second transistor 16 is turned on.
The second output transistor 25 is turned on and remains in that state as long as the switch 15 is turned on.

Further, in a muting state where a muting signal is generated at the output terminal 26, when the muting control signal is stopped and the switch 15 is turned off, the first transistor 14 is turned off, so that the charging transistor 22 and the first output transistor are turned off. 24 turns off immediately and delay capacitor 1
7 stops charging. However, since the terminal voltage of the delay capacitor 17 is sufficiently high, the second transistor 16 is not turned off, and the second output transistor 25 is not turned off either, so that the muting signal continues to be generated at the output terminal 26.

When the discharge of the delay capacitor 17 progresses and the base voltage of the second transistor 16 becomes lower than the DC voltage of the DC power supply 27, the second transistor 16
is turned off, the second output transistor 25 is also turned off, and no muting signal is generated at the output terminal 26. Therefore, the period during which the muting signal is generated is from when the switch 15 is turned on until when the second transistor 16 is turned off.

The muting signal obtained at the output terminal 26 of the muting signal generation circuit of FIG. 1 is used instead of the control signal obtained from the switch 13 and the DC power supply 29 of FIG.
The voltage is applied to the base of the transistor 11 constituting the transistor 2, and muting is performed as explained in FIG.

Therefore, the muting signal generation circuit shown in FIG. 1 is inserted between the detection stage and the stereo multiplex stage of the FM tuner with detuning mute, and the muting signal for the detuning mute is generated by the muting signal generation circuit shown in FIG. If the muting control signal is set to 1, the pop sound generated when the detuning mute is released is prevented from being transmitted to the stereo multiplex stage.

(g) Effects of the invention As described above, according to the invention, a mutating signal is generated at the same time as the application of the mutating control signal, and the mutating signal is canceled after a certain period of time has passed after the mutating control signal is stopped. This has the advantage that it is possible to prevent the occurrence of pop noises caused by detuned mute.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional muting signal generation circuit. Explanation of main figure numbers, 14...first transistor,
16... Second transistor, 17... Delay capacitor, 20... Charging circuit, 23... Output circuit.

Claims (1)

[Scope of utility model registration request] a first transistor having a base to which a muting control signal is applied; a second transistor having a base connected to a delay capacitor; a charging transistor charging the delay capacitor according to a collector current of the first transistor; and an output circuit that generates a muting signal in response to the collector current of at least one of the second transistors, and generates the muting signal simultaneously with the application of the mutating control signal and after the termination of the mutating control signal. A mutating signal generation circuit configured to stop the mutating signal.