JPS5830248Y2 - muting circuit - Google Patents
muting circuitInfo
- Publication number
- JPS5830248Y2 JPS5830248Y2 JP11835677U JP11835677U JPS5830248Y2 JP S5830248 Y2 JPS5830248 Y2 JP S5830248Y2 JP 11835677 U JP11835677 U JP 11835677U JP 11835677 U JP11835677 U JP 11835677U JP S5830248 Y2 JPS5830248 Y2 JP S5830248Y2
- Authority
- JP
- Japan
- Prior art keywords
- signal transmission
- circuit
- muting
- resistor
- state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Amplifiers (AREA)
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
Description
【考案の詳細な説明】
本考案はテープレコーダーに於けるミューティング回路
の改良に関する。[Detailed Description of the Invention] The present invention relates to an improvement of a muting circuit in a tape recorder.
一般にテープレコーダーのミューティング回路は再生状
態から停止状態に切換わる時、又は停止状態から再生状
態に切換わる時に動作するようになっている。Generally, the muting circuit of a tape recorder operates when switching from a playback state to a stop state, or when switching from a stop state to a playback state.
即ち、再生状態から停止状態に切換わる時には瞬時に信
号伝送路をミューティングすることが好１しく、又停止
状態から再生状態に切換わる時にはテープが正常速度に
なる１での開信号伝送路をミューティングすることが好
渣しい。That is, when switching from the playback state to the stop state, it is preferable to mute the signal transmission path instantaneously, and when switching from the stop state to the playback state, it is preferable to open the signal transmission path at 1, where the tape reaches normal speed. I like muting.
このため従来は第１図に示すようにステレオテープレコ
ーダーにあっては再生状態から停止状態に切換わった時
第１信号伝送路１の出力を瞬時に接地するための第１ミ
ユーテイングスイツチＳ１と、第２信号伝送路２の出力
を瞬時に接地するための第２ミユーテイングスイツチＳ
２と、停止状態から再生状態に切換わった時第１及び第
２信号伝送回路１，２を成る時間だけ接地するための第
３ミユーテイングスイツチＳ３とを備えていた。For this reason, conventionally, as shown in Fig. 1, in a stereo tape recorder, a first muting switch S1 is provided to instantly ground the output of the first signal transmission path 1 when switching from the playback state to the stop state. , a second mutating switch S for instantaneously grounding the output of the second signal transmission line 2;
2, and a third muting switch S3 for grounding the first and second signal transmission circuits 1 and 2 for a certain period of time when switching from a stop state to a regeneration state.
本考案は斯る従来回路に釦いて用いていたスイッチの数
を減少せしめて回路配線を簡潔にし、併せてコストの低
減を計ったものである。The present invention aims to reduce the number of switches used in conventional circuits, simplify the circuit wiring, and reduce costs.
以下第２図に示す本考案回路の実施例につき説明する。An embodiment of the circuit of the present invention shown in FIG. 2 will be described below.
図は第１図と同様のステレオテープレコーダーを表わし
て釦り、３は入力端子４、プリアンプ５、メインアンプ
６及び出力端子７から威る第１信号伝送路、８は入力端
子９、プリアンプ１０、メインアンプ１１及び出力端子
１２から成る第２信号伝送路である。The figure shows a stereo tape recorder similar to that shown in Figure 1, with buttons 3, the first signal transmission path from the input terminal 4, preamplifier 5, main amplifier 6, and output terminal 7, 8 the input terminal 9, and the preamplifier 10. , a main amplifier 11 and an output terminal 12.
１３．１４は第１．第２信号伝送路３，８と接地間にそ
れぞれコレクタ、エミッタが接続された第１及び第２ト
ランジスタである。13.14 is the 1st. These are first and second transistors whose collectors and emitters are connected between the second signal transmission lines 3 and 8 and ground, respectively.
１５．１６は前記各信号伝送路３，８の出力端子ｌ、１
２にそれぞれ一方の固定接点ａ、ａが接続されると共に
可動接片す、ｂが共通に接地された第１及び第２切換ス
イツチで、この切換スイッチ１５，１６はテープレコー
ダーの再生、停止の切換操作に関連して切換えられるも
ので、前述のミューティングスイッチである。15.16 are the output terminals l and 1 of each of the signal transmission lines 3 and 8.
These are first and second changeover switches, in which one fixed contact a, a is connected to 2, and the movable contacts a, b are commonly grounded. This switch is switched in connection with the switching operation, and is the aforementioned muting switch.
Ｌｌは前記第１及び第２トランジスタ１３，１４０各ベ
ースにバイアス抵抗１８，１９及びダイオード２０を介
して接続された充放電回路であり、該回路Ｕ′は抵抗２
１及びコンデンサ２２の並列回路から成る。Ll is a charging/discharging circuit connected to the bases of the first and second transistors 13, 140 via bias resistors 18, 19 and a diode 20;
1 and a capacitor 22 in parallel.
２３は該充放電回路Ｕに電源（十Ｂ）を供給する抵抗２
４と逆流防止用ダイオード２５の直列回路で、該抵抗２
４と逆流防止用ダイオード２５の接続中点Ｘが倒れか一
方の切換スイッチ１６の他方の固定接点Ｃに接続されて
いる。23 is a resistor 2 that supplies power (10 B) to the charging/discharging circuit U.
4 and a backflow prevention diode 25, the resistor 2
4 and the backflow prevention diode 25 are connected to the other fixed contact C of one of the selector switches 16.
本考案回路は上述の如く構成されたもので、以下にその
動作を説明する。The circuit of the present invention is constructed as described above, and its operation will be explained below.
図示の状態は切換スイッチ１５，１６の可動接片す、ｂ
が他方の固定接点ｃ、ｃ側に切換っている再生状態を示
しており、この時第１及び第２信号伝送路３．８はその
出力端子γ、１２が接地されておらず、又電源（十Ｂ）
は抵抗２４及び切換スイッチ１６を通じて接地されてお
り、この時充放電回路Ｕの充電はなされていない。The illustrated state is the movable contacts of the changeover switches 15 and 16.
shows a reproducing state in which the switch is switched to the other fixed contact c, c side, and at this time, the output terminals γ and 12 of the first and second signal transmission lines 3.8 are not grounded, and the power supply (10B)
is grounded through the resistor 24 and the changeover switch 16, and the charging/discharging circuit U is not being charged at this time.
従って第１及び第２トランジスタ１３，１４は非導通状
態にあって各信号伝送路３，８はミューティングされて
いない。Therefore, the first and second transistors 13 and 14 are in a non-conductive state, and each signal transmission path 3 and 8 is not muted.
次に断る再生状態より停止状態に切り換えたならば、各
切換スイッチ１５．１６の可動接片す。Next, when the regeneration state is switched to the stop state, the movable contacts of each changeover switch 15 and 16 are turned off.
ｂが一方の固定接点ａ、ａに切換わる。b is switched to one fixed contact a, a.
この時第１及び第２信号伝送路３，８の出力端子７，１
２は各スイッチ１５．１６を通じて接地されるので、各
出力を瞬時にミューティングする。At this time, the output terminals 7 and 1 of the first and second signal transmission lines 3 and 8
2 is grounded through each switch 15, 16, thereby instantly muting each output.
そして同時に切換スイッチ１６の固定接点Ｃが接地から
開放されるので、電源（十Ｂ）の電圧が抵抗２４及び逆
流防止用ダイオード２５を通じて充放電回路Ｕのコンデ
ンサ２２に充電される。At the same time, the fixed contact C of the changeover switch 16 is disconnected from the ground, so that the voltage of the power source (10 B) is charged to the capacitor 22 of the charging/discharging circuit U through the resistor 24 and the backflow prevention diode 25.
そのため抵抗１８．１９を通して正電位が第１及び第２
トランジスタ１３．１４のベースに供給されて各トラン
ジスタ１３，１４は導通状態となり、プリアンプ５，１
００出力は接地され各信号伝送路３，８は完全にミュー
ティング状態となる。Therefore, a positive potential is applied to the first and second terminals through resistors 18 and 19.
It is supplied to the bases of transistors 13 and 14, and each transistor 13 and 14 becomes conductive, and the preamplifiers 5 and 1
The 00 output is grounded and each signal transmission line 3, 8 is completely muted.
次にこの停止状態より再生状態に切換えたならば、各切
換スイッチ１５．１６は図示の状態になり、出力端子Ｔ
、１２に係る□ニーティングが解除され、同時に充放電
回路Ｕへの電源（十Ｂ）の供給が解除される。Next, when switching from this stopped state to the reproducing state, each changeover switch 15, 16 will be in the state shown, and the output terminal T
, 12 is canceled, and at the same time, the supply of power (10B) to the charging/discharging circuit U is canceled.
しかし、コンデンサ２２に充電された電荷が抵抗２１を
通じて放電する間トランジスタ１３，１４が導通状態に
あるためプリアンプ５，１００出力はミューティング状
態にあり、しばらくした後にそのミューティングが解除
されることになる。However, since the transistors 13 and 14 are in a conductive state while the charge stored in the capacitor 22 is discharged through the resistor 21, the output of the preamplifier 5,100 is in a muting state, and the muting will be canceled after a while. Become.
斯るプリアンプ出力のミューティング解除は、テープが
正常速度になった後においてなされるように充放電回路
Ｕによって設定されている。The charging/discharging circuit U is set so that muting of the preamplifier output is canceled after the tape reaches normal speed.
本考案ミューティング回路は上述したように構成したも
のであるから、従来必要としていたスイッチの個数を減
少させることが可能となると共に回路配線を簡潔にする
ことが出来、コストの低減を計ることが出来るものであ
る。Since the muting circuit of the present invention is configured as described above, it is possible to reduce the number of switches that were conventionally required, and the circuit wiring can be simplified, resulting in cost reduction. It is possible.
第１図は従来回路図を示し、第２図は本考案回路図を示
す。
３．１・・・信号伝送路、Ｔ、１２・・・出力端子、１
５゜１６・・・切換スイッチ、１７−・・充放電回路、
１３゜１４・・・トランジスタ、２４・・・抵抗、２５
・・・逆流防止用ダイオード。FIG. 1 shows a conventional circuit diagram, and FIG. 2 shows a circuit diagram of the present invention. 3.1... Signal transmission line, T, 12... Output terminal, 1
5゜16...Selector switch, 17-...Charge/discharge circuit,
13゜14...Transistor, 24...Resistor, 25
... Diode for backflow prevention.
Claims (1)
トランジスタと、前記信号伝送路の出力端子に一方の固
定接点が接続されると共に可動接片が接地された切換ス
イッチと、前記トランジスタのベースに接続された充放
電回路と、該充放電回路に電源を供給する抵抗と逆流防
止用ダイオードの直列回路とより成り、前記切換スイッ
チは再生、停止の切換操作に関連して切換えられその他
方の固定接点に前記抵抗と逆流防止用ダイオードの接続
中点を接続したことを特徴とするミューティング回路。a transistor whose collector and emitter are connected between a signal transmission path and ground; a changeover switch whose one fixed contact is connected to the output terminal of the signal transmission path and whose movable contact is grounded; It consists of a connected charging/discharging circuit, a series circuit of a resistor for supplying power to the charging/discharging circuit, and a backflow prevention diode, and the changeover switch is switched in connection with the regeneration/stop switching operation, and the other is fixed. A muting circuit characterized in that a connection point between the resistor and a reverse current prevention diode is connected to a contact point.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11835677U JPS5830248Y2 (en) | 1977-08-30 | 1977-08-30 | muting circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11835677U JPS5830248Y2 (en) | 1977-08-30 | 1977-08-30 | muting circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5442522U JPS5442522U (en) | 1979-03-22 |
| JPS5830248Y2 true JPS5830248Y2 (en) | 1983-07-04 |
Family
ID=29072611
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11835677U Expired JPS5830248Y2 (en) | 1977-08-30 | 1977-08-30 | muting circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5830248Y2 (en) |
-
1977
- 1977-08-30 JP JP11835677U patent/JPS5830248Y2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5442522U (en) | 1979-03-22 |
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