JPH0540150A - Semiconductor testing device - Google Patents

Abstract

PURPOSE:To enable an IC with a number of input/output pins to be tested by providing a synthesis circuit which synthesizes an output from the IC and a delay circuit and then comparing output signals at a plurality of arbitrary points using a comparison circuit. CONSTITUTION:Since an output signal is judged by a value ts of STB along with output signals DQ0 and DA1 for an output from an IC2, one signal DQ1 is delayed by a specified amount of time t by a delay circuit 7. A synthesis circuit 8 synthesizes the signal DQ0 and the delayed output signal DQ1 and judges the signal DQ0 by STB1 which is the DQ0 at the value ts of STB and the output signal DQ1 by STB2 which is a value ts+t of STB. These series of operations allow an output signal which is output from two input/output pins 3 to be judged by one comparator.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor tester for testing a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional semiconductor test apparatus (hereinafter referred to as IC
(Referred to as a tester), where 1 is I
The station portion of the C tester, 2 is an IC to be tested, 3 is an input / output pin of IC2, and here, IC2 having four input / output pins 3 is shown as an example. 4 is IC
A driver for applying a signal to the I / O pin 3 of 2 and I / I
Relay for O control, 6 is input / output pin 3 of IC2
This is a comparator that determines the output signals DQ _{0 to} DQ ₁ output from the I / O pin card 9 by the driver 4, the I / O control relay 5, and the comparator 6 described above. The I / O pin card 9 exists in the station 1, and the electric wiring 1 is connected to the input / output pin 3 of the IC 2.
There is a one-to-one correspondence with one.

Next, the operation will be described. The output signal from IC2 is I / O connected to each input / output pin 3 on a one-to-one basis.
The judgment is made by the comparator 6 in the O pin card 9. For example, the output signal DQ ₀ of the input / output pin 3 of IC2
Corresponds to I / O ₀ of the I / O pin card 9, the output signal DQ ₁ of the input / output pin 3 corresponds to I / O ₂ of the I / O pin card 9, and each output signal corresponds to the corresponding I / O pin. Card 9
It is determined by the internal comparator 6. Therefore, as many I / O pin cards 9 as the number of input / output pins 3 of the IC 2 are required.

In some IC testers, all pin cards are I / O pins, but most ICs
In order to reduce the price in a tester, it is general that the required minimum number is taken into consideration in consideration of the function of the IC to be tested.

[0005]

Since the conventional semiconductor test apparatus is constructed as described above, when the number of the input / output pins 3 of the IC 2 increases, the I / O pin card 9 runs short, I / O pin card 9 may be impossible in some cases, especially when multiple simultaneous measurements are being performed.
The number of simultaneous measurements decreases due to the lack of the number of devices, and the decrease in the processing capacity of the semiconductor test equipment poses a problem. There was a problem that it could not be used.

The present invention has been made in order to solve the above-mentioned problems, and prevents the deterioration of the processing capacity due to the decrease in the number of simultaneous measurement of a large number even if the number of input / output pins 3 of the IC 2 increases. At the same time, it is an object of the present invention to obtain a semiconductor test apparatus capable of maintaining the efficiency of the semiconductor test apparatus at the original level.

[0007]

In a semiconductor test apparatus according to the present invention, a delay circuit delays an output signal from an IC to be tested for a predetermined time, and an output signal from the IC and the delay circuit are delayed. A comparator circuit for synthesizing the output signal is provided, and the output signal at arbitrary plural points is determined by a comparator circuit.

[0008]

The semiconductor test apparatus according to the present invention enables determination of output signals output from a plurality of input / output pins of an IC to be tested with one I / O pin card.
Even if the number of I / O pins of the IC increases, it is possible to prevent the processing capacity from deteriorating, and it is possible to test an IC having many I / O pins with a small number of I / O pin cards, which is an inexpensive IC tester. Can be obtained.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a semiconductor tester (hereinafter referred to as an IC tester) according to an embodiment of the present invention. In the figure, 1 is a station portion of the IC tester, 2 is an IC to be tested, and 3 is an IC2. It is an output pin, and in this embodiment, it is assumed that the IC 2 has eight input / output pins 3 and outputs output signals DQ _{0 to} DQ ₇ from the input / output pins 3, respectively.

Further, FIG. 2 is a timing chart showing the process of judging the output signal from the IC, where a is the output signals DQ ₀ and DQ ₁ from the IC 2 and b is a delay circuit 7 which delays the signal by a time t. The output signal DQ ₁ is represented by c, and the output signal DQ ₀ and DQ ₁ synthesized by the synthesizing circuit 8 are synthesized and judged.

Reference numeral 4 is a driver for applying a signal to the IC 2, 5
Is a relay for I / O control, 6 is a comparator for judging an output signal output from the input / output pin 3 of the IC 2, and has a function of judging an output signal at a plurality of arbitrary points. Reference numeral 7 is a delay circuit that delays the output signal from the IC 2 for a predetermined time, and 8 is a combining circuit that combines a plurality of output signals from the IC 2. An I / O pin card 9 is composed of a driver 4, an I / O control relay 5, a comparator 6, a delay circuit 7, and a synthesis circuit 8.

Reference numeral 10 denotes a pin (PIN) on the station 1 of the IC tester, and the IC 2 and this pin 10 are connected by a wiring 11.

Next, the operation of this embodiment will be described below by taking the output signals DQ ₀ and DQ ₁ of the input / output pin 3 as an example.

For one I / O pin card 9, two input / output pins 3 are connected by wiring 11, and the output signal DQ ₀ is output to PIN1 on the station 1 and the output signal DQ ₀ is output.
Q ₁ is PIN 5 on station 1 and so on, 2
The two output signals DQ ₀ and DQ ₁ are connected to the I / O ₀ of the I / O pin card 9.

As shown in FIG. 2a, the output from IC2 must be determined by the value t _{S of} STB for both output signals DQ ₀ and DQ ₁ . In the case of the present invention, in order to judge the output signal by one comparator 6, one output signal DQ ₁ is delayed by a predetermined time t by the delay circuit 7 as shown in FIG. 2b.

Next, as shown in FIG. 2C, the output signal DQ ₀ and the delayed output signal DQ ₁ ′ are combined by the synthesizing circuit 8, and the output signal DQ is output at STB ₁ which is the value t _S of STB.
_The output signal DQ ₁ is determined based on STB _2, which is _0, which is the value t _S + t of STB.

In a series of these operations, one comparator 6 can determine the output signal output from the two input / output pins 3. The other input / output pins 3 can be determined by the same method.

In the above embodiment, an IC with eight input / output pins 3
2 is shown, but 2 ICs with 4 input / output pins
In the case of individual I / O pin cards, the same method can be used for testing.

In the above embodiment, the I / O pin 3 of the IC 2 and the I / O pin card 9 are connected by the wiring 11, but the IC 2 can be programmed by the relay matrix.
The connection between the input / output pin 3 and the I / O pin card 9 may be freely changed.

Further, in the above embodiment, the case where one comparator 6 judges the output signals of the two input / output pins 3 of the IC 2 has been described. However, the case where the number of the input / output pins 3 is three or more is arbitrary. Can be dealt with, and the same effect can be obtained.

[0021]

As described above, according to the present invention, since it is possible to judge the output signals output from the plurality of input / output pins of the IC to be tested with one I / O pin card, a large number of There is an effect that a test device capable of testing an IC having an input / output pin can be inexpensive.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a semiconductor test apparatus according to the present invention.

FIG. 2 is a timing chart showing a process of determining an output signal from an IC by the semiconductor test apparatus according to the present invention.

FIG. 3 is a configuration diagram showing a conventional semiconductor test apparatus.

[Explanation of symbols]

 1 Station part of IC tester 2 IC 3 to perform test 3 Input / output pin of IC2 4 Driver 5 I / O control relay 6 Comparator 7 Delay circuit 8 Synthesis circuit 9 I / O pin card 10 Pin on station 11 Wiring

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] January 9, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

Claims (1)

[Claims] 1. A semiconductor test apparatus for testing a semiconductor integrated circuit (hereinafter referred to as an IC) by determining an output signal output from the IC by a comparison circuit, wherein an output signal from the IC is predetermined. A semiconductor test apparatus comprising: a delay circuit that delays time and time; and a combining circuit that combines the output signal from the IC and the output signal delayed by the delay circuit.