JPH0537313Y2 - - Google Patents

Description

[Detailed description of the invention] <Industrial application field> This invention is an MPU peripheral device access method that improves the access time when a microprocessor MPU accesses peripheral devices such as a CRT controller or a floppy disk controller. This relates to control circuits.

<Prior Art> A conventional method by which a microprocessor MPU accesses its peripheral devices is shown in FIGS. 7 and 8.

Figure 7 shows the microprocessor MPU1 and CRT.
4 is a connection relationship diagram with peripheral devices 5 such as a controller and a floppy disk controller;
This is an address decoder provided between MPU 1 and peripheral device 5 via bus B.

In this figure, first, the MPU 1 outputs address signals A ₁ -A ₂₃ and an address strobe signal for outputting the timing at which the address signals A ₁ -A ₂₃ become valid. Address signal A ₁ ~
A ₂₃ is applied to the peripheral device 5 and also to the address decoder 4 at the same time. Address decoder 4 decodes address signals A ₁ to _{A 23} and these address signals A ₁ to _{A 23} are sent to peripheral device 5.
At the same time, it indicates that it is the address of the MPU.
It outputs a selection signal for synchronization with the enable signal E from 1, and outputs a chip select signal to the peripheral device 5. Confirmation output
VMA is a signal used as part of the chip select signal from MPU1.

FIGS. 8a and 8b show time charts representing the operation of this peripheral device access circuit.

In both figures, A is the system clock CL in the MPU 1, B is the address signals A ₁ to _{A 23} , C is the address strobe signal, D is the enable signal E, E is the selection signal, and F is the confirmation signal. Note that the enable signal is a clock pulse signal generated by a dedicated circuit inside the MPU 1.

FIG. 8a shows that the MPU 1 accesses the peripheral device 5 until the read or write operation is completed.
8b shows the earliest timing behavior (best case), and FIG. 8b shows the slowest timing behavior (worst case).

That is, the enable signal E is not necessarily a clock signal.
It is not necessarily synchronized with the pulse CL, and Fig. 8a
is at timing _t1 when enable signal E is “L”
MPU1 detects the signal output in state S4, sets the signal to "L", and during the period _e1 between the signal "L" and the enable signal E "H"
The MPU 1 executes an access operation to the peripheral device 5.

FIG. 8b shows that the enable signal E"L" cannot detect the signal "L" output in state S4 at detection timing _t2 , and detects the signal "L" at the next detection timing _t3 . ”
Output. Then, the MPU 1 executes an access operation to the peripheral device ₅ during a period e2 when the signal is "L" and the enable signal E is "H".

Note that the MPU 1 detects the signal at intermediate timings t ₁ , T ₂ , and t ₃ when the enable signal E is at “L” level, and the state w of the system clock CL is
Indicates the wait state of MPU1.

In this way, in conventional peripheral device access circuits, the best
10 of the system clock CL from state S0 to state S6 even in the case (Fig. 8a).
In the worst case (FIG. 8b), 19 states are required. That is,
Average (10+19)/2 from access start to end
= required a period of 14.5 clock pulses. Furthermore, since the enable signal E is fixed at a frequency that is 1/10 of the system clock CL by a dedicated circuit inside the MPU1, for example, even if you try to operate a peripheral device at 2MHz, the system clock
If the clock is 8MHz, the clock pulse (enable signal E) to peripheral device 5 is 0.8MHz.
was fixed, and no further speed-up of the operation could be achieved.

<Problem to be solved by the invention> The problem to be solved by the invention is that even if the frequency of the clock to peripheral devices is increased,
The purpose of this invention is to enable the MPU to access peripheral devices.
An object of the present invention is to provide an MPU peripheral device access control circuit that allows an MPU to access peripheral devices at high speed.

<Means for Solving the Problems> In order to solve the above problems, the present invention provides a method to solve the problems described above by using a memory storage system without using the dedicated interface function for accessing peripheral devices inside the MPU, which was mentioned in the section of the prior art. It utilizes read/write cycles using a sequencer consisting of circuits and latch circuits, and its configuration is as follows.

That is, as shown in FIG. 1, the present invention provides an MPU peripheral device access control device 6 that controls access to the peripheral device 5 designated by the microprocessor MPU 1. a memory circuit 61 which inputs an address decode signal DC obtained by decoding the address of , an address strobe signal on a control bus Bc, and a data strobe signal and generates an internal chip select signal from these; and a clock pulse signal CL. Divide the frequency of the MPU
1 to the peripheral device 5 to be accessed, latches the internal chip select signal, sends the latched chip select signal (clocked) to the memory circuit 61, and then A latch circuit 62 is provided for sending a response signal (clocked) to the memory circuit 61, and the memory circuit 61 immediately sends the latch chip select signal (clocked) given from the latch circuit 62 to the peripheral device. This MPU peripheral device access control circuit is characterized in that it provides a chip select signal and then provides the internal response signal (clocked) provided from the latch circuit 62 to the MPU 1 as a response signal ( ).

<Operation> The MPU peripheral device access control circuit of the present invention operates as follows.

When the microprocessor MPU accesses a peripheral device, it inputs a signal that decodes the address, an address strobe signal, and a data strobe signal, latches information related to the peripheral device from the memory circuit, and converts it into a clock pulse. The MPU accesses the peripheral devices by synchronously outputting an access enable signal to the MPU, and outputting chip select signals and enable signals to the peripheral devices.

<Embodiment> FIG. 1 shows an example of an MPU peripheral device access control circuit implementing the present invention.

In this figure, 1 is the microprocessor
MPU, 2 is a clock pulse generation circuit that outputs clock pulses of, for example, 16MHz, and 3 is a clock pulse generation circuit that outputs 8M clock pulses from clock pulse generation circuit 2.
A frequency divider circuit that divides the frequency of the system clock CL in Hz,
4 is an address decoder that decodes the address signal that MPU1 outputs to address bus B _A , and 5 is an address decoder that decodes the address signal that MPU1 outputs to address bus B A.
Peripheral devices that the MPU 1 accesses, 6 is an MPU peripheral device access control circuit according to the present invention. Note that the access control circuit 6 uses a ROM (read-only memory) as a storage circuit 61.
Alternatively, it is composed of a PLA (programmable logic array) and a latch circuit 62.

The operation of the access control circuit of the present invention constructed in this way will be explained with reference to the time chart of FIG.

In this figure, A is the 8MHz clock pulse CL output from the frequency divider circuit 3.

In this state, MPU1 is connected to peripheral device 5.
When accessing the address bus from MPU1
B Address output is performed to _A. Then, address signals of address bus B _A and data bus B _D
The address strobe signal and data strobe signal are set so that the upper data signal is valid.
DS2 is input to the ROM 61 of the access control circuit 6 via the control bus _BC . The operation shown in FIG. 2 is a read operation in which the MPU 1 reads data from the peripheral device 5 (read/write signal R/"H" H).

Furthermore, a latch circuit 62 in the access control circuit 6
inputs 8MHz clock pulse CL, and inputs 2MHz clock pulse CL.
The system clock (enable signal E) is output.

Now, the ROM 61 to which the address decode signal DC, address strobe signal and data strobe signal are input outputs an internal chip select signal "L", and this signal is latched by the latch circuit 62.

The latch circuit 62 then receives the enable signal E.
is "L" and at timing t when the system clocks CL and S2 fall, the latched internal chip select signal is output to the ROM 61 as a clocked "L" chip select signal.

The ROM 61 receives this latch chip select signal clocked “L” and converts it to the chip select signal clocked “L”.
It is immediately transmitted to the peripheral device 5 as a select signal "L".

Next, at the timing when the enable signal E becomes "H", the latch circuit 62 outputs an internal response signal clocked "L" to the ROM 61.

The ROM61 receives this internal response signal clocked.
Upon receiving DTACK "L", this signal is sent to the MPU 1 as a response signal "L".

Then, the enable signal E is “H” and the response signal is
During the DTACK "L" period _e3 , the MPU 1 accesses the peripheral device 5 and performs a read operation.

The operation ends when the address strobe signal and data strobe signal change from "L" to "H".

The timing chart in Figure 2 is for MPU1.
is the read operation for the peripheral device 5, and is the best case in which the access operation time is the shortest. That is, from the start to the end of the access operation, the bus cycle is 5 clocks from S0 to S7, and the enable signal E is 2MHz, so it takes 500ns.
You can perform access operations with .

In order to make the operation of the access control circuit 6 of the present invention easier to understand, FIG. 3 shows a state transition diagram corresponding to the states of the 8 MHz clock pulse.

From ST0 to ST8, enable signal E is “H”,
It represents a signal output according to the state of the internal signal of the access control circuit 6 in accordance with "L".

That is, if ST0 is the enable signal E "L" and the internal chip select signal is "H", ST1; enable signal E "L", ST2;
Enable signal E "H", ST3; enable signal E "H", ST0; state transition of enable signal E "L".

Further, in ST0, when the internal chip select signal "L" is output, it is latched, and in ST4, the internal chip select signal clocked "L" is output with the enable signal E "L". Next, when the enable signal E is “H”, ST
5; Internal response signal clocked “L” is output. ST6 shows the same state as ST5, ST7
Enable signal E “L”, ST8; Enable signal E “L”, internal chip select signal clocked
PCS “H”, internal response signal clocked “H”
Then, the state transitions to state ST2.

FIG. 4 shows the worst case in which the MPU 1 performs a read access operation to the peripheral device 5.

At timing t ₁ of the first ST0 ₁ , the internal chip select signal cannot be latched, and the next
This is a case where the internal chip select signal is latched at timing chip t ₂ of ST0 _2. As in the case of FIG. 2, MPU 1 accesses peripheral device 5 in ST5 and ST6, and the access operation starts in period e ₄ . Execute. In this case, eight states of the system clock CL are required from the start of access to the end of access.

In FIG. 5, MPU 1 communicates with peripheral device 5.
This shows the write access operation when writing data, and is the best case.

In the case of a write operation, unlike the case of a read operation, the data strobe signal is output one bus cycle later than the address strobe signal from MPU1, so the internal chip select signal latches for this cycle. is delayed, the internal chip select signal is detected at ST0 after passing through states ST2 and ST3, and ST
5. In period _e5 of ST6, an access operation is performed. In this case, six states are required from the start to the end of the access operation.

Figure 6 shows the worst write access operation.
In this case, the rise of the enable signal E,
Due to the falling timing, at ST0 ₁ ,
Since the internal chip select signal cannot be latched, the internal chip select signal is latched in state _ST02 , and an access operation is performed in period _e6 between ST5 and ST6.

In this case, nine states are required from the start to the end of access.

In this way, the access control circuit of the present invention
Access time can be controlled depending on MPU read access and write access.

In this example, the best read access
In this case, there are 5 states, and the worst case of a write cycle is 9 states, so the access operation can be executed in an average of (5+9)/2=7 bus cycles. For traditional access control circuits, the average bus cycle is 14.5
Compared to this, in the access control circuit of the present invention, the bus cycle time is less than 1/2 since the state is required.

<Effects of the invention> According to the MPU peripheral device access control circuit of the invention, the following effects can be obtained.

It is possible to realize an MPU peripheral device access control circuit that allows the MPU to access peripheral devices by increasing the frequency of the clock to the MPU peripheral devices, and allows the MPU to access peripheral devices at high speed. can.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an MPU peripheral device access control circuit according to an embodiment of the present invention, FIG. 2 is a time chart showing the operation of the MPU peripheral device access control circuit according to an embodiment of the present invention, and FIG. 3 is a diagram of the present invention. FIGS. 4 to 6 are state transition diagrams of the MPU peripheral device access control circuit according to the embodiment of the invention; FIG. 7 is a time chart showing the operation of the MPU peripheral device access control circuit in other cases according to the embodiment of the invention; 8 is a block diagram showing an example of a conventional peripheral device access control circuit, and FIGS. 8a and 8b are time charts for explaining the operation of the conventional peripheral device access control circuit. 1... Microprocessor MPU, 2... Clock/pulse generation circuit, 3... Frequency dividing circuit, 4...
Address decoder, 5... Peripheral device, 6...
...Access control circuit, 61...Memory circuit ROM,
62...Latch circuit, B _A ...Address bus, Bc
...Control bus, B _D ...Data bus.

Claims (1)

[Claims for Utility Model Registration] In an MPU peripheral device access control device 6 that controls access to a peripheral device 5 designated by the microprocessor MPU 1, an address of the peripheral device 5 accessed by the MPU 1 is decoded. A memory circuit 61 inputs an address decode signal DC, an address strobe signal on a control bus Bc, and a data strobe signal and generates an internal chip select signal from these, and a memory circuit 61 which divides the frequency of a clock pulse signal CL. Said MPU
1 to the peripheral device 5 to be accessed, latches the internal chip select signal, sends the latched chip select signal (clocked) to the memory circuit 61, and then and a latch circuit 62 that sends a response signal (clocked) to the memory circuit 61, and the memory circuit 61 immediately transmits the latch chip select signal (clocked) given from the latch circuit 62 to the peripheral device. 5 as a chip select signal, and then the internal response signal (clocked) given from the latch circuit 62 is given as a response signal () to the MPU 1.