JPH0536729A - Compound semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit which is excellent in property of electrically isolating elements and is free of electrode wiring disconnection, so as to reduce the mutual interference effect between each element constituting the semiconductor integrated circuit and the leak current between respective elements. CONSTITUTION:This device comprises a semiinsulating compound semiconductor substrate 1, a compound semiconductor high-resistance layer 5 grown at low temperature of approximately 200 deg.C, an insulating film 2, a compound semiconductor high-resistance deposition layer 4 formed on the insulating film and an active layer 6 whereon compound semiconductor elements are made. An active layer 6, whereon a plurality of compound semiconductor elements are made, is formed on a semiinsulating compound semiconductor substrate 1. The semiinsulating compound semiconductor substrate 1 and the active layer 6 are electrically separated by the compound semiconductor high-resistance layer 5 grown at low temperature. Between the active layers 6, each element is electrically separated completely by the insulating film 2 and the compound semiconductor high-resistance deposition layer 4 formed on the insulating film 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device and a method of manufacturing the same, and by electrically completely separating each element constituting an integrated circuit, mutual interference effect between each element and (EN) A compound semiconductor integrated circuit capable of operating stably even in a high-density integrated circuit because a leak current between elements can be significantly reduced.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, each element forming the integrated circuit must be electrically isolated. Schottky barrier gate field effect transistors (MESFETs) are mainly used in integrated circuits using GaAs. However, as a method for electrically separating elements, each element is selectively placed on a semi-insulating GaAs substrate. Semi-insulating GaAs formed separately in the formed n-type island region
Isolation between elements is performed by utilizing the insulating property of the substrate.

However, according to this method, since each element is not completely electrically separated, a leak current called a side gate effect is generated between each element and it is difficult to operate each element of the circuit independently. It was

As an effective method for suppressing such an effect, a region where no element is formed on the semi-insulating GaAs substrate,
That is, SiO ₂ and Ga ₂ O are formed in the region where element isolation is desired.
_A method has been proposed in which an insulating film such as ₃ is formed, and crystals are grown on the semi-insulating GaAs substrate by a molecular beam epitaxy method to separate elements. 17 to 19 are process cross-sectional views when performing element isolation. A film thickness of 50 to 100 is formed in a region on the semi-insulating GaAs substrate 1 where element isolation is desired.
A SiO ₂ film 2 of about Å is deposited (FIG. 17). This Si
Crystal growth is performed on the entire surface of the semi-insulating compound semiconductor substrate on which the O ₂ film is deposited, using a molecular beam epitaxy method at a growth temperature of around 600 ° C. (FIG. 18). At this time, the film grown on the GaAs substrate becomes a good epitaxial growth film (active layer) 6, whereas the film 4 deposited on the SiO ₂ film becomes a high resistance deposition layer having extremely poor crystallinity. Next, MESFET
The ohmic electrodes of the source electrode 7 and the drain electrode 9 and the Schottky gate electrode 8 are formed to separately form the MESFETs of the integrated circuit (FIG. 1).
9).

[0005]

However, in the above-mentioned conventional example, since each active layer 6 is not electrically completely separated from the semi-insulating GaAs substrate 1, the semi-insulating GaAs substrate is interposed between the separated MESFETs. There is a problem that the leakage current flows, the integration is advanced, and the closer the distance between the respective elements is, the more insufficient the suppression of the side gate effect becomes.

The present invention solves the above-mentioned conventional problems and provides an extremely excellent compound semiconductor device because each element can be electrically separated completely by a simple method.

[0007]

In order to achieve this object, the present invention forms a compound semiconductor device by using the following two methods.

In the first method, an insulating film is formed on a semi-insulating compound semiconductor substrate, a region for forming an element is selectively removed and a window is opened, and then a molecular beam epitaxy method is used to obtain a temperature of about 200 ° C. Compound semiconductor high resistance layer is grown at low temperature
Next, crystal growth of the compound semiconductor active layer is performed at a growth temperature of 400 ° C. or higher. Next, an electrode is formed in the region where the window is opened to form each semiconductor element forming an integrated circuit, and an insulating film and a high resistance growth layer deposited on the insulating film and a high resistance compound semiconductor grown at a low temperature are formed. In this method, the layer is used as an element isolation layer.

The second method is to grow a compound semiconductor high resistance layer on a semi-insulating compound semiconductor substrate at a low temperature of about 200 ° C. by using the molecular beam epitaxy method. Next, an insulating film is formed on the compound semiconductor high resistance layer, and a region for forming an element is selectively removed to open a window. Using the molecular beam epitaxy method again, crystal growth of the compound semiconductor active layer is performed at a growth temperature of 400 ° C. or higher, electrodes are formed in the region where the window is opened, and each semiconductor element forming an integrated circuit is formed, In this method, an insulating film and a high resistance growth layer deposited on the insulating film and a high resistance compound semiconductor layer grown at a low temperature are used as element isolation layers.

[0010]

In this method, a film grown on the compound semiconductor substrate at a growth temperature of 400 ° C. or higher by the molecular beam epitaxy method has a good crystallinity, whereas a film grown on the insulating film has a good crystallinity. A very high resistance amorphous film is formed.

The molecular beam epitaxy method is used to measure 200 to
The film grown on the compound semiconductor substrate at a low temperature of 250 ° C.
Usually, the temperature of the arsenic evaporation source is 200 to 250 ° C., and the stoichiometric composition ratio of the crystal shifts due to the excess arsenic adsorbed on the compound semiconductor substrate. A bad high resistance film is formed.

Therefore, each element is completely separated by the insulating film, the high resistance film formed thereon, and the high resistance film grown at a low temperature, so that the side gate effect between the elements can be reduced, It is possible to stabilize the operation of the device.

[0013]

EXAMPLE As a first example of the present invention, GaAs MES
FIG. 1 shows a method of manufacturing an integrated circuit composed of FETs.
~ It demonstrates using the process sectional drawing of FIG. First, semi-insulating G
A sulfuric acid-based etchant (for example, H ₂ SO ₄ : H ₂ O ₂ : H ₂ O = 8: 1: 1 etc.) for cleaning the surface of the aAs substrate 1.
Etching is performed on the entire surface of the semi-insulating GaAs substrate 1 by 50
A SiO ₂ film 2 of about 100 Å is deposited. S at this time
It is necessary to select the film thickness of the iO ₂ film 2 to be sufficiently thin so that step breakage does not occur when forming the electrodes of the FET and wiring each FET forming the integrated circuit (FIG. 1). Resist 3 is applied (Fig. 2), and F is applied by photolithography.
A window is opened in the resist in the region where ET is formed (FIG. 3). Next, SiO in the region where the FET is formed with hydrogen fluoride
_{The two} films are selectively removed to expose the surface of the GaAs substrate (Fig. 4). After removing the resist with acetone, and then introducing it into the high vacuum of the molecular beam epitaxy system to grow crystals on a clean GaAs surface, especially carbon-based impurities such as resist remaining on the surface by oxygen plasma treatment etc. Is completely removed. Ga for further crystal growth
Although it is necessary to clean the As surface, if a sulfuric acid-based etchant having a large etching rate is used, the step difference between the GaAs surface and the SiO ₂ surface in the portion where the window is opened becomes large, crystal growth, and FET electrode formation. , And because a step breakage is likely to occur when wiring the FETs that form the integrated circuit, a hydrochloric acid-based solution (for example, HCl: H ₂ O = 1: 1) that hardly removes GaAs is used. Surface treatment is performed (Fig. 5). After that, it is carried into a molecular beam epitaxy apparatus, and thermal cleaning is performed by heating the substrate to raise the temperature to 580 ° C. or higher to remove the natural oxide film on the GaAs surface, expose a clean GaAs surface, and start crystal growth. First, the growth substrate temperature is set to 200 to 250.
It grows on the GaAs substrate 1 at a low temperature of ° C. At this time 20
The film grown on the GaAs substrate at a low temperature of 0 to 250 ° C. forms a high resistance film 5 having poor crystallinity. On the other hand, SiO ₂
The crystal-grown film grown on top of this has an extremely high-resistance amorphous film 4 deposited (FIG. 6). Next, the growth substrate temperature is set to 500 to 600 [deg.] C. where normal GaAs growth is performed, and the growth is performed. First of all, the growth is about 5000 Å undoped GaAs.
N-type Ga having a Si concentration of about 5 × 10 ¹⁷ cm ⁻³ and a thickness of about 2000 Å to be an active layer of MESFET.
The Si concentration of 500 Å or less is 2 × 10 in order to perform As crystal growth and further reduce the FET source resistance.
Grow ¹⁸ cm ⁻³ n-type GaAs. The on the high-resistance GaAs layer 5 at low temperature growth when the epitaxial layer is grown with good crystallinity but, SiO ₂ film 2 thereto
A high resistance amorphous high resistance GaAs layer 4 is similarly deposited on the upper high resistance GaAs deposition layer 4 (FIG. 7).
Next, the substrate is taken out from the molecular beam epitaxy apparatus and FE
The source electrode 7 and the drain electrode 9 of T are formed. Au / Ge / Ni / Au or the like is used as the material of the ohmic electrode. Next, the high-concentration n-type GaAs layer in the gate portion where the Schottky electrode is formed is selectively removed by etching, and the enhancement type FET and the depletion type F are further removed.
In order to manufacture two types of FETs of ET, the threshold value of FETs is adjusted by changing the etching depth of the n-type GaAs layer. The gate electrode 8 is formed by using an electrode material such as Ti / Pt / Au, and finally wirings between the FETs are performed to manufacture an integrated circuit (FIG. 8).

Next, a second embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to process sectional views. First, semi-insulating GaAs
In order to clean the surface of the substrate 1, etching is performed with a sulfuric acid-based etchant (for example, H ₂ SO ₄ : H ₂ O ₂ : H ₂ O = 8: 1: 1). Introduced into the high vacuum of a molecular beam epitaxy system, the substrate is heated to perform thermal cleaning.
The temperature is raised to 0 ° C. or higher to remove the natural oxide film on the GaAs surface, expose a clean GaAs surface, and start crystal growth. First, the growth substrate temperature is set to a low temperature of 200 to 250 ° C.
It grows on the aAs substrate 1. At this time 200-250 ℃
The film grown on the GaAs substrate at a low temperature has a high resistance film 5 with poor crystallinity (FIG. 9). Next, the substrate is taken out from the molecular beam epitaxy apparatus and 50
A SiO ₂ film 2 of about 100 Å is deposited. S at this time
It is necessary to select the film thickness of the iO ₂ film 2 to be sufficiently thin so that step breakage does not occur when forming the electrodes of the FET and wiring each FET forming the integrated circuit (FIG. 10). A resist 3 is applied (FIG. 11), and a resist window is opened in a region where an FET is formed by photolithography (FIG. 12). Next, Si in the region where the FET is formed with hydrogen fluoride
The O ₂ film is selectively removed to expose the high resistance GaAs layer 5 grown at low temperature (FIG. 13). To remove the resist with acetone, and then to re-introduce it into the high vacuum of the molecular beam epitaxy system to perform crystal growth on a clean GaAs surface,
Particularly, carbon-based impurities such as resist remaining on the surface are completely removed by oxygen plasma treatment or the like. Further, it is necessary to clean the GaAs surface where crystal growth is performed, but if a sulfuric acid-based etchant with a large etching rate is used, the step between the GaAs surface and the SiO ₂ surface in the portion where the window is opened becomes large, Since step breakage is likely to occur when forming FET electrodes and wiring each FET that constitutes an integrated circuit, a hydrochloric acid-based solution (for example, HCl: H ₂ O = 1: 1) that hardly removes GaAs. The surface treatment is performed using (FIG. 14). After that, it is re-introduced into the molecular beam epitaxy apparatus, and thermal cleaning is performed by heating the substrate to raise the temperature to 580 ° C. or higher and GaA.
The natural oxide film on the s surface is removed, the clean GaAs surface is exposed, and crystal growth is started. At this time, the growth substrate temperature is set to a temperature at which the layer grown on SiO ₂ does not re-evaporate, and the temperature is set to 500 to 600 ° C. for performing normal GaAs growth. First of all, the growth is about 5000 Å undoped GaA.
n-type G with an Si concentration of about 5 × 10 ¹⁷ cm ^-3 and a thickness of about 2000 Å to be an active layer of MESFET.
The Si concentration of 500 Å or less is 2 × 1 for crystal growth of aAs and for reducing the source resistance of FET.
0 ¹⁸ cm ⁻³ n-type GaAs is grown. At this time, an epitaxial layer having good crystallinity grows on the high-resistance GaAs layer 5 grown at low temperature, while a high-resistance amorphous high-resistance GaAs deposition layer 4 is formed on the SiO ₂ film 2. To be done. (FIG. 15). Next, the substrate is taken out from the molecular beam epitaxy apparatus, and the source electrode 7 and the drain electrode 9 of the FET are formed. Au / Ge / Ni / Au or the like is used as the material of the ohmic electrode. Next, the high-concentration n-type GaAs layer in the gate portion where the Schottky electrode is formed is selectively removed by etching, and two types of FETs, an enhancement type FET and a depletion type FET, are further removed.
In order to manufacture the above, the threshold value of the FET is adjusted by changing the etching depth of the n-type GaAs layer. Ti / P
forming the gate electrode 8 using an electrode material such as t / Au,
Finally, wiring is performed between the FETs to manufacture an integrated circuit (FIG. 16).

In this embodiment, the GaAs substrate has been described, but it goes without saying that the same effect can be obtained with other compound semiconductor substrates such as GaP and InP.

[0016]

As described above, in the compound semiconductor device of the present invention, since each element can be electrically separated completely in the integrated circuit formed on the semi-insulating compound semiconductor substrate, the side gate effect between each element can be obtained. Can be greatly reduced, and the operation of the integrated circuit can be kept stable. Moreover, if the insulating film is made sufficiently thin, the step between the high-resistance compound semiconductor deposition layer and the compound semiconductor active layer can be reduced, and electrode disconnection can be eliminated at the same time. Therefore, it is practical for the production of high-density and high-performance compound semiconductor integrated circuits. This is extremely advantageous.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first step of a GaAs integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a second step of the GaAs integrated circuit according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a third step of the GaAs integrated circuit according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a fourth step of the GaAs integrated circuit according to the first embodiment of the present invention.

FIG. 5 is a sectional view of a fifth step of the GaAs integrated circuit according to the first embodiment of the present invention.

FIG. 6 is a sectional view showing a sixth step of the GaAs integrated circuit according to the first embodiment of the present invention.

FIG. 7 is a sectional view of a seventh step of the GaAs integrated circuit according to the first embodiment of the present invention.

FIG. 8 is a sectional view of an eighth step of the GaAs integrated circuit according to the first embodiment of the present invention.

FIG. 9 is a sectional view of a first step of the GaAs integrated circuit according to the second embodiment of the present invention.

FIG. 10 is a sectional view showing a second step of the GaAs integrated circuit according to the second embodiment of the present invention.

FIG. 11 is a sectional view showing a third step of the GaAs integrated circuit according to the second embodiment of the present invention.

FIG. 12 is a sectional view showing a fourth step of the GaAs integrated circuit according to the second embodiment of the present invention.

FIG. 13 is a sectional view of a fifth step of the GaAs integrated circuit according to the second embodiment of the present invention.

FIG. 14 is a sectional view showing a sixth step of the GaAs integrated circuit according to the second embodiment of the invention.

FIG. 15 is a sectional view of a seventh step of the GaAs integrated circuit according to the second embodiment of the present invention.

FIG. 16 is a sectional view showing an eighth step of the GaAs integrated circuit according to the second embodiment of the present invention.

FIG. 17 is a first process cross-sectional view of a conventional GaAs integrated circuit.

FIG. 18 is a sectional view of a second step of the conventional GaAs integrated circuit.

FIG. 19 is a sectional view showing a third step of the conventional GaAs integrated circuit.

[Explanation of symbols]

1 semi-insulating GaAs substrate 2 SiO ₂ film 3 resist 4 high resistance GaAs deposition layer 5 high resistance GaAs layer grown at low temperature 6 GaAs active layer 7 source electrode 8 gate electrode 9 drain electrode

Claims (3)

[Claims] 1. A semi-insulating compound semiconductor substrate, a low temperature grown compound semiconductor high resistance layer, an insulating film, a compound semiconductor high resistance deposition layer deposited on the insulating film, and an active layer forming a compound semiconductor element, An active layer forming a plurality of compound semiconductor devices is formed on a semi-insulating compound semiconductor substrate, and the semi-insulating compound semiconductor substrate and the active layer are electrically separated by a compound semiconductor high resistance layer grown at a low temperature, A compound semiconductor device, wherein active layers are electrically separated by the insulating film and a compound semiconductor high resistance deposition layer deposited on the insulating film. 2. A step of forming an insulating film on one main surface of a semi-insulating compound semiconductor substrate, and a region where the surface of the semi-insulating compound semiconductor substrate is exposed by selectively removing the insulating film. A step of performing crystal growth of the compound semiconductor high resistance layer at a low temperature of about 200 ° C. on the entire surface of the semi-insulating compound semiconductor substrate using a molecular beam epitaxy method, and a crystal growth of the compound semiconductor high resistance layer at the low temperature. The compound semiconductor high-resistance layer grown at low temperature in the region where the insulating film is selectively removed by crystallizing the compound semiconductor at a growth temperature of 400 ° C. or higher by using a molecular beam epitaxy method on the entire surface of the semi-insulating compound semiconductor substrate A method of manufacturing a compound semiconductor device, comprising the step of forming an active layer of a compound semiconductor element on the above. 3. A step of crystal-growing a compound semiconductor high resistance layer on a main surface of a semi-insulating compound semiconductor substrate at a low temperature of about 200 ° C. using a molecular beam epitaxy method, and a compound semiconductor high resistance at the low temperature. The step of forming an insulating film on the entire surface of the semi-insulating compound semiconductor substrate on which the crystal growth of the layer is performed, and the surface of the layer on which the crystal growth of the compound semiconductor high resistance layer is performed at a low temperature by selectively removing the insulating film is exposed. And the selective removal of the insulating film by performing crystal growth of the compound semiconductor active layer on the entire surface of the semi-insulating compound semiconductor substrate at a growth temperature of 400 ° C. or higher using a molecular beam epitaxy method. A method of manufacturing a compound semiconductor device, comprising the step of forming an active layer of a compound semiconductor element on a compound semiconductor high resistance layer grown at a low temperature in a region.