JPH0536699A - Single crystal silicon substrate - Google Patents
Single crystal silicon substrateInfo
- Publication number
- JPH0536699A JPH0536699A JP18908191A JP18908191A JPH0536699A JP H0536699 A JPH0536699 A JP H0536699A JP 18908191 A JP18908191 A JP 18908191A JP 18908191 A JP18908191 A JP 18908191A JP H0536699 A JPH0536699 A JP H0536699A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- rear surface
- silicon substrate
- surface side
- silicon carbide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は集積回路用の単結晶シリ
コン基板に関し、特にゲッタリングサイトを裏面に高密
度に形成した単結晶シリコン基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single crystal silicon substrate for an integrated circuit, and more particularly to a single crystal silicon substrate having a back surface with gettering sites formed at a high density.
【０００２】[0002]
【従来の技術】従来、集積回路製造用の単結晶シリコン
基板へのプロセス汚染に対するゲッタリング方法として
は、種々の方法が提案され試みられてきた。例えば、チ
ョクラルスキ法によるシリコン基板に含まれる酸素の析
出を利用したイントリンシックゲッタリング法、基板裏
面への粒子吹き付けによる歪付けを利用したゲッタリン
グ法、基板裏面へのポリシリコンの被着による歪付けを
利用したゲッタリング法、あるいはアルゴン等の不活性
ガスのイオン注入によるゲッタリング法などが主に実施
されてきた。2. Description of the Related Art Conventionally, various methods have been proposed and tried as a gettering method for process contamination of a single crystal silicon substrate for manufacturing an integrated circuit. For example, the intrinsic gettering method utilizing the precipitation of oxygen contained in the silicon substrate by the Czochralski method, the gettering method utilizing the distortion by spraying particles on the back surface of the substrate, and the distortion by depositing polysilicon on the back surface of the substrate. A gettering method utilizing the above or a gettering method by ion implantation of an inert gas such as argon has been mainly performed.
【０００３】[0003]
【発明が解決しようとする課題】上述した従来のゲッタ
リング方法には次のような欠点がある。まず、基板中の
酸素析出を利用したイントリンシックゲッタリング法
は、表面層での酸素析出を防ぐための高温熱処理が必要
であり、これに続いて酸素析出核形成のための低温熱処
理が必要である。これらの余分の長時間の熱処理がこの
ゲッタリング法には必要不可欠のものである。更に、酸
素析出のコントロールが容易ではないという欠点があ
り、安定した効果を維持できない。The conventional gettering method described above has the following drawbacks. First, the intrinsic gettering method utilizing oxygen precipitation in the substrate requires high-temperature heat treatment to prevent oxygen precipitation in the surface layer, followed by low-temperature heat treatment to form oxygen precipitation nuclei. is there. These extra long heat treatments are essential to this gettering method. Further, there is a drawback that the control of oxygen precipitation is not easy, and a stable effect cannot be maintained.
【０００４】また粒子の裏面への吹き付けを利用した歪
付け法は、微粒子が発生するという難点がある。裏面へ
のポリシリコン被着を利用した裏面歪付け法は、被着時
に基板酸素を著しく析出させる核を形成する熱処理が付
随し、プロセス中の酸素析出と重畳して、基板にそりや
スリップを形成し易いという難点がある。またアルゴン
等の不活性ガスのイオン注入法は、ゲッタリング効果が
持続しないという難点がある。Further, the straining method utilizing the spraying of particles on the back surface has a drawback that fine particles are generated. The backside straining method, which uses the deposition of polysilicon on the backside, is accompanied by heat treatment that forms nuclei that significantly precipitate substrate oxygen during deposition, and superposes oxygen precipitation during the process to prevent warping and slipping on the substrate. There is a drawback that it is easy to form. Further, the ion implantation method of an inert gas such as argon has a drawback that the gettering effect does not last.
【０００５】[0005]
【課題を解決するための手段】本発明による単結晶シリ
コン基板は、裏面内にシリコンカーバイド層を形成した
ものである。The single crystal silicon substrate according to the present invention has a silicon carbide layer formed in the back surface thereof.
【０００６】本発明による単結晶シリコン基板は、製造
プロセスの初期の熱処理においてすでに裏面内に充分な
量のゲッタリングサイトとなるシリコンカーバイドを発
生させており、いったん形成されたこのサイトはこれに
続く熱処理でも消えにくく、従って、ゲッタリング効果
はプロセス初期から長期間持続する。イオン注入の加速
電圧及びドーズ量については、基板内のなるべく深い位
置に、固溶限を越えた炭素を注入するという条件から決
定される。熱処理温度は８００℃以上が有効であり、こ
れより高い温度であればより短時間でシリコンカーバイ
ドを形成する事が出来、シリコンカーバイドの形成は赤
外吸収スペクトルから判定できる。カーバイドが比較的
浅い位置に形成され、製造プロセス中の酸化によってゲ
ッタリングサイトが無くなるおそれの有る場合には、裏
面に酸化防止の為の厚い保護膜を付ける方法もとる事が
できる。The single crystal silicon substrate according to the present invention has already generated a sufficient amount of silicon carbide, which is a gettering site, in the back surface in the heat treatment in the initial stage of the manufacturing process, and this site once formed is followed by this. It is hard to disappear even by heat treatment, and therefore the gettering effect lasts for a long period from the beginning of the process. The acceleration voltage and dose of ion implantation are determined under the condition that carbon exceeding the solid solubility limit is implanted at a position as deep as possible in the substrate. It is effective that the heat treatment temperature is 800 ° C. or higher, and if the temperature is higher than this, silicon carbide can be formed in a shorter time, and the formation of silicon carbide can be judged from the infrared absorption spectrum. When the carbide is formed at a relatively shallow position and there is a possibility that gettering sites will be lost due to oxidation during the manufacturing process, a method of attaching a thick protective film for preventing oxidation can be used on the back surface.
【０００７】[0007]
【作用】本発明の単結晶シリコン基板は、裏面近傍にゲ
ッタリングサイトとなるシリコンカーバイド層を形成し
ており、これにより、製造プロセス中に混入する重金属
を表面側素子形成部から除去できる。In the single crystal silicon substrate of the present invention, a silicon carbide layer which becomes a gettering site is formed in the vicinity of the back surface, whereby heavy metals mixed during the manufacturing process can be removed from the front surface side element forming portion.
【０００８】[0008]
【実施例】次に本発明について図面を参照して説明す
る。図１は本発明の一実施例の断面である。The present invention will be described below with reference to the drawings. FIG. 1 is a cross section of an embodiment of the present invention.
【０００９】シリコン基板１の裏面近傍にはシリコンカ
ーバイド層２が形成されている。集積回路の製造プロセ
ス中の重金属汚染は、このシリコンカーバイド層２の付
近でゲッタリングされる。次に製造方法について説明す
る。A silicon carbide layer 2 is formed near the back surface of the silicon substrate 1. Heavy metal contamination during the integrated circuit manufacturing process is gettered near this silicon carbide layer 2. Next, the manufacturing method will be described.
【００１０】表面側は鏡面仕上げ、裏面側はラップ後エ
ッチング仕上げされ加工歪の無い状態になっているシリ
コン基板１を用いた。この基板の裏面に、炭素イオンを
加速電圧１８０ｋｅＶで、１×１０15ｃｍ-2全面に注入
した後、１１００℃４時間の熱処理を加えた。赤外吸収
スペクトルからカーバイド特有のピークが認められ、ま
た、裏面近傍を透過型電子顕微鏡で観察したところ、析
出及び、析出物から発生した欠陥が確認された。欠陥密
度は１０8 ｃｍ-2程度であった。A silicon substrate 1 having a mirror surface finish on the front surface and an etching finish on the back surface after lapping and no processing distortion was used. Carbon ions were implanted on the entire surface of 1 × 10 15 cm −2 at an acceleration voltage of 180 keV on the back surface of this substrate, and then heat treatment was performed at 1100 ° C. for 4 hours. A peak peculiar to carbide was observed from the infrared absorption spectrum, and when the vicinity of the back surface was observed with a transmission electron microscope, precipitation and defects generated from the precipitate were confirmed. The defect density was about 10 8 cm -2 .
【００１１】この基板に素子を製造し、裏面にイオン注
入を行なわない基板と素子歩留りを比較すると、平均し
て２．２倍の歩留りの上昇が確認できた。また、ＭＯＳ
Ｃ−ｔ法によるライフタイムを比較すると、平均して
１ケタ程度のライフタイム増大が認められ、製造プロセ
ス中の重金属汚染のゲッタリングがなされていると推定
された。When a device was manufactured on this substrate and the device yield was compared with that of a substrate on the back surface of which no ion implantation was performed, it was confirmed that the yield was increased by 2.2 times on average. Also, MOS
Comparing the lifetimes by the Ct method, an average lifetime increase of about one digit was observed, and it was estimated that gettering of heavy metal contamination during the manufacturing process was performed.
【００１２】[0012]
【発明の効果】以上説明したように本発明は、裏面に炭
素のイオン注入と熱処理を行いシリコンカーバイド層を
形成する事により、素子歩留りを向上できる効果があ
る。注入イオンとして用いている炭素は基板中で電気的
に不活性であり、また、拡散係数が小さく、表面側に達
する恐れも無い。また使用するシリコン基板は、チョク
ラルスキラ法，フローティングゾーン法，磁場中チョク
ラルスキ法いずれでも良く、製造法によらない。As described above, the present invention has an effect that the device yield can be improved by forming a silicon carbide layer on the back surface by ion implantation of carbon and heat treatment. The carbon used as the implanted ions is electrically inactive in the substrate, has a small diffusion coefficient, and is unlikely to reach the surface side. The silicon substrate used may be any of the Czochralski method, the floating zone method, and the Czochralski method in a magnetic field, regardless of the manufacturing method.
【図１】本発明の単結晶シリコン基板の断面図である。FIG. 1 is a cross-sectional view of a single crystal silicon substrate of the present invention.
１ シリコン基板 ２ シリコンカーバイド層 1 Silicon substrate 2 Silicon carbide layer
Claims (1)
形成した事を特徴とする単結晶シリコン基板。1. A single crystal silicon substrate having a silicon carbide layer formed in the back surface of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18908191A JPH0536699A (en) | 1991-07-30 | 1991-07-30 | Single crystal silicon substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18908191A JPH0536699A (en) | 1991-07-30 | 1991-07-30 | Single crystal silicon substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0536699A true JPH0536699A (en) | 1993-02-12 |
Family
ID=16234996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18908191A Pending JPH0536699A (en) | 1991-07-30 | 1991-07-30 | Single crystal silicon substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0536699A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100434960B1 (en) * | 1996-10-02 | 2004-10-14 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device for trapping impurities using gettering layer |
| CN108074995A (en) * | 2016-11-11 | 2018-05-25 | 英飞凌科技股份有限公司 | Semiconductor wafer and semiconductor devices and its manufacturing method with barrier layer |
-
1991
- 1991-07-30 JP JP18908191A patent/JPH0536699A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100434960B1 (en) * | 1996-10-02 | 2004-10-14 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device for trapping impurities using gettering layer |
| CN108074995A (en) * | 2016-11-11 | 2018-05-25 | 英飞凌科技股份有限公司 | Semiconductor wafer and semiconductor devices and its manufacturing method with barrier layer |
| US10833218B2 (en) | 2016-11-11 | 2020-11-10 | Infineon Technologies Ag | Semiconductor wafers and semiconductor devices with barrier layer and methods of manufacturing |
| CN108074995B (en) * | 2016-11-11 | 2021-02-23 | 英飞凌科技股份有限公司 | Semiconductor wafer and semiconductor device with barrier layer and method for manufacturing the same |
| US11239384B2 (en) | 2016-11-11 | 2022-02-01 | Infineon Technologiesag | Semiconductor wafers and semiconductor devices with barrier layer and methods of manufacturing |
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