JPH0535771A - Vector data processor - Google Patents

Abstract

PURPOSE:To provide a vector processor which does not require the generation of mask vector by simplifying read/write operation to a vector register with regard to element data. CONSTITUTION:This processor is provided with an address control circuit 160 which controls inter-element distance of element data which is specified by an external setting signal, a reading interval setting register 130 which outputs the value controlled by the address control circuit and a writing interval setting register 140. When the element data is read out from a vecto register 100, the value obtained by adding the output value of the reading interval setting register 130 to a previous address value through an address calculator 150 is outputted from an address register 110 as an address value, and in the case of writing in, the address value obtained by adding the output of the writing interval setting register 140 to a previous address value through an address calculator 151 is written in so as to be outputted from an address register 120.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector data processing device, and more particularly to a vector data processing device for transferring element data between a vector register, an arithmetic unit and a main memory.

[0002]

2. Description of the Related Art A conventional vector data processing device is shown in FIG.
Vector registers 10 and 11, which partially store the data output from the main memory or the arithmetic unit 50,
Read / write address registers 20 and 21 for designating addresses of data to be stored in the vector registers 10 and 11, respectively, an element data input selection circuit 30 for selecting an input by an external input selection command, and an external output selection command. It is composed of an element data output selection circuit 40 for switching the output destination according to and an arithmetic unit 50.

The vector registers 10 and 11 are registers for holding a plurality of element data, and usually a plurality of vector registers are provided. The read / write address registers 20 and 21 indicate the location of the element data when reading the element data in the vector registers 10 and 11 and when writing the element data in the vector registers 10 and 11 described above. The address register normally has a +1 count function of clearing the value to "0" when an external setting command is input and increasing the address value by 1 when storing one data in the vector register 10 or 11. . The element data input selection circuit 30 selects and reads either element data from a main memory (not shown) or a calculation result from the arithmetic unit 50 by an external input selection instruction and reads it into the vector register 10 or 11. And has a function of distributing. The element data output selection circuit 40 is the vector register 1 described above.
The element data read from 0 and 11 is controlled by an output selection signal applied from the outside, and has a function of selecting and distributing to the main memory (not shown) or the arithmetic unit 50.

In the conventional vector data processing device having such a configuration, in order to perform an operation on vector data arranged at a constant interval in the main memory, element data from the main memory to the vector registers 10 and 11 are used. Method, the element distance is specified and only the element data to be operated is transferred to the vector registers 10 and 11 to perform the operation, or all the continuous areas including the element data to be operated are transferred to the vector register 10 11 and 11 are loaded, a mask vector is generated and given to element data other than the calculation target, and calculation with a mask is performed.

[0005]

In the above-described conventional vector data processing device, in order to perform vector operation on vector data arranged at a constant interval in the main memory, inter-elements are loaded at the time of loading to the vector register. There is a method of specifying the distance, loading only the element data to be operated on the vector register, and performing the operation. However, in this case, access to the main memory is usually made to discontinuous addresses, so that there is a disadvantage that the throughput of the memory is lowered due to bank conflict or the like.

On the other hand, in the method of generating a mask vector and performing a masked operation, it is necessary to perform mask generation processing.
Moreover, since the vector length is required to be longer than the originally required length, there is a drawback that the execution time becomes long.

[0007]

The vector data processing device of the present invention comprises vector data storage means for temporarily holding all or part of the element data of the vector data stored in the main memory, and Write address setting means for writing write data to the vector data storage means at an arbitrary fixed interval set by a setting signal input from the outside, and setting the element data input from the outside from the vector data storage means And a read address setting means for reading at an arbitrary fixed interval set by a signal.

[0008]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a vector data processing device of the present invention. Vector register 10 holding a plurality of ordered element data
0, a read address register 110 indicating the location of element data for reading element data from the vector register 100, a write address register 120 indicating the location of write data for the vector register 100 described above, and the vector described above. When reading / writing to the register 100,
A read interval setting register 130, a write interval setting register 140, and a read address register 1 for setting a distance between elements of element data, that is, an address increment value
Address adders 150 and 151 for adding the address value in 10 and the address increment value in the read interval setting register 130, and the address value in the write address register 120 and the address increment value in the write interval setting register 140, respectively, and A read address register 110, a write address register 120, a read interval setting register 130, an address control circuit 160 for initializing the write interval setting register 140 and the read interval setting register 130 according to a setting signal from the outside, and an input added from the outside. An element data input selection circuit 170 for selecting and inputting load data output from the main memory or an operation result output from an arithmetic unit to the vector register 100 controlled by the selection signal, and an output selection signal applied from the outside. Controlled and vector register 100
It has an element data output selection circuit 180 for outputting the element data read from the main memory or an arithmetic unit (not shown).

The operation of this embodiment is as follows.

For example, when performing an operation on complex data, the data in which the real part and the imaginary part are combined is loaded from the main memory onto the vector register 100. This is because normally real data and imaginary data are alternately arranged in the main memory of complex data. When only the real number part or only the imaginary number part is to be calculated, in the present invention, the vector register 100 holding the element data to be calculated is designated by an external instruction, and the read start address and the element of the vector register 100 are designated. The distance is applied to the address control circuit 160 from the outside, and the address control circuit 1
The read address register 110 and the read interval setting register 130 are initialized via 60. Similarly, the vector register for storing the calculation result, the write start address, and the inter-element distance are also specified by an externally added instruction. When the calculation result is written back to the vector register 100, the write start address and the inter-element distance are set to the write address register 12 via the address control circuit 160.
0 and the write interval setting register 140 are initialized. The vector register 100 outputs the element data at the location designated by the read address register 110 to the element data output selection circuit 180. The read address register 110 is sequentially set by adding the address increment value in the read interval setting register 130 to the address value stored in the read address register 110 by the address adder 150 for sequentially reading the element data. To be done. As a result, the element data in the vector register 100 is read at a constant interval by the specified vector length, and the read element data is sent to the main memory or the arithmetic unit by the element data output selection circuit 180. The selection of whether to output to the main memory or the arithmetic unit is made by an output selection signal applied from the outside.

On the other hand, when the operation result output from the operation unit or the load data output from the main memory is written in the vector register 100, the write address register 1
Writing of the element data is started at the time when the first element data is output from the element data input selection circuit 170 to the location designated by 20. Similarly to the read address register 110, the write address register 120 uses the address adder 151 to sequentially write the element data, and the write address register 1
A value obtained by adding the address increment value in the write interval setting register 140 to the address value stored in 10 is sequentially updated and set.

For setting the interval value in the write interval setting register 140, an external setting signal is used by the address control circuit 160.
And is set by the output of the address control circuit 160. As a result, the element data is written in the vector register 100 at regular intervals for the specified vector length.

Although one vector register has been described in the present embodiment, the present invention is not limited to one vector register, and it is now applicable to a vector data processing device having a plurality of vector registers. It is clear from the above explanation.

[0015]

As described above, according to the present invention, the vector data storage means (vector register) is provided with the address setting means capable of reading / writing the element data at an arbitrary fixed interval. Registers can be used flexibly, and store / load instructions can be used to perform partial vector operations on element data stored in vector registers via main memory, or executed without generating a mask vector. Since this is possible, there is an effect that it can be performed without increasing the vector length of the data to be calculated.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a vector data processing device of the present invention.

FIG. 2 is a block diagram showing an example of a conventional vector data processing device of this type.

[Explanation of symbols]

100 vector register 110 Read address register 120 write address register 130 Read interval setting register 140 Write Interval Setting Register 150-151 Address adder 160 address control circuit

Claims (3)

[Claims] 1. Vector data storage means for temporarily holding all or part of the element data of the vector data stored in the main memory, and the element data input from the outside by the vector data storage means. And a read address setting means for reading at an arbitrary fixed interval set by the setting signal. 2. Vector data storage means for temporarily holding all or part of the element data of the vector data stored in the main memory, and write data for the vector data storage means are inputted from the outside. A vector data processing device characterized by comprising write address setting means for writing at a fixed interval by a setting signal. 3. Vector data storage means for temporarily holding all or part of the element data of the vector data stored in the main memory, and write data for the vector data storage means are inputted from the outside. Write address setting means for writing at a constant interval by a setting signal, and read address setting for reading the element data from the vector data storage means at an arbitrary constant interval set by a setting signal input from the outside. And a vector data processing device.