JPS59121524A - Information holding system of information processor - Google Patents

Abstract

PURPOSE:To make two or more kinds of information holding part capacity variable to give flexibility to information processing, by providing a means which increases or reduces selectively the holding capacity of the information holding part and changing variably the holding capacity of the information holding part. CONSTITUTION:The means which increases or reduces selectively the holding capacity of the information holding part. For example, an instruction inputted to a buffer 6' and two data used by this instruction are outputted from the buffer 6', and the instruction is transmitted immediately to an instruction transmitting circuit through an instruction register iR0 or the like if ''0'' appears on a line 29. Addresses which designate data registers DRF and DRS which are not used under the control of a flag control circuit 5 are transmitted to the instruction transmitting circuit through an address register AR0 or the like. Two data are stored in auxiliary information processing parts SRF and SRS by connection changing means 50 and 52, and output signals are transmitted to an operating device through selectors 60 and 64.

Description

Detailed Description of the Invention (I) 0 Technical Field of the Invention The present invention relates to information retention in an information processing device in which the information retention mode is improved by providing means for selectively increasing or decreasing the retention capacity of two or more types of information retention units. Regarding the method.

(2) Technical Background Generally, when data processing is performed in the field of information processing devices such as scientific and technical computers, a plurality of instructions for the processing and data processed by these instructions are temporarily transferred from memory to an information storage unit. In some cases, a method is adopted in which the actual processing begins after the ring 9 is issued.

In such a case, if the capacity of the information holding unit is kept constant, even if a program processing request arises that requires more instructions or data to be held in the information holding unit, it will not be possible to meet the request. Therefore, there has been a demand for the development of technical means to solve these problems.

(3) Prior Art and Problems An example of the above-mentioned conventional information holding means is shown in FIG. In this information holding means, instructions and data are fetched from an external device 1 to a command fetching circuit 2, and the instructions are sent to the arithmetic processing unit in a predetermined order (order determined by SEL) via a selector 4 of a command sending circuit 3. (not shown), the data used in the instruction is transferred from the data registers DRF and DR8 to the arithmetic unit under the control of the flag control circuit 5.

Then, the instruction register (iR
l, iR2, iR3) is connected to an external device l.
The instruction held in the buffer 6 is taken out from there, and the instruction sent to the instruction register iR8 is sent to the clock signal CL1. K is set in response to CL2 or CL3, and the corresponding address register (A
One of R1 to AR3) Hair address register ARo
The address of the person Ro is sent in response to the clock signal CLo.
One of the RRF responses whose flag is off is sent.

On the other hand, data is sent from the address register AR (i=1.2.3) corresponding to the issued command to the flag control circuit 5 via the selector 7 and line 8, and from there via line 9. data register DRF
The address is sent to DRs, and the two data there are sent to the arithmetic unit as described above, but the write address of each data to data registers DRF and DR8 is A.
Given by Ro.

In this way, iR(+-t R3 is only for instructions, ARO
;.

Since AR3 is allocated only to addresses and only DRF and DR8U data, the storage capacity for instructions or data remains constant, and it is desirable for such information processing means to be able to take in more instructions or data. This results in not only being unable to cope with such data processing demands, but also a decline in usage efficiency of the holding section.

(4) Purpose of the Invention The present invention was devised in view of the drawbacks of the conventional system as described above, and its purpose is to provide flexibility in information processing by varying the amount of information holding means of 2 m or more. An object of the present invention is to provide an information retention method for an information processing device that can be used.

(5) 1 Structure of the Invention And, this object is to provide an information processing apparatus having two or more types of information holding sections, and to provide a means for selectively increasing/decreasing the storage capacity of the information holding sections, and to use the means to selectively increase/decrease the storage capacity of the information holding sections. By causing a variable change in the holding capacity of the holding part,
achieved.

(6) Embodiments of the Invention The present invention will now be described in detail with reference to the accompanying drawings.

FIG. 2 shows an embodiment of the invention. This embodiment basically differs from the apparatus shown in FIG. 1 in the following points.

The difference is shown in Figure 1.In the conventional configuration, the instruction register iR
The output of the address register ARo is connected directly to the selector 21 by the instruction connection change circuit means 20 or via the data register D 11 F3, and the output of the address register ARo is connected directly to the selector 21 by the address connection change circuit means 22. or through a part of the data register DR83 to the selector 23, and these selectors 22 and 23 are connected to the command generation circuit 3 (
(see FIG. 1).

In addition, storage access to data registers T) RF and DR3 is provided by the decoder 24. This decoder is connected to address register ARo.

The outputs of DRFO to DRF3 are connected to the selector 25, and the output 26 of the lag control circuit 5 in FIG. 2, which corresponds to the output of the flag control circuit 5 of the conventional configuration in FIG. The contents of the data registers D group 0 to DRF3 are selected and sent to an arithmetic unit (not shown) according to the output signal appearing at .

Further, the outputs of DRO to DR83 are connected to the selector 27, and the output 26 of the flag control circuit 5'' is connected to the selector 27, and the contents of the data registers DR8o to DR83 are selected by the output signal appearing at the output 26 and sent to the arithmetic unit. configured to be sent.

The above-mentioned instruction connection change circuit means 2o is an instruction register iRo.
and connected to the output of buffer 6, whose output 'eDRF
A selector 28 connected to 3 and a line 29 connected to this selector and sending a connection change control signal to select it.
and an AND gate 31 which connects this line 29 to the gate control input via an inverter 30 (this AND gate includes the corresponding output of the decoder 24 and the clock signal CLD).
F line 32 is connected. ) and the AND gate 33 which connects the above line 29 to the gate control input (the AND gate of C is connected to the clock signal CLo line), and the outputs of the AND gates 31 and 33 are connected. It consists of an or gate 34. The output of OR gate 34 is connected to the storage control input of DR,i3.

Further, the selector 35 is connected to the address connection change circuit means 22U7, the address register AR8, and the output of the buffer 6, and the above-mentioned line is connected to this selector 35 and sends a connection change iti control signal to select it. 29
and the AND gate 36 which connects this IfJ29 to the gate control input via the inverter 30 (the corresponding output of the decoder 24 and the clock signal CLDs line 37 are connected to this AND gate), and the above line. 29 to the gate control input (to which the clock signal CLo line 33 is connected) and the outputs t- of AND gates 36 and 38.
1 & the following OR gate 39. The output of OR gate 39 is connected to the storage control input of DR83.

40.41.42il-t and gate these 7
under the control of the clock signal CLI)F,
Corresponding output signal fr DRFO of decoder 24.

DRFl is for supplying to the storage control input of the DR section 2. Further, 43, 44, and 45 are AND gates, and these AND gates convert the corresponding output signals of the decoder to DR80 and DR81 under the control of the clock signal CLD8.
, Q for supplying to the storage control input of DR82.

The output of the buffer 6, which is the same as the buffer 6 of the conventional configuration in FIG.
Connected to 8O to DR82.

The address output ld of the flag control circuit 5 is connected to the address register ARo via the line 46k, and the line 8 is connected to the input of the circuit 5+ (similar to the device in FIG. 1).

Next, the operation of the configuration device shown in FIG. 2 will be explained.

The command input to the buffer 6 and the two data used for it are output from the buffer 6. The command is first input to the command register fRO, and the two data are as shown in FIG. As described above, under the control of the flag control circuit 5, among the DR addresses, an address indicating a DR part whose flag is off, that is, which is not used, is set in the address 7 register AR6 via the line 46. The address is decoded by the decoder 24, and the output signal indicates DRp i , DR31 (l is 0 to 3
or 0 to 2, and this difference will become clear from what will be described later. ).

That is, this difference is that when the instruction connection change circuit means 20 and the address connection change circuit means 21 are not in the holding capacity increase mode, and when the o'' signal is supplied on the 9 line 29, the selector 28.35 are respectively I Ro and A R
The two data from buffer 6 are selected separately without selecting the output of o. At the same time, the gate operation of the circuit means 2o and 21 at 33.38 does not occur, but instead the gate operation at 31.36 occurs. The DR section, DR section 0 to DR 8 are used for storing data in the same manner as the operation of the device 4 in FIG. 1.

However, when "1" is supplied on the line 29, the output of the selector 28.35U buffer 6 is not selected, but the corresponding registers iRo and ARo are selected, and at the same time Antogame) 31.
36 gate operations, but instead causes AND gates 33.38 gate operations, causing DRFa to I.
Interpose between RQ and selector 21, and interpose a part of DR,3 between ARo and selector 23 (
ff! : See Figure 3).

As is clear from the above, this type of connection change can be used as DRF, DR8.
"'-DRF 2 , I) RSO ~ DR is decreased to 82 (see FIG. 3).

Due to this change in the use of circuit elements, the number of instruction registers and address registers increases, while the number of data registers decreases.

As a result, the number of instructions that can be fetched can be increased, the processing performance of instructions that use only internal registers as operands can be improved, and a decrease in DR usage efficiency can also be prevented in this case. Therefore, the present invention provides a means for arranging software-operated software into a hardware configuration that is more suitable for the software.

Next, another embodiment of the present invention will be described with reference to FIG.

This embodiment is basically the same as the embodiment in FIG.
This embodiment differs from the embodiment shown in FIG. 2 in that the above-mentioned increase or decrease in the number of information holding units is caused by connection change using connection change means similar to the above-mentioned connection change means of the auxiliary information holding unit.

That is, the auxiliary information holding section in the embodiment shown in FIG.
and the selector 51.
'3 and is configured to be used as register SR
Reference numeral 8 denotes a second connection change circuit, which is arranged to be interposed between the ARo and the selector 53 by the path means 52 or used as the DR 83.

The first connection change circuit means 50 includes a selector 54 which selects and outputs the output of iRo and the output of the bumper 6 by a connection change control signal on a line 29, and a decoder 56 which connects the line 29 via an inverter 55 and which will be described later. AND gate 57 having its inputs connected to the first output of and to line 32, AND gate 58 having its inputs connected to lines 29 and 33, and having its inputs connected to the outputs of these AND gates 57, 58. It consists of ORGATE 59.

The output of OR gate 59 is connected to the storage control input of register SRp. Further, the output of the selector 54 is connected to the input of the register SRF.

The output of the register SRF is connected to one input of the selector 51 (the output of iRo is connected to the other input) and one input of the selector 60.

Second connection change circuit means. 52 has all inputs connected to the output of ARo, the output of bumper 6, a selector 61 that selects and outputs the output according to the connection change control signal on the t line 29, the first output of the decoder 56, the line 37, and the output of the inverter 55. and an OR gate 63 whose inputs are connected to the outputs of AND gates 62 and 58.

The output of OR gate 63 is connected to the storage control input of register SRs. Further, the output of the selector 61 is connected to the input of the register SR8.

The address output of register SR8 is connected to one input of selector 53 (the output of 1dARo is connected to the other input), and its data output is connected to selector 6.
-h is connected to one input of 4.

ARo is connected to the output of input uARo of decoder 56;
The input of DR is the unused DR section (DR
(FO-DRF2, DRSO-DR82) is connected to a line 65 that outputs the address of the flag control circuit 5 (FO-DRF2, DRSO-DR82).
56 input line 8 (see FIG. 1) is connected.

).

, the decoder 56 has a line 66 connected to the DR, which outputs all data stored at 1/s to the DR. or,
A line 32 is connected to DRF, and a line 37 is connected to DR8.

The flag control circuit 5 also has a line 67 for outputting the address of data to be read from the DR, and this line is connected to the DR and selectors 60 and 64.

Next, the entire operation of this embodiment will be explained.

As in the embodiment shown in FIG. 1, the instruction input to the buffer 6 and the two data used therein are output from the buffer 6, and if 0'' appears on the line 29, one of the instructions is iRO 'c is immediately supplied to the command generation circuit, and under the control of the flag control circuit 5, among the DR addresses, the address indicating the unused DR section whose flag is turned off is connected to the line 65. After ARo'
While the two data are supplied to the command generation circuit 3 via connection change circuit means 5Q, 52, register SRF is incorporated into DRF3 of DRF, and register SR8 is incorporated into DR8. DT? , s3 as D
It is stored in the DR as if it were incorporated into the BS, and from there it is given to the arithmetic unit via the selectors 60 and 64 (fifth
(see figure).

Such incorporation of the SRF, SR8, into the DR is caused by selection of the output of the buffer 6 by the selectors 54 and 61, and generation of the gate operations of the AND gates 57 and 62.

If "1" appears on the line 29, the connection change circuit means 50.52 causes the register SRF to change to i.
Interposed between RO and selector 51, register S
As R8 is interposed between ARo and the selector 53, the command is supplied through the register iRo and SRF, and the address is supplied through the register ARo and SR8 to the command issuing circuit 3 (see FIG. 1) (see FIG. 6). ). The two pieces of data are stored in the DR with its original capacity, and the selector 60.
64 and is supplied to the arithmetic unit.

Such intervening processing of S'RF-8R8 is performed by the selector 54.
This is caused by the selection of the IRo output by the selector 61 and the AR0 output by the selector 61, and the gate operation of the AND gate 58.

In this manner, also in this embodiment, each iH information holding section can increase or decrease its capacity as needed. Therefore,
The same effect as the embodiment in FIG. 2 can be obtained.

In each of the above embodiments, the capacity increase or decrease a° of the information holding section is explained in the case of one unit capacity, but the invention is not limited to this, and the capacity can be increased or decreased by any number of unit capacities. It is constructed like this.

(7) Effect of zero invention As described above, according to the present invention, ■Variably change the capacity of two or more types of information holding parts.

(2) In particular, when the information holding section consists of an instruction holding section and a data holding section, the holding capacity of instructions and data can be set to the optimum amount required on the software.

(2) Therefore, effects such as adjusting the hardware configuration to suit the software can be obtained.

[Brief explanation of the drawing]

Fig. 1 shows an example of a conventional device, Fig. 2 shows an embodiment of the present invention, Fig. 3 shows an operational mode of the embodiment of Fig. 2, and Fig. 4 shows an example of the present invention. A diagram showing another embodiment,
5 and 6 are diagrams showing the operation mode of the embodiment of FIG. 4. FIG. In the figure, 6' is a buffer, iRo is an instruction register, ARo
is an address register, 20 is an instruction connection change circuit means,
22 is address connection change circuit means, 21.23, 25
．． 27, 60.64 is a selector, 24.56 is a decoder, 5 is a flag control circuit, 50 is a first connection change circuit means, 51 is a second connection change circuit means, DRF is a first data reception device, DR8 is the second data register, 5R4
1, SR8 is an auxiliary information holding section. Patent applicant Fujitsu Limited

Claims (3)

[Claims] (1) In an information processing device having two or more types of information holding sections, a means for selectively increasing/decreasing the holding capacity of the information holding section is provided, and the means allows variable changes in the holding capacity of the information holding section. An information retention method for an information processing device 4, characterized in that the information processing device 4 is configured to hold the information. (2) The means is configured to selectively change the connection of a part of the information holding part of one of the two or more types of information holding part to use it as part of the information holding part of another type. An information retention system for an information processing device according to claim 1, characterized in that: (3) The means described in claim 1 is characterized in that the means includes an auxiliary information holding section, and is configured to selectively change connections so as to use this as a part of the information holding section. information retention method for information processing equipment.