JPH0535618B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to forward and backward protection means for a digital signal train input to a frame synchronization circuit.
The present invention is mainly used for frame synchronization detection in PCM communication devices.

[Conventional technology]

FIG. 3 shows the configuration of a conventional frame synchronization circuit. A digital signal string 500 having an m-bit frame synchronization word is shifted by m bits in an m-bit shift register 4 by a clock 510 synchronized with this signal string 500. shift register 4
The decoder 5 determines whether or not the Q ₁ to Q _n outputs 140 are synchronization words. This judgment output 150
is input to an N-bit shift register 6 whose shift clock is a frame synchronization position signal 520 indicating the time point at which the frame synchronization word is to be checked.
Here, the synchronization protection is set to N ₁ stage forward and N ₂ stages backward (N ₁ ,
N ₂ ≦N), the state where there is no frame sync word at the time when the frame sync word should be checked is N ₁
If the number is consecutive, the output of shift register 6 ~ _N1
160 are all "1" and their logical value is "1", so the flip-flop 9 is reset and the decision output 190 becomes "0". Also, if the frame sync word is present N _two times in a row,
Since the outputs Q ₁ to _{Q NZ} 161 of the shift register 9 all become "1" and their AND output 180 also becomes "1", the flip-flop 9 is set and the judgment output 190 becomes "1". Furthermore, when the frame synchronization pattern does not arrive consecutively less than N ₁ times or when it arrives consecutively less than N ₂ times, both the R and S inputs of the flip-flop 9 are "0" and its output 190 does not change. .

This circuit is used for synchronization pattern detection in PCM communication equipment, and it sends out a synchronization detection output only when the synchronization pattern is detected N ₁ times in a row, and synchronizes only when the synchronization pattern is not detected N ₂ times in a row. By sending out an undetected output, stable synchronization judgment is performed without following synchronization disturbances caused by spurious signals each time.

[Problem that the invention seeks to solve]

Front N ₁ stage realized with this kind of circuit configuration,
Reset-type frame synchronization protection circuit with _two backward N stages has the following problems: (1) It is difficult to change the synchronization word, which requires changing the decoder, and (2) It is difficult to change the number of forward and backward protection stages. , it has disadvantages such as the need to change the shift register and (3) the circuit is complex.

SUMMARY OF THE INVENTION An object of the present invention is to improve these drawbacks, and to provide a frame synchronization circuit that can easily change the frame synchronization word and the number of forward and backward protection stages with a simple circuit configuration.

[Means for solving problems]

The present invention provides a shift register that converts a digital signal string having a frame synchronization word of m bits into a parallel signal of every m bits, and a shift register that converts a digital signal string having a frame synchronization word of m bits into a parallel signal of _every m bits, and frame synchronization, which outputs a value and outputs another logic value when a state in which a synchronization word is not detected in this parallel signal N ₂ times in a row, and a judgment means of judgment logic that holds the previous output at other times. As a means for solving the above-mentioned problem in the judgment circuit, the judgment means uses at least m+n+2 bits (n is an integer greater than or equal to the larger of _N1 and _N2 ).
A programmable read-only memory including an address input of and an output of n+2 bits, and a frame period position signal of the n-bit output of this read-only memory is latched, and this output is the address of the remaining n bits of the read-only memory. an n-bit flip-flop connected to the input; the remaining two bits of the read-only memory are connected back to the remaining two bits of its address input;
One of the bits is connected to the judgment output,
The read-only memory outputs one logic value in order from the first terminal of the n-bit output each time a synchronization word pattern is input to the m-bit address input, and continuously outputs _N1 synchronization words. When a pattern is input, one logic value is output to the judgment output terminal, and each time an asynchronous word pattern is input to the m-bit address input, other logic values are sequentially output from the first terminal of the n-bit output. The configuration is such that another logical value is output to the judgment output terminal by successively inputting N ₂ asynchronous word patterns, and the read-only memory has a logic value corresponding to the judgment logic. A pattern is stored, and as this recorded pattern, one of the address inputs from the shift register is a synchronous word pattern, and one of the n-bit address inputs from the flip-flop is a synchronous word pattern.
If _N1 bit is one logical value and one bit other than the judgment output connected as feedback is another logical value, the one logical value is output as the judgment output, and the address input is Of these, the input from the shift register is not a synchronous word pattern, and the AND of N2 bits of the n-bit address inputs input from the flip _- flop is another logical value, which is different from the judgment output connected to the feedback circuit. The present invention is characterized in that a pattern of judgment logic is stored that outputs the other logical value as the judgment output when the other one bit of the bit is one logical value.

[Effect]

The present invention provides parallel synchronization words at the address inputs of a programmable read only memory (hereinafter referred to as "PROM"). The PROM is programmed so that when this synchronization word is a correct synchronization word pattern, one logical value will appear in one bit of the first output. This first output 1 bit is touched at the timing of the frame synchronization position signal and fed back to another address 1 bit of the PROM. It is programmed so that when this address has the above-mentioned one logical value and the parallel synchronization word is a correct synchronization word pattern, one logical value will appear on one bit of the second output. This output is latched at the frame sync position signal timing,
It is fed back to yet another address 1 bit of the PROM. If this continues _N times, the PROM output becomes a synchronization determination signal.

The same thing happens with the opposite logic when the parallel sync word is incorrect N ₂ times.

Further, the outputs of the remaining two bits of the PROM are connected in feedback to the address input, thereby performing an operation of holding the outputs.

In this configuration, the only element is a PROM flip-flop, which simplifies this configuration and further
By changing the contents of PROM, it is possible to easily change the synchronization word and the number of protection stages.

〔Example〕

Hereinafter, a circuit implementing the present invention will be explained based on the drawings.

FIG. 1 is a block configuration diagram showing the configuration of this embodiment circuit. Figure 2 is provided in this example circuit.
This is a comparison table of data written to the PROM and addresses, and the symbol F in the figure indicates a frame synchronization word, and the symbols indicate other than the frame synchronization word.

Next, the configuration of this embodiment circuit will be explained based on FIG.

This embodiment circuit is a frame synchronization circuit in which the number m of frame synchronization words is m=8, the number N ₁ of forward protection stages is N ₁ =4, and the number N ₂ of backward protection stages is N ₂ =2. This example circuit includes a shift register 1,
PROM 2, flip-flop 3, digital signal string input terminal 50, clock signal input terminal 51, frame synchronization position signal input terminal 52,
and a determination output terminal 53. Here, shift register 1 has an 8-bit configuration, and PROM 2 has 128 bits.
It has a storage capacity of kilobytes, and the flip-flop 3 has a 4-bit configuration.

A digital signal string input terminal 50 is connected to a first input D of the shift register 1, and a clock signal input terminal 51 is connected to a second input C of the shift register 1. i-th of shift register 1 (however,
The output of 1≦i≦8) is connected to the i-th input of PROM2, and the j-th input of PROM (where 0≦j≦3)
The output of is connected to the j-th input of flip-flop 3.

Frame sync position signal input terminal 52 is connected to the fifth input of flip-flop 3. The first output Q ₉ of flip-flop 3 is connected to the ninth input A ₈ of PROM2, the second output Q ₁₀ of flip-flop 3 is connected to the tenth input A 9 of PROM2, and the third output of flip-flop 3 is connected to the ninth input A ₈ of PROM2. Output Q ₁₁ is
The eleventh input A ₁₀ of PROM2 is connected, and the fourth output Q ₁₂ of flip-flop 3 is connected to the twelfth input A ₁₁ of PROM2. The fifth output O ₄ of PROM2 is connected to the judgment output terminal 53 and the thirteenth input A ₁₂ of PROM2, and the sixth output O ₅ of PROM2
is connected to the fourteenth input A ₁₃ of PROM2.

Next, the operation of this embodiment circuit will be explained based on FIG.

In the 8-bit shift register 1, the 8-bit frame synchronization word is shifted one bit at a time by a clock 510 synchronized with the digital signal string 500 containing it, and a signal 110 is output.
In PROM2, the output signal 110 of shift register 1 is input to its address input terminals _A0 to _A7 ,
When this input matches the sync word,
Output 121 of terminal O ₀ of PROM2 becomes "1",
The PROM 2 is programmed to output "0" when there is no match. moreover
When the input 131 of the address input terminal A ₈ of the PROM 2 is "1", the output 122 of the terminal O ₁ becomes "1", and when this input is "0", "0" is output. From terminal O ₂ , address input terminal A ₉ input 1
32, the signal 123 is output, and the terminal O ₃
A signal 124 corresponding to the input 133 of the address input terminal A ₁₀ is outputted from the address input terminal A 10 . Output 12 of terminal O ₄
5 is address input terminal A ₁₃ input 126 is "0"
Inputs 131 to 13 of address input terminals A ₈ to _{A 11}
It becomes “1” only when all of 4 are not “0”,
In other cases, "0" is output. In addition, the output 126 of the terminal _O5 is output from the address input terminals _A8 and _A9 when the input 125 of the address input terminal _A12 is "0".
It becomes "1" only when the logical product of inputs 131 and 132 is "0", and becomes "0" in other cases.

As shown above, the output for each address is
Write to PROM2 and output 12 of PROM2
1 to 124 are respectively input to the D inputs D ₁ to _{D 4} of the 4-bit D flip-flop 3, and latched with the frame synchronization position signal 520 indicating the point at which the frame pattern is to be inspected.
are connected to address input terminals A ₈ -A ₁₁ of PROM 2, outputs 122 - 124 operate like outputs of a shift register when input 131 is used as a data input and frame synchronization position signal 520 is shifted clocked. Also, since the terminal _O4 is connected to the address input terminal _A12 and the terminal _O5 is connected to the address input terminal _A13 , the output 125 uses the inputs 131 and 132 as set inputs, and inputs the inputs 131, 132, and 133. This becomes the Q output of an R-S type flip-flop whose reset input is the negative value of the AND of the inputs 134 and 134. That is, the output 125 of the terminal _O4 becomes "0" when it is determined that the synchronization is out, and becomes "1" when it is determined that the synchronization state is established.

Although this invention has been described above using an example circuit, this is for explaining this invention and is not intended to limit this invention, and this invention extends to the entire scope of the claims.

〔Effect of the invention〕

As explained above, the present invention simplifies the circuit configuration and improves reliability.Furthermore, when changing the frame synchronization word, the number of forward protection stages, and the number of backward protection stages, the present invention only needs to rewrite the contents of the PROM. This has the effect of making setting operations easier.

[Brief explanation of the drawing]

FIG. 1 is a circuit connection diagram showing the configuration of a circuit according to an embodiment of the present invention. FIG. 2 is provided in the circuit according to the embodiment of the present invention.
Comparison table of data written to PROM and addresses. FIG. 3 is a circuit connection diagram showing the configuration of a conventional circuit. 1, 4, 6...shift register, 2...
PROM, 3, 9... flip-flop, 5...
Decoder, 7, 8...AND gate, 50...Digital signal string input terminal, 51...Clock signal input terminal, 52...Frame synchronization position signal input terminal, 53...Judgment output terminal.

Claims (1)

[Claims] A shift register that converts a digital signal string having a frame synchronization word of 1 m bits into a parallel signal of every m bits, and a state in which a synchronization word is detected in the parallel signal.
Judgment logic that outputs one logical value when it occurs N _once in a row, outputs another logical value when the synchronization word is not detected in this parallel signal _twice in succession, and holds the previous output otherwise. In the frame synchronization determination circuit, the determination means comprises at least m+n+2 bits (n is N ₁ and
A programmable read-only memory including an address input (an integer greater than or equal to the larger of _N2 ) and an n+2 bit output, and an n-bit output of this read-only memory are latched at the timing of the frame period position signal, and the output is an n-bit flip-flop, each connected to the remaining n-bit address inputs of the dedicated memory; the remaining 2 bits of the read-only memory are feedback connected to the remaining 2 bits of its address input; One bit of the bits is connected to the judgment output, and the read-only memory reads one logic value sequentially from the first terminal of the n-bit output each time a synchronization word pattern is input to the m-bit address input. By continuously inputting _N1 synchronous word patterns, one logic value is output to the judgment output terminal, and each time an asynchronous word pattern is input to the m-bit address input, the n Other logical values are sequentially output from the first terminal of the bit output, and other logical values are outputted to the judgment output terminal by consecutively inputting _N2 asynchronous word patterns. A pattern corresponding to the above judgment logic is stored in the read-only memory, and this recorded pattern is such that among the address inputs, the input from the shift register is a synchronous word pattern, and the n-bit input from the flip-flop is a synchronous word pattern. Outputting the _one logical value as the judgment output when N1 bits of the address input are one logical value and one bit other than the judgment output connected as feedback is another logical value, Among the address inputs, the input from the shift register is not a synchronous word pattern, and the AND of _N2 bits of the n-bit address inputs input from the flip-flop is another logical value,
Frame synchronization characterized in that a pattern of judgment logic is stored in which the other logic value is output as the judgment output when one bit other than the judgment output connected as feedback is one logical value. circuit.