JPH05343853A - Formation through hole in multilayer insulating film - Google Patents

Formation through hole in multilayer insulating film

Info

Publication number
JPH05343853A
JPH05343853A JP14777092A JP14777092A JPH05343853A JP H05343853 A JPH05343853 A JP H05343853A JP 14777092 A JP14777092 A JP 14777092A JP 14777092 A JP14777092 A JP 14777092A JP H05343853 A JPH05343853 A JP H05343853A
Authority
JP
Japan
Prior art keywords
insulating film
hole
conductor
forming
multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14777092A
Other languages
Japanese (ja)
Inventor
Sen Minemura
践 峰村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14777092A priority Critical patent/JPH05343853A/en
Publication of JPH05343853A publication Critical patent/JPH05343853A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a forming method for a through hole capable of avoiding the cracking in a conductor at the junction point of multilayer insulating film. CONSTITUTION:Within this through hole making method in multilayer insulating film, the through hole 7a provided in the lower insulating film 6a is made larger than the through hole 7b provided in the upper layer insulating film 6b so that the upper layer insulating film 6b may be inserted into the through hole 7a in the lower layer insulating film 6a.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はポリイミド樹脂からなる
絶縁膜で絶縁された下層導体と上層導体を具えてなる混
成集積回路基板に係り、特に積層された複数の膜からな
る多層絶縁膜に下層導体と上層導体を接続するスルーホ
ールを形成する方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit board comprising a lower layer conductor and an upper layer conductor which are insulated by an insulating film made of a polyimide resin, and more particularly to a multi-layer insulating film having a plurality of laminated layers. The present invention relates to a method of forming a through hole connecting a conductor and an upper layer conductor.

【0002】混成集積回路基板等において導体間に介在
させた絶縁膜にピンホールがあるとピンホールを介して
短絡する場合がある。かかる短絡を無くす手段として樹
脂の塗布と硬化を複数回繰り返すことによって複数層か
らなる絶縁膜を生成する。
If a pinhole is present in an insulating film interposed between conductors in a hybrid integrated circuit board or the like, a short circuit may occur via the pinhole. As a means for eliminating such a short circuit, the application and curing of the resin are repeated a plurality of times to form an insulating film having a plurality of layers.

【0003】しかし、かかる絶縁膜にスルーホールを形
成すると上下層の導体を接続する導体に亀裂が入り断線
する場合がある。そこで多層絶縁膜に絶縁膜の接合点に
おいて導体に亀裂が入らないスルーホールを形成する方
法の開発が要望されている。
However, when a through hole is formed in such an insulating film, a conductor connecting upper and lower conductors may be cracked and broken. Therefore, there is a demand for development of a method for forming a through hole in the multilayer insulating film at which the conductor does not crack at the junction of the insulating films.

【0004】[0004]

【従来の技術】図3は従来のスルーホール形成方法を示
す側断面図である。図において従来のスルーホール形成
方法は下層導体1を有する基板2上にポリイミド樹脂か
らなる絶縁膜が生成され、絶縁膜はピンホール等による
短絡を防止するため層状に被着された例えば2重の絶縁
膜3aおよび3bで構成されている。
2. Description of the Related Art FIG. 3 is a side sectional view showing a conventional through hole forming method. In the figure, according to the conventional method of forming a through hole, an insulating film made of a polyimide resin is formed on a substrate 2 having a lower conductor 1, and the insulating film is, for example, a double layer applied in a layered form to prevent a short circuit due to a pinhole or the like. It is composed of insulating films 3a and 3b.

【0005】2重の絶縁膜は基板2に塗布された感光性
ポリイミド樹脂を露光して現像し絶縁膜3aをパターニン
グした後焼成する。更に、その上に塗布された感光性ポ
リイミド樹脂を露光して現像し絶縁膜3bをパターニング
した後焼成し生成される。
The double insulating film is formed by exposing the photosensitive polyimide resin coated on the substrate 2 to light and developing it to pattern the insulating film 3a and then baking it. Further, the photosensitive polyimide resin applied thereon is exposed to light and developed to pattern the insulating film 3b and then baked to generate the insulating film 3b.

【0006】生成された絶縁膜には絶縁膜3b上に形成さ
れた上層導体4を下層導体1に接続するスルーホール5
が形成されており、スルーホール5は絶縁膜3a、3bにそ
れぞれ設けられた貫通孔5a、5bと貫通孔内部を貫通する
導体5cとで形成されている。
Through holes 5 are formed in the generated insulating film to connect the upper conductor 4 formed on the insulating film 3b to the lower conductor 1.
The through hole 5 is formed by through holes 5a and 5b provided in the insulating films 3a and 3b, respectively, and a conductor 5c penetrating the inside of the through hole.

【0007】貫通孔5a、5bの壁面に沿って導体5cを生成
する場合は各壁面の段差が小さいほど膜厚の一様な導体
を生成しやすい。そこで下層の絶縁膜3aには外径が上層
の絶縁膜3bに設けられた貫通孔5bの外径より小さい貫通
孔5aが設けられている。
When the conductor 5c is formed along the wall surfaces of the through holes 5a and 5b, the smaller the step on each wall surface, the easier it is to form a conductor having a uniform film thickness. Therefore, the lower insulating film 3a is provided with a through hole 5a having an outer diameter smaller than that of the through hole 5b provided in the upper insulating film 3b.

【0008】[0008]

【発明が解決しようとする課題】図4は従来の形成方法
における問題点を示す側断面図である。しかし、従来の
形成方法は上層の絶縁膜3bを生成する前に下層の絶縁膜
3aが焼成されて黒色ポリイミドになっており、上層の絶
縁膜3bを露光するための紫外線が下層の絶縁膜3aに吸収
されて貫通孔5bの周縁部に対する露光量が小さくなる。
FIG. 4 is a side sectional view showing a problem in the conventional forming method. However, in the conventional method, the lower insulating film is formed before the upper insulating film 3b is formed.
3a is baked into black polyimide, and the ultraviolet rays for exposing the upper insulating film 3b are absorbed by the lower insulating film 3a, so that the exposure amount to the peripheral portion of the through hole 5b becomes small.

【0009】また、量産時に上層の絶縁膜3bを現像する
際の現像液が絶縁膜の間に侵入して絶縁膜3bの下面がし
ばしば浸食され、焼成すると図4に示す如く貫通孔の周
縁部がめくれ上がり上下導体層を接続する導体に亀裂が
生じるという問題があった。
Further, the developing solution for developing the upper insulating film 3b during mass production invades between the insulating films, so that the lower surface of the insulating film 3b is often eroded, and when fired, the peripheral portion of the through hole as shown in FIG. There has been a problem that the conductor that flips up and cracks occur in the conductor that connects the upper and lower conductor layers.

【0010】本発明の目的は多層絶縁膜に絶縁膜の接合
点において導体に亀裂が入らないスルーホールを形成す
る方法を提供することにある。
It is an object of the present invention to provide a method for forming a through hole in a multilayer insulating film in which a conductor is not cracked at a junction of the insulating films.

【0011】[0011]

【課題を解決するための手段】図1は本発明になるスル
ーホール形成方法を示す側断面図である。なお全図を通
し同じ対象物は同一記号で表している。
FIG. 1 is a side sectional view showing a through hole forming method according to the present invention. Note that the same object is denoted by the same symbol throughout the drawings.

【0012】上記課題は下層導体を有する基板上に2層
以上の絶縁膜を積層し最上層の絶縁膜上に形成された上
層導体を、絶縁膜に設けられた貫通孔を介して下層導体
に接続する多層絶縁膜へのスルーホール形成において、
下層の絶縁膜6aに設けられる貫通孔7aを上層の絶縁膜6b
に設けられる貫通孔7bに比べて大きくすると共に、上層
の絶縁膜6bを下層の絶縁膜6aの貫通孔7aに嵌入させる本
発明になる多層絶縁膜へのスルーホール形成方法によっ
て達成される。
The above problem is that the upper layer conductor formed on the uppermost insulating film by laminating two or more layers of insulating film on the substrate having the lower layer conductor is converted into the lower layer conductor through the through hole provided in the insulating film. When forming a through hole in the multi-layer insulation film to be connected,
The through-hole 7a provided in the lower insulating film 6a is replaced by the upper insulating film 6b.
This is achieved by the method of forming a through hole in a multilayer insulating film according to the present invention, which is made larger than the through hole 7b provided in the above, and the upper insulating film 6b is fitted into the through hole 7a of the lower insulating film 6a.

【0013】[0013]

【作用】図1において下層の絶縁膜に設けられる貫通孔
を上層の絶縁膜に設けられる貫通孔に比べて大きくする
と共に、上層の絶縁膜を下層の絶縁膜の貫通孔に嵌入さ
せることによってスルーホールから絶縁膜の接合点を無
くすことができる。
In FIG. 1, the through hole provided in the lower insulating film is made larger than the through hole provided in the upper insulating film, and the upper insulating film is inserted into the through hole of the lower insulating film to allow the through hole. It is possible to eliminate the junction point of the insulating film from the hole.

【0014】即ち、多層絶縁膜に絶縁膜の接合点におい
て導体に亀裂が入らないスルーホールを形成する方法を
実現することができる。
That is, it is possible to realize a method of forming a through hole in the multilayer insulating film at which the conductor does not crack at the junction of the insulating films.

【0015】[0015]

【実施例】以下添付図により本発明の実施例について説
明する。なお図2は本発明になる形成方法の他の実施例
を示す側断面図である。
Embodiments of the present invention will be described below with reference to the accompanying drawings. 2 is a side sectional view showing another embodiment of the forming method according to the present invention.

【0016】図1において本発明になるスルーホール形
成方法は従来と同様に下層導体1を有する基板2上に絶
縁膜が生成され、絶縁膜はピンホール等による短絡を防
止するため層状に被着された例えば2重の絶縁膜6aおよ
び6bで構成されている。
In the method of forming a through hole according to the present invention shown in FIG. 1, an insulating film is formed on a substrate 2 having a lower layer conductor 1 as in the conventional case, and the insulating film is applied in layers to prevent a short circuit due to a pinhole or the like. For example, the double insulating films 6a and 6b are formed.

【0017】2重の絶縁膜は基板2に塗布された感光性
ポリイミド樹脂を露光して現像し絶縁膜6aをパターニン
グした後焼成する。更に、その上に塗布された感光性ポ
リイミド樹脂を露光して現像し絶縁膜6bをパターニング
した後焼成し生成される。
The double insulating film is formed by exposing the photosensitive polyimide resin coated on the substrate 2 to light and developing it to pattern the insulating film 6a and then baking it. Further, the photosensitive polyimide resin applied thereon is exposed to light and developed to pattern the insulating film 6b, and then baked to generate the insulating film 6b.

【0018】生成された絶縁膜には絶縁膜6b上に形成さ
れた上層導体4を下層導体1に接続するスルーホール7
が形成されており、スルーホール7は絶縁膜6a、6bにそ
れぞれ設けられた貫通孔7a、7bと貫通孔内部を貫通する
導体7cとで形成されている。
Through holes 7 for connecting the upper layer conductor 4 formed on the insulating film 6b to the lower layer conductor 1 are formed in the generated insulating film.
The through hole 7 is formed of through holes 7a and 7b provided in the insulating films 6a and 6b and a conductor 7c penetrating the inside of the through hole.

【0019】従来の方法とは異なり下層の絶縁膜6aには
外径が上層の絶縁膜6bに設けられた貫通孔7bより大きい
貫通孔7aが設けられ、段差を小さくするため上層の絶縁
膜6bが下層の絶縁膜6aに設けられた貫通孔7aに嵌入する
ように構成されている。
Unlike the conventional method, the lower insulating film 6a is provided with a through hole 7a having an outer diameter larger than that of the through hole 7b formed in the upper insulating film 6b, and the upper insulating film 6b is formed to reduce a step. Is configured to be fitted into the through hole 7a provided in the lower insulating film 6a.

【0020】なお、前記実施例は下層の絶縁膜6aの膜厚
と上層の絶縁膜6bの膜厚がほぼ等しくなるように形成さ
れているが、図2に示す如く下層の絶縁膜6aの膜厚を上
層の絶縁膜6bの膜厚より厚くすることで段差を更に小さ
くすることが可能になる。
In the above-described embodiment, the lower insulating film 6a and the upper insulating film 6b are formed to have almost the same thickness. However, as shown in FIG. 2, the lower insulating film 6a is formed. By making the thickness thicker than the thickness of the upper insulating film 6b, it becomes possible to further reduce the step.

【0021】このように下層の絶縁膜に設けられる貫通
孔を上層の絶縁膜に設けられる貫通孔に比べて大きくす
ることによって、上層の絶縁膜をパターニングする際に
貫通孔の内部に下層導体が露呈しており露光用の紫外線
が吸収されることはない。
By making the through-hole provided in the lower insulating film larger than the through-hole provided in the upper insulating film, the lower-layer conductor is provided inside the through-hole when the upper insulating film is patterned. It is exposed and does not absorb ultraviolet rays for exposure.

【0022】その結果、上層の絶縁膜の現像時における
絶縁膜下面の浸食や焼成時における貫通孔周縁部のめく
れ上がりが無くなり、多層絶縁膜に絶縁膜の接合点にお
いて導体に亀裂が入らないスルーホールを形成する方法
を実現することができる。
As a result, erosion of the lower surface of the insulating film at the time of developing the upper insulating film and curling up of the peripheral portion of the through hole at the time of baking are eliminated, and the conductor does not crack at the junction of the insulating film in the multilayer insulating film. A method of forming holes can be realized.

【0023】しかも、上層の絶縁膜をパターニングする
際の紫外線の吸収が無くなるため露光量を削減すること
が可能になり、絶縁膜をパターニングする装置の処理能
力が向上すると共に混成集積回路基板の製造に要する時
間を短縮することができる。
Moreover, since the absorption of ultraviolet rays when patterning the upper insulating film is eliminated, the exposure amount can be reduced, the processing ability of the device for patterning the insulating film is improved, and the hybrid integrated circuit substrate is manufactured. The time required for can be shortened.

【0024】[0024]

【発明の効果】上述の如く本発明によれば多層絶縁膜に
絶縁膜の接合点において導体に亀裂が入らないスルーホ
ールを形成する方法を提供することができる。
As described above, according to the present invention, it is possible to provide a method for forming a through hole in a multilayer insulating film at which a conductor does not crack at a junction of the insulating films.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明になるスルーホール形成方法を示す側
断面図である。
FIG. 1 is a side sectional view showing a through hole forming method according to the present invention.

【図2】 本発明になる形成方法の他の実施例を示す側
断面図である。
FIG. 2 is a side sectional view showing another embodiment of the forming method according to the present invention.

【図3】 従来のスルーホール形成方法を示す側断面図
である。
FIG. 3 is a side sectional view showing a conventional through hole forming method.

【図4】 従来の形成方法における問題点を示す側断面
図である。
FIG. 4 is a side sectional view showing a problem in a conventional forming method.

【符号の説明】[Explanation of symbols]

1 下層導体 2 基板 4 上層導体 6a、6b 絶縁膜 7 スルーホール 7a、7b 貫通孔 7c 導体 1 Lower layer conductor 2 Substrate 4 Upper layer conductor 6a, 6b Insulating film 7 Through holes 7a, 7b Through hole 7c Conductor

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 下層導体を有する基板上に2層以上の絶
縁膜を積層し最上層の該絶縁膜上に形成された上層導体
を、該絶縁膜に設けられた貫通孔を介して該下層導体に
接続する多層絶縁膜へのスルーホール形成において、 下層の絶縁膜(6a)に設けられる貫通孔(7a)を上層の絶縁
膜(6b)に設けられる貫通孔(7b)に比べて大きくすると共
に、上層の絶縁膜(6b)を下層の絶縁膜(6a)の貫通孔(7a)
に嵌入させることを特徴とする多層絶縁膜へのスルーホ
ール形成方法。
1. An upper layer conductor formed by stacking two or more layers of insulating films on a substrate having a lower layer conductor, and forming an upper layer conductor on the uppermost insulating film through a through hole provided in the insulating film. When forming a through hole in a multi-layer insulating film that is connected to a conductor, make the through hole (7a) in the lower insulating film (6a) larger than the through hole (7b) in the upper insulating film (6b). Together with the upper insulating film (6b) through hole (7a) of the lower insulating film (6a)
A method for forming a through hole in a multilayer insulating film, which is characterized in that:
【請求項2】 請求項1に記載された多層絶縁膜へのス
ルーホール形成方法において下層の絶縁膜(6a)の膜厚
を、上層の絶縁膜(6b)の膜厚に比べて厚くすることを特
徴とした多層絶縁膜へのスルーホール形成方法。
2. In the method for forming a through hole in a multilayer insulating film according to claim 1, the thickness of the lower insulating film (6a) is made thicker than the thickness of the upper insulating film (6b). A method of forming a through hole in a multi-layer insulating film, characterized by:
JP14777092A 1992-06-09 1992-06-09 Formation through hole in multilayer insulating film Pending JPH05343853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14777092A JPH05343853A (en) 1992-06-09 1992-06-09 Formation through hole in multilayer insulating film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14777092A JPH05343853A (en) 1992-06-09 1992-06-09 Formation through hole in multilayer insulating film

Publications (1)

Publication Number Publication Date
JPH05343853A true JPH05343853A (en) 1993-12-24

Family

ID=15437791

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14777092A Pending JPH05343853A (en) 1992-06-09 1992-06-09 Formation through hole in multilayer insulating film

Country Status (1)

Country Link
JP (1) JPH05343853A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS515568A (en) * 1974-07-05 1976-01-17 Oki Electric Ind Co Ltd Tasohaisenkairono seizohoho
JPS62171194A (en) * 1986-01-24 1987-07-28 キヤノン株式会社 Matrix wiring board
JPS6318697A (en) * 1986-07-11 1988-01-26 日本電気株式会社 Multilayer interconnection board
JPH02148888A (en) * 1988-11-30 1990-06-07 Nec Corp Multilayer interconnection substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS515568A (en) * 1974-07-05 1976-01-17 Oki Electric Ind Co Ltd Tasohaisenkairono seizohoho
JPS62171194A (en) * 1986-01-24 1987-07-28 キヤノン株式会社 Matrix wiring board
JPS6318697A (en) * 1986-07-11 1988-01-26 日本電気株式会社 Multilayer interconnection board
JPH02148888A (en) * 1988-11-30 1990-06-07 Nec Corp Multilayer interconnection substrate

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