JPH05343523A - Method of macrocell wiring in semicustom integrated circuit - Google Patents

Abstract

PURPOSE:To prevent that an electrical signal held in a capacitor in a dynamic circuit is destroyed by inhibiting that an automatic wiring is passed on a pattern for the dynamic circuit formed in a macrocell. CONSTITUTION:First, many circuit patterns are registered in a library as macrocells 6a, 6b, 7. Then, an automatic wiring region 22 is registered in the library in such a way that an automatic wiring 1 is not passed on a pattern for a dynamic circuit inside the macrocell 7 which is provided with a dynamic circuit 5 in which an electrical signal is held in a capacitor when an integrated circuit is designed, patterns for various kinds of circuits are combined variously on the basis of data registered in the library, and a pattern for the semiconductor circuit is formed by using the automatic wiring inhibition region 22. In the semiconductor integrated circuit which is obtained by this method, the electrical signal which is held in the capacitor formed in the dynamic circuit 5 is not destroyed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a macro cell wiring method in a semi-custom integrated circuit,
In particular, it is used for automatic wiring of a macro cell having a dynamic circuit.

[0002]

2. Description of the Related Art A conventional automatic placement and wiring method for a macro cell including a dynamic circuit will be described with reference to FIGS. FIG. 2 is a pattern plan view showing a state in which macro cells including a dynamic circuit that holds an electric signal in a capacitor are automatically arranged and automatically wired.

Reference numerals 106a, 106b and 107 in FIG. 2 denote macro cells. The macro cell 106a has an input / output terminal 10
3a to 103c are arranged, input / output terminals 103d to 103f are arranged in the macro cell 107,
Input / output terminals 103g to 103j are arranged at 6b. The input / output terminals 103a to 103j formed in each macro cell 106a, 106b, 107c are selectively connected by the automatic wiring 101 to form a desired integrated circuit. The horizontal wiring portion and the vertical wiring portion of the automatic wiring 101 are connected by the contacts 102a to 102u.

Further, in the macro cell 106a, through wiring regions 104a, 10a in which automatic wiring can pass over the pattern are provided.
4b is formed, through wiring regions 104c to 104f are formed in the macro cell 107, and through wiring regions 104g and 104h are formed in the macro cell 106b.

Further, in the macro cell 107, a dynamic circuit 1 for holding an electric signal in a capacitor described later is provided.
Have 05. Since the through wiring regions 104c and 104d are formed on the pattern of the dynamic circuit 105 designed in the macro cell 107 as described above, the automatic wiring 101 passes through.

FIG. 3 is an enlarged pattern plan view of a part of the dynamic circuit 105 shown in FIG. 2, and FIG.
It is a sectional view taken along the line -Y '. In these figures, the automatic wiring 101 is arranged on the pattern of the dynamic circuit formed in the macro cell.

[0007] semiconductor substrate 114 in FIG. 4, P ⁺ A diffusion region 127 and a P well diffusion region 128 are formed.
In the P well diffusion region 128, N ⁺ A diffusion region 129 is formed. A gate electrode 130a is formed between the power supply aluminum 126a and the wiring aluminum 131, and a gate electrode 130 is formed between the power supply aluminum 126b and the wiring aluminum 131.
b is formed.

The control signals φ1, φ1 (φ1 — represents an inverted signal of φ1) and the input signal IN are supplied to predetermined gate electrodes in FIG. 3, and the control signals φ2, φ2 — are predetermined gates. The output signal OUT, which is supplied to the electrodes, is output from the output terminal of a clocked inverter described later.
As shown in FIG. 4, the capacitor 115 formed between the point A of the wiring aluminum 131 and the semiconductor substrate 114 holds an electric signal. When the automatic wiring 101 is formed on the wiring aluminum as shown in FIG. 4, a capacitor 119 is formed between the point A of the wiring aluminum 131 and the automatic wiring 101.

FIG. 5 shows a specific example of the configuration of the dynamic circuit shown in FIG. 3, which is composed of clocked inverters 123a and 123b which are cascaded by a signal line A.

FIG. 6 shows a concrete configuration example of the clocked inverters 123a and 123b shown in FIG. As shown in FIG. 6, the clocked inverter 123a
Is a P-channel MOSFET 124a, N-channel MOS
FET 125b, P-channel MOSFET 12 for control
4b, an N-channel MOSFET 125a for control. P-channel MOSFET 124 for control
The control signal φ1 is applied to the gate electrode of b and the control signal φ1 is applied to the gate electrode of the control N-channel MOSFET 125a.
Is being supplied.

The clocked inverter 123b includes a P-channel MOSFET 124c and an N-channel MOSFET 1
25d, a control P-channel MOSFET 124d, and a control N-channel MOSFET 125c. The gate electrode of the control P-channel MOSFET 124d has a control signal φ2 and a control N-channel MOS.
The control signal φ2 is supplied to the gate electrode of the FET 125c.

The control signals φ1, φ1 and φ shown in FIG.
2, φ2 — input signal IN, output signal OUT are control signals φ1, φ1 — φ2, φ2 — input signal I shown in FIG.
N, corresponding to the output signal OUT.

FIG. 7A shows a clocked inverter 123.
7A is a control signal φ1 supplied to a, and FIG. 7B is a control signal φ2 supplied to the clocked inverter 123b.
7C shows the input signal IN shown in FIG. 5, and FIG. 7D shows the level of the signal supplied to the automatic wiring.

When the automatic wiring is formed on the capacitor of the dynamic circuit and the signals shown in FIGS. 7A to 7C are supplied to the dynamic circuit, the connection line A of FIG. ) Affected by the signal level of the automatic wiring. That is, the potential of the connection line A shown in FIGS.
As shown in (e), it temporarily falls from high (dotted line 121) to low level (120).

Further, the change in the potential of the connecting line A (120)
In response to this, the output signal OUT is, as shown in FIG.
A low level (dashed-dotted line 121) temporarily rises to a high level.

[0016]

As described above, when the automatic wiring passes over the pattern of the dynamic circuit of the macrocell, there is a problem that the electric signal held in the capacitor in the dynamic circuit is destroyed.

The present invention has been made in view of the above circumstances, and holds a capacitor in a capacitor by prohibiting passage of automatic wiring on the pattern of the dynamic circuit of a macro cell including a dynamic circuit for holding an electric signal in the capacitor. It is an object of the present invention to provide a wiring method of a macro cell in a semi-custom integrated circuit that prevents the destruction of the electric signal being used.

[0018]

A macrocell wiring method in a semi-custom integrated circuit according to the present invention comprises a first step of registering various circuit patterns as a macrocell in a library before designing the integrated circuit, and an integrated circuit. Prior to designing, a second step of designating a macrocell pattern having a dynamic circuit for holding an electric signal in a capacitor as an automatic wiring prohibited area and registering it in a library;
It has a third step of forming a desired integrated circuit by automatically arranging and wiring based on the data registered in the library in the second step, and automatically avoiding the pattern of the dynamic circuit of the macrocell. It is characterized by wiring.

[0019]

In the first and second steps, automatic placement and wiring are performed based on the data registered in the library, and a desired integrated circuit is formed by the third step. A semi-custom integrated circuit with automatic wiring avoiding is obtained. With this semi-custom integrated circuit, it is possible to prevent the electric signal held in the capacitor of the dynamic circuit from being destroyed.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A macrocell wiring method (hereinafter referred to as macrocell wiring method) in a semi-custom integrated circuit according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a pattern plan view showing a state of automatic placement and automatic wiring of macro cells including a dynamic circuit for holding an electric signal in a capacitor according to an embodiment of the present invention. still,
A dynamic circuit (eg, DRAM) is a circuit having a function of temporarily storing a signal.

Reference numerals 6a, 6b and 7 in FIG. 1 denote macro cells. Input / output terminals 3a to 3c are arranged in the macro cell 6a, input / output terminals 3d to 3f are arranged in the macro cell 7, and input / output terminals 3g to 3j are arranged in the macro cell 6b. The input / output terminals 3a to 3j formed in each of the macro cells 6a, 7 and 6b are selectively connected by the automatic wiring 1 to form a desired integrated circuit. The horizontal wiring portion and the vertical wiring portion of the automatic wiring 1 are connected by the contacts 2a to 2q.

Further, the macro cell 6a is formed with through wiring regions 4a and 4b through which automatic wiring can pass on the pattern, and the macro cell 7 is formed with a through wiring region 4c.
Through wiring regions 4d and 4e are formed in the macro cell 6b. The automatic wiring 1 is arranged in the through wiring regions 4a, 4c, 4e.

Further, the macro cell 7 has a dynamic circuit 5 for holding an electric signal in a capacitor. An automatic wiring prohibited area 22 is formed on the pattern of the dynamic circuit 5 designed in the macro cell 7. next,
The design of a semi-custom integrated circuit by the macro cell wiring method will be described.

First, before designing the semi-custom integrated circuit,
A large number of combinational circuits or sequential circuits are prepared as macrocells. The combination circuit is a logic circuit that immediately determines the output based on the current input signal, and is, for example, a combination of an inverter, an OR gate, and an AND gate. Further, the sequential circuit is a logic circuit having a function of temporarily storing an input signal and is, for example, a latch circuit, a memory, or the like.

That is, the patterns of various circuits are made into a library as a basic pattern and stored in a memory of a computer (not shown). In addition, the pattern of the dynamic circuit of the macro cell is designated as an automatic wiring prohibited area, which is made into a library and stored in the memory of the computer.

In designing, the patterns of various circuits stored in this library are variously combined by the CAD method, and the semi-custom integrated circuit is designed using the wiring prohibited area.

According to the above embodiment, the macro cell 7 having the automatic wiring prohibited area 22 formed on the dynamic circuit as shown in FIG. 1 is obtained. Since the automatic wiring prohibited area 22 is formed on the pattern of the dynamic circuit, the obtained macro cell is not automatically wired on the capacitor formed in the wiring aluminum of the dynamic circuit. Therefore, a capacitor is not formed between the wiring aluminum and the automatic wiring and is not affected by the level of the signal supplied to the automatic wiring, so that the electric signal held by the capacitor formed in the wiring aluminum is not destroyed.

[0028]

As described above, according to the present invention,
Since the passage of the automatic wiring on the pattern of the dynamic circuit formed in the macro cell is prohibited, it is possible to provide the wiring method of the macro cell in the semi-custom integrated circuit which prevents the electric signal held in the capacitor from being destroyed.

[Brief description of drawings]

FIG. 1 is a pattern plan view of automatic placement and automatic wiring of macro cells including a dynamic circuit according to an embodiment of the present invention.

FIG. 2 is a pattern plan view showing automatic placement and automatic wiring of macro cells including a conventional dynamic circuit.

FIG. 3 is a plan view of a pattern of a dynamic circuit.

FIG. 4 is a cross-sectional view of a dynamic circuit.

FIG. 5 is a circuit diagram of a dynamic circuit.

FIG. 6 is a diagram showing details of a clocked inverter forming a dynamic circuit.

FIG. 7 is a timing chart showing the operation of the dynamic circuit.

[Explanation of symbols]

1 ... Automatic wiring, 2a-2q ... Automatic wiring contact, 3a
~ 3j ... I / O terminals, 4a-4e ... Through wiring area, 5
... Dynamic circuit, 6a, 6b, 7 ... Macro cell, 2
2 ... Automatic wiring prohibited area.

Claims (1)

[Claims] 1. A first step of registering various circuit patterns in a library as a macro cell before designing an integrated circuit, and a macro cell pattern having a dynamic circuit for holding an electric signal in a capacitor before designing the integrated circuit. Is designated as an automatic wiring prohibited area and registered in the library, and a desired integrated circuit is obtained by performing automatic placement and automatic wiring based on the data registered in the library in the first and second steps. And a third step of forming a macro cell, wherein the wiring is performed automatically while avoiding the pattern of the dynamic circuit of the macro cell.