JPH05343487A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH05343487A
JPH05343487A JP4170189A JP17018992A JPH05343487A JP H05343487 A JPH05343487 A JP H05343487A JP 4170189 A JP4170189 A JP 4170189A JP 17018992 A JP17018992 A JP 17018992A JP H05343487 A JPH05343487 A JP H05343487A
Authority
JP
Japan
Prior art keywords
pad terminal
pad
probe
terminal
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4170189A
Other languages
Japanese (ja)
Inventor
Noboru Kawamata
昇 川又
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4170189A priority Critical patent/JPH05343487A/en
Publication of JPH05343487A publication Critical patent/JPH05343487A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To inspect the damage to a cover film due to a probe needle for inspection use in the inspection of the circuit device in a wafer state. CONSTITUTION:A second pad terminal 12 which is smaller than a cover opening part 3 on a first pad terminal 2 is formed on a semiconductor integrated circuit(IC) 1. A metal interconnection 11 is arranged so as to surround its circumference in such a way that an inner-side length l becomes smaller than a single- side length L at the cover opening part 3. It is detected whether a probe needle 7 for inspection use comes into contact with the metal interconnection 11, and the dislocation of the probe needle 7 is detected.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体集積回路装置
（以下、ＩＣという）に関し、特に内部に設置されたパ
ッド端子の構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device (hereinafter referred to as an IC), and more particularly to the structure of pad terminals installed inside.

【０００２】[0002]

【従来の技術】通常、ＩＣは図５，図６に示すように、
ＩＣ１内の内部回路４と外部端子５とを接続するために
パッド端子２を設け、パッド端子２と外部端子５とをワ
イヤー６にて結線することにより、外部回路とＩＣ回路
とを接続させている。2. Description of the Related Art Normally, an IC is constructed as shown in FIGS.
By providing a pad terminal 2 for connecting the internal circuit 4 in the IC 1 and the external terminal 5 and connecting the pad terminal 2 and the external terminal 5 with a wire 6, the external circuit and the IC circuit are connected. There is.

【０００３】ＩＣ１の表面は、内部回路４を保護するた
めにカバーで覆われているが、パッド端子２には、ワイ
ヤー６と接続するためにカバー開口部３が設けられてい
る。The surface of the IC 1 is covered with a cover for protecting the internal circuit 4, but the pad terminal 2 is provided with a cover opening 3 for connecting with the wire 6.

【０００４】また、パッド端子２は、ワイヤー６により
結線する前、すなわちウェハ状態において内部回路４を
検査する際にも使用される。その方法は、外部結線され
た針をパッド端子２に接触させることにより、外部との
接続を行っている。The pad terminals 2 are also used before the internal circuits 4 are inspected before they are connected by the wires 6, that is, in the wafer state. In this method, the externally connected needle is brought into contact with the pad terminal 2 to connect to the outside.

【０００５】従来のＩＣは図６に示すように、設置され
たパッド端子２は全て同一の大きさであり、その大きさ
は、ワイヤー６の先端径が約１００μｍに対し、１２０
μｍ前後である。As shown in FIG. 6, in the conventional IC, the pad terminals 2 installed are all the same size, and the size is 120 when the tip diameter of the wire 6 is about 100 μm.
It is around μm.

【０００６】ところが、針の先端径は５０μｍ前後であ
るため、パッド端子２との接触巾は２０〜３０μｍ程度
である。また、目合わせ用に前記パッド端子の大きさよ
りも面積が小さい第２のパッド端子を２ケ以上設け、前
記第２のパッド端子間を導体で接続し、テストの際に前
記第２のパッド端子間の導通を確認するという方法もあ
る（例えば、特開平２−１５１０４８号）。However, since the tip diameter of the needle is around 50 μm, the contact width with the pad terminal 2 is about 20 to 30 μm. Further, two or more second pad terminals having an area smaller than the size of the pad terminals are provided for alignment, and the second pad terminals are connected by a conductor, and the second pad terminals are used during a test. There is also a method of confirming continuity between the two (for example, JP-A-2-151048).

【０００７】さらに、プローブ針とパッド端子との接続
を確認するために、一対の電極間の電気抵抗を測定する
という検査方法もある（例えば特開平２−２００３７
号）。Further, there is also an inspection method of measuring the electric resistance between a pair of electrodes in order to confirm the connection between the probe needle and the pad terminal (for example, Japanese Patent Laid-Open No. 20037/1990).
issue).

【０００８】[0008]

【発明が解決しようとする課題】この従来のＩＣでは、
ウェハ状態において内部回路を検査する際、すなわち検
査用針をパッド端子に接触させる時、針の接着面積に対
しパッド端子の面積が十分に大きいため、正確な目合わ
せができず、その結果、検査が進むにつれ、針の接着位
置が次第にずれていき、ひどい時にはパッド端子上のカ
バー膜を傷つけてしまうが、それを検出するには、目視
検査しかなく、目視検査では、多くの工数がかかり、ま
た、検出率も低いという問題点があった。In this conventional IC,
When inspecting the internal circuit in the wafer state, that is, when the inspection needle is brought into contact with the pad terminal, the area of the pad terminal is sufficiently larger than the bonding area of the needle, so accurate alignment cannot be performed. The adhesive position of the needle gradually shifts as it progresses, and when it is severe, it damages the cover film on the pad terminal, but to detect it, there is only visual inspection, and it takes a lot of man-hours in visual inspection. There is also a problem that the detection rate is low.

【０００９】また、特開平２−１５１０４８号の場合、
プローブ針の圧力が大き過ぎて、パッド剤を伴ってズレ
る場合があり、この時プローブ針先が第２のパットより
ズレていても導通する可能性は高い。さらに特開平２−
２００３７号の場合は、一対の電極にプローブ針が接触
さえしていれば良く、プローブ針先によるパッシベーシ
ョン膜破壊に対して何の効果も期待できない。Further, in the case of JP-A-2-151048,
There is a case where the pressure of the probe needle is too large and the probe needle is displaced together with the pad material. At this time, even if the probe needle tip is displaced from the second pad, there is a high possibility of conduction. Further, JP-A-2-
In the case of No. 20037, it suffices that the probe needle is in contact with the pair of electrodes, and no effect can be expected against the destruction of the passivation film by the probe needle tip.

【００１０】本発明の目的は、検査用探針によるカバー
膜損傷を検出可能な半導体集積回路装置を提供すること
にある。An object of the present invention is to provide a semiconductor integrated circuit device capable of detecting a cover film damage caused by an inspection probe.

【００１１】[0011]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係る半導体集積回路装置は、第１のパッド
端子を有する半導体集積回路装置であって、第１のパッ
ド端子は、少なくとも一部がカバー膜に覆われ、外部端
子と内部回路を接続するためのものであり、前記第１の
パッド端子のカバー膜に覆われていない部分は、第１の
パッド端子よりも小さい第２のパッド端子を有し、かつ
前記第２のパッド端子の外周縁に沿う金属配線を有する
ものである。To achieve the above object, a semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device having a first pad terminal, wherein the first pad terminal is at least one. A portion of the first pad terminal which is covered with the cover film to connect the external terminal and the internal circuit, and a portion of the first pad terminal which is not covered with the cover film is smaller than the first pad terminal. It has a pad terminal and a metal wiring along the outer peripheral edge of the second pad terminal.

【００１２】[0012]

【作用】従来は一対のパッド端子間の導通状態を確認し
ているが、本発明は、パッド端子と周囲金属配線との非
導通状態を確認することにより、プローブ針ズレがない
ことを確認する。In the prior art, the conduction state between the pair of pad terminals has been confirmed, but the present invention confirms that there is no probe needle displacement by confirming the non-conduction state between the pad terminals and the surrounding metal wiring. .

【００１３】[0013]

【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.

【００１４】（実施例１）図１は、本発明の実施例１を
示す平面図である。(Embodiment 1) FIG. 1 is a plan view showing Embodiment 1 of the present invention.

【００１５】図において、ＩＣ１内に外部接続用の第１
のパッド端子２が配置され、その第１のパッド端子２上
には、ワイヤーとの接続用のカバー開口部３が設けられ
ている。その隣には、第２のパッド端子１２が配置さ
れ、第２のパッド端子１２の周囲は、金属配線１１によ
り囲まれている。In the figure, a first IC for external connection is provided in IC1.
Pad terminals 2 are arranged, and a cover opening 3 for connection with a wire is provided on the first pad terminal 2. Next to it, the second pad terminal 12 is arranged, and the periphery of the second pad terminal 12 is surrounded by the metal wiring 11.

【００１６】金属配線１１は、第１のパッド端子２と接
続されており、その内辺ｌは、カバー開口部３の辺Ｌよ
りも小さい。The metal wiring 11 is connected to the first pad terminal 2, and its inner side 1 is smaller than the side L of the cover opening 3.

【００１７】第２のパッド端子１２上のカバー開口部３
のサイズは、パッド端子２上のカバー開口部３と同一サ
イズで、第２のパッド端子１２の全てと金属配線１１の
一部がカバー開口部になる。The cover opening 3 on the second pad terminal 12
Is the same size as the cover opening 3 on the pad terminal 2, and the entire second pad terminal 12 and part of the metal wiring 11 are the cover opening.

【００１８】次にウェハー上での検査をする場合を説明
する。図３は、探針がパッド端子に正常に接着された状
態を示す図である。探針７は第１及び第２のパッド端子
２，１２の中心に接触されており、第２のパッド端子１
２と金属配線１１は接続されていないので、第２のパッ
ド端子１２上の探針７には、第２のパッド端子１２の信
号のみが伝達される。この時、第１のパッド端子２上の
探針は、カバー開口部内にあるため、カバーは損傷しな
い。Next, a case of inspecting on a wafer will be described. FIG. 3 is a diagram showing a state in which the probe is normally bonded to the pad terminal. The probe 7 is in contact with the centers of the first and second pad terminals 2 and 12, and the second pad terminal 1
Since 2 and the metal wiring 11 are not connected, only the signal of the second pad terminal 12 is transmitted to the probe 7 on the second pad terminal 12. At this time, since the probe on the first pad terminal 2 is in the cover opening, the cover is not damaged.

【００１９】次に図４に探針位置がズレた場合の説明図
を示す。第１のパッド端子２上の探針７は、カバー開口
部３をはみ出している。すなわち、カバー膜を傷つけて
いる状態である。Next, FIG. 4 shows an explanatory view when the probe position is displaced. The probe 7 on the first pad terminal 2 protrudes from the cover opening 3. That is, the cover film is damaged.

【００２０】この時、第２のパッド端子１２上の探針７
は、第２のパッド端子１２と金属配線１１の双方に接着
している。金属配線１１は、第１のパッド端子２と接続
されているので、第２のパッド端子１２上の探針７に
は、第１のパッド端子２の信号と第２のパッド端子１２
の信号が混信した信号が伝達される。At this time, the probe 7 on the second pad terminal 12
Is adhered to both the second pad terminal 12 and the metal wiring 11. Since the metal wiring 11 is connected to the first pad terminal 2, the probe 7 on the second pad terminal 12 is connected to the signal of the first pad terminal 2 and the second pad terminal 12.
The signal that the signal of is mixed is transmitted.

【００２１】（実施例２）図２は、本発明の実施例２を
示す平面図である。第２のパッド端子１２及び、その周
囲を取り囲む金属配線１１が円形状になっている。ま
た、金属配線１１には、インバータ１０の出力が接続さ
れている。この場合も実施例１と同様に、第２のパッド
端子１２上の探針７には、第１のパッド端子２上のカバ
ー膜が傷ついたか否かで異なる信号が伝達される。(Second Embodiment) FIG. 2 is a plan view showing a second embodiment of the present invention. The second pad terminal 12 and the metal wiring 11 surrounding the second pad terminal 12 are circular. The output of the inverter 10 is connected to the metal wiring 11. Also in this case, as in the first embodiment, a different signal is transmitted to the probe 7 on the second pad terminal 12 depending on whether or not the cover film on the first pad terminal 2 is damaged.

【００２２】[0022]

【発明の効果】以上説明したように本発明は、通常のパ
ッド端子よりも小さい第２のパッド端子を設け、その周
囲を金属配線で囲むことにより、プローブ針のいかなる
ズレがあっても、第２のパッド端子上の探針に伝達され
る信号を検出することにより、探針の位置ズレによるカ
バー膜の損傷の有無が確認できるので、検査が少ない工
数でできるという効果を有する。As described above, according to the present invention, by providing the second pad terminal smaller than the normal pad terminal and surrounding the second pad terminal by the metal wiring, even if any deviation of the probe needle occurs, By detecting the signal transmitted to the probe on the pad terminal of No. 2, the presence or absence of damage to the cover film due to the displacement of the probe can be confirmed.

【００２３】また、金属配線の内辺ｌをカバー開口部の
辺Ｌより小さくすることで、カバー膜を傷つけるよりも
少ない探針ズレから検出可能であり、カバー膜損傷の検
出精度が高くなるという効果も有する。Further, by making the inner side l of the metal wiring smaller than the side L of the cover opening, it is possible to detect with less probe deviation than to damage the cover film, and the accuracy of detecting cover film damage is improved. It also has an effect.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の実施例１を示す平面図である。FIG. 1 is a plan view showing a first embodiment of the present invention.

【図２】本発明の実施例２を示す平面図である。FIG. 2 is a plan view showing a second embodiment of the present invention.

【図３】図１のＩＣに正常に探針が接着した状態を示す
図である。FIG. 3 is a diagram showing a state in which a probe is normally bonded to the IC of FIG.

【図４】図１のＩＣに探針がズレて接着した状態を示す
図である。FIG. 4 is a diagram showing a state in which a probe is displaced and adhered to the IC of FIG.

【図５】従来例を示す平面図である。FIG. 5 is a plan view showing a conventional example.

【図６】従来例のＩＣ平面図である。FIG. 6 is a plan view of an IC of a conventional example.

【符号の説明】[Explanation of symbols]

１ ＩＣ ２ 第１パッド端子 ３ カバー開口部 ４ 内部回路 ５ 外部端子 ６ ワイヤー ７ 探針 １０ インバータ １１ 金属配線 １２ 第２パッド端子 1 IC 2 1st pad terminal 3 cover opening 4 internal circuit 5 external terminal 6 wire 7 probe 10 inverter 11 metal wiring 12 second pad terminal

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 第１のパッド端子を有する半導体集積回
路装置であって、 第１のパッド端子は、少なくとも一部がカバー膜に覆わ
れ、外部端子と内部回路を接続するためのものであり、 前記第１のパッド端子のカバー膜に覆われていない部分
は、第１のパッド端子よりも小さい第２のパッド端子を
有し、かつ前記第２のパッド端子の外周縁に沿う金属配
線を有することを特徴とする半導体集積回路装置。1. A semiconductor integrated circuit device having a first pad terminal, wherein the first pad terminal is at least partially covered with a cover film and is for connecting an external terminal and an internal circuit. The portion of the first pad terminal not covered by the cover film has a second pad terminal smaller than the first pad terminal and has metal wiring along the outer peripheral edge of the second pad terminal. A semiconductor integrated circuit device having.
JP4170189A 1992-06-04 1992-06-04 Semiconductor integrated circuit device Pending JPH05343487A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4170189A JPH05343487A (en) 1992-06-04 1992-06-04 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4170189A JPH05343487A (en) 1992-06-04 1992-06-04 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH05343487A true JPH05343487A (en) 1993-12-24

Family

ID=15900333

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4170189A Pending JPH05343487A (en) 1992-06-04 1992-06-04 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH05343487A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923048A (en) * 1996-05-30 1999-07-13 Nec Corporation Semiconductor integrated circuit device with test element
US6373143B1 (en) * 1998-09-24 2002-04-16 International Business Machines Corporation Integrated circuit having wirebond pads suitable for probing
US7170189B2 (en) 2004-11-16 2007-01-30 Matsushita Electric Industrial Co., Ltd. Semiconductor wafer and testing method therefor
JP2007158346A (en) * 2005-12-02 2007-06-21 Samsung Electronics Co Ltd Probe sensing pad and method of detecting contact position of probe needle
JP2007335550A (en) * 2006-06-14 2007-12-27 Seiko Instruments Inc Semiconductor device
US11714123B2 (en) 2020-09-02 2023-08-01 United Semiconductor Japan Co., Ltd. Probe position monitoring structure and method of monitoring position of probe

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923048A (en) * 1996-05-30 1999-07-13 Nec Corporation Semiconductor integrated circuit device with test element
US6373143B1 (en) * 1998-09-24 2002-04-16 International Business Machines Corporation Integrated circuit having wirebond pads suitable for probing
US7170189B2 (en) 2004-11-16 2007-01-30 Matsushita Electric Industrial Co., Ltd. Semiconductor wafer and testing method therefor
JP2007158346A (en) * 2005-12-02 2007-06-21 Samsung Electronics Co Ltd Probe sensing pad and method of detecting contact position of probe needle
JP2007335550A (en) * 2006-06-14 2007-12-27 Seiko Instruments Inc Semiconductor device
US11714123B2 (en) 2020-09-02 2023-08-01 United Semiconductor Japan Co., Ltd. Probe position monitoring structure and method of monitoring position of probe
US11994556B2 (en) 2020-09-02 2024-05-28 United Semiconductor Japan Co., Ltd. Probe position monitoring structure and method of monitoring position of probe

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