JPH05343471A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device wherein it can be constituted without a complicated process, it eliminates a fracture phenomenon, in a bump region, due to a thermal stress or the like and it displays an excellent heat- dissipating property in the semiconductor device wherein a semiconductor element chip is mounted facedown on a circuit board having a different coefficient of thermal expansion. CONSTITUTION:The main point is that a bump 7 is formed as a double structure. That is to say, a semiconductor device is provided with the following: a circuit board 4 which is provided with a required connecting pad 4a on its main face; and a semiconductor element 1 which is mounted facedown on the connecting pad 4a on the circuit board via the bump 7. The bump 7 is composed of the following: a first metal 6a which is connected electrically to an electrode pad 1a on the semiconductor chip 1 and to the connecting pad 4a on the circuit board 4; and a second metal 6b with which the circumferential face of the first metal 6a is covered electrically. In addition, Young's modulus or the coefficient of thermal conduction of the first metal 6a is selected and set so as to be larger than Young's modulus or the coefficient of thermal conduction of the second metal 6b.

Description

Detailed Description of the Invention

[Object of the Invention]

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor element chip is mounted facedown on a required circuit board surface via bumps.

[0003]

2. Description of the Related Art As electronic equipment becomes smaller, thinner, and more sophisticated, means for mounting semiconductor element chips on a circuit board surface at high density is required. As one of the means, a method of mounting (mounting) the semiconductor element chip in a flip-chip state face down on the surface of the circuit board is effective. In this method, generally, a bump solder bump is first formed on the electrode pad of the semiconductor element chip by a method such as electroplating. For example, as shown in cross-sections in FIGS. 6 and 7, the barrier metal layer 2a and the solder 2b are deposited on the surface of the electrode pad 1a of the semiconductor element chip 1 by electroplating, dipping, vapor deposition, etc. The bumps of the straight wall bumps 2'are formed. In this case, in order to enable connection at low temperature, the mushroom bumps 2,
Alternatively, it has been attempted to coat / laminate a metal (including alloy) having a low melting point on the surface of the straight wall bump 2 '. 6 and 7, 3 indicates a passivation film.

On the other hand, the connection pads provided on the main surface of the circuit board are made of a material having good solder wettability, for example, silver palladium, silver platinum, copper, nickel, etc., and are plated with solder. In some cases. After that, the electrode bumps 1a of the semiconductor element chip 1 and the connection pads 4a of the circuit board 4 are aligned and mounted, and reflow connection is performed. FIG. 8 is a cross-sectional view showing the structure of the connecting portion between the semiconductor element chip 1 mounted on the circuit board 4 by the above method. In general, the stress caused by the difference in the coefficient of thermal expansion between the semiconductor element chip 1 and the circuit board 4 is
In order to avoid concentrating on the bumps 2 (2 ') involved in the connection (bonding) of both, the semiconductor element chip 1 and the circuit board 4
And the resin layer 5 is filled and arranged between them. The arrangement of the filling / resin layer 5 can reduce defects or failures caused by the thermal expansion to some extent, but it cannot be said to be sufficient.
In particular, when the thermal expansion coefficients of the semiconductor element chip 1 and the circuit board 4 are significantly different, the interface formed by the circuit board 4, the bump 2 (2 ') and the filling / resin layer 5, that is, the arrow shown in FIG. The stress concentrates on the portion, and the solder bump 2 (2 ') is damaged. The solder bump 2 (2 ') is electrically connected between the semiconductor element chip 1 and the circuit board 4 and mechanically connected. Therefore, the solder bump 2 (2') is damaged. Immediately affect the electrical characteristics,
The semiconductor device may be defective or malfunction.

As a solution to the defect or failure caused by the thermal expansion, for example, (a) a circuit board is made of a material having a thermal expansion coefficient close to that of silicon (chip-on-wafer), (b) heat Forming the bump 2 (2 ') in a drum shape by noting that the location of the failure due to stress is near the interface where the bump 2 (2') and the semiconductor element chip 1 are in contact, or (c)
Attempts have been made to provide thermal stress resistance by forming a bump structure with a polyimide tape layer interposed therebetween.

[0006]

However, the above-mentioned means has the following problems. That is, the above (a)
If the circuit board is made of a material that matches the coefficient of thermal expansion of the semiconductor element chip to be mounted, the manufacturing cost of the circuit board will increase because complicated steps are required. Further, when the bump shape of (b) is formed in a drum shape, the semiconductor element chip and the circuit board are separated while the bumps are melted, and the separation distance is sufficiently calculated to make the bump shape a drum shape. If not set, there is a problem that not only the required shape cannot be maintained, but also a connection failure is likely to occur. Furthermore, in order to stack the bump structure of (c), a so-called bump seam is separately made, which requires a complicated process for manufacturing, resulting in cost increase and poor reliability of connection. There is a problem.

Further, in the case where the semiconductor element chip 1 is mounted face down, the heat generating surface of the semiconductor element chip 1 faces the surface of the circuit board 4, so that the amount of heat generated is accumulated in the semiconductor element chip 1. Often, it cannot easily perform a predetermined function because it is easy. As a measure against such a heat generation problem, for example, a heat radiation fin is provided on the back surface of the semiconductor element chip 1, or a metal piece (Cu piece or the like) having good thermal conductivity is used for the solder bumps 2, 2 '.
It is also practiced to embed heat in the inside. However, these means not only impair thinning or miniaturization of the semiconductor device, but also reliability and functional point of connection (high resistance by alloying Cu and solder bumps, etc.)
However, there is a problem with this and it is not satisfactory in practice.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a highly reliable semiconductor device by face-down mounting of a semiconductor element chip. That is, in a semiconductor device in which semiconductor element chips are mounted on circuit boards having different coefficients of thermal expansion in a face-down manner, it can be configured without complicated steps, and a fracture phenomenon in the bump region due to thermal stress, etc. It is an object of the present invention to provide a semiconductor device which solves the above problem and exhibits excellent heat dissipation.

[Structure of Invention]

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention has a gist that a bump has a double structure. That is, the present invention is a semiconductor device including a circuit board having required connection pads on a main surface thereof, and a semiconductor element chip mounted facedown on the connection pads of the circuit board via bumps, wherein the bumps are semiconductors. A first metal for electrically connecting the electrode pad of the element chip and a connection pad of the circuit board; and a second metal layer integrally covering the peripheral surface of the first metal, and the first metal The Young's modulus or thermal conductivity coefficient of the second metal is selected and set to be larger than the Young's modulus or thermal conductivity coefficient of the second metal.

More preferably, it is a semiconductor device in which the outer peripheral surface region of the bump is sealed by permeation / curing with an insulating resin, and the semiconductor device having such a structure has a semiconductor element chip via the bump. In a method of manufacturing a semiconductor device which is installed (mounted) on a circuit board surface face down, for example, a resist mask in which a central portion of a region corresponding to an electrode pad of a semiconductor element chip is opened is arranged,
First metal (single metal or alloy) filled and arranged in the opening and connected to the electrode pad surface, and then the opening of the resist mask is enlarged to fill the first metal. After the second metal (single metal or alloy) is integrally filled and arranged on the outer peripheral portion to form concentric bumps having a double structure, the double structure bump is formed on the pad surface on the circuit board surface. The bumps can be easily manufactured by aligning the bumps and heating and press-bonding them.

[0012]

According to the present invention, the bumps involved in the connection between the pads of the circuit board and the electrode pads of the semiconductor element chip have a Young's modulus or a thermal conductivity coefficient which gradually changes from the inner metal to the outer metal. Make up the composition. Therefore, in the case where the Young's modulus changes stepwise, the stress in the bump region is more dispersed and is less likely to concentrate in one place, and it is easy for defects to occur due to the difference in thermal expansion between the semiconductor element chip and the circuit board. Avoided or eliminated. on the other hand,
In the case of a structure in which the thermal conductivity coefficient changes, the heat generated in the semiconductor element space is easily dissipated to the circuit board by the inner metal (first metal) having a relatively large thermal conductivity coefficient. In addition to avoiding or eliminating the functional deterioration or failure of, it is possible to reduce the thickness.
That is, in any case, the semiconductor device functions as a highly reliable semiconductor device.

Further, in the above structure, a metal having a relatively high melting point is selected as the first metal, and a metal having a relatively low melting point is selected as the second metal, and the temperature is lower than the melting point of the first metal and the second metal is selected. When heated and pressure-bonded at a temperature higher than the melting point of the metal, the second metal forming a part of the bump spreads to the underlying metal interface, and the contact angle with the electrode pad of the semiconductor element is 90 °. And a reliable connection against heat stress and the like is achieved.

[0014]

The details of the present invention will be described below with reference to the illustrated embodiments.

Embodiment 1 FIG. 1 is a cross-sectional view showing an example of the essential structure of a semiconductor device according to the present invention, in which 1 is a semiconductor element chip and 4 is a circuit board. Then, the semiconductor element chip 1 is mounted (installed) face down on the surface of the circuit board 4 via the bumps 6 having a double structure. That is,
The semiconductor element chip 1 is provided on the surface, for example,
The electrode pad 1a made of Al is formed concentrically around the cylindrical Au 6a and the outer periphery of the cylindrical Au 6a in correspondence with the connection pad 4a formed by printing and firing gold paste on the surface of the circuit board 4. It is mounted facedown via bumps 6 having a double structure composed of In layers 6b integrally arranged. In FIG. 1, reference numeral 5 denotes a resin layer which is impregnated / cured (filled / arranged) between the mounted semiconductor element chip 1 and the surface of the circuit board 4 to seal the bump bonding portion.

In the above structure, in the bump 6 having a double structure, the inner Au 6a (gold bump) is the Al pad 1a on the surface of the semiconductor element chip 1 and the connection pad 4a on the surface of the wiring substrate 4. And are electrically connected to each other. In addition, an In-based alloy bump 6b that almost completely covers the outer peripheral surface of the inner gold bump 6a is a connection pad on the surface of the gold bump 6a and the circuit board 4.
4a is involved in electrical and mechanical connection.

Next, a method of manufacturing the semiconductor device having the above structure will be described.

First, the Al pad 1a on the surface of the semiconductor element chip 1
Gold balls are formed thereon by, for example, a ball bonding method, and the wires are cut to form gold pads 6a. On the other hand, for example, gold paste is printed / printed on the surface of the circuit board 4.
Bake it to form the required pattern, and then in the connection pad 4a
An In-based alloy bump 6b is formed by printing and reflowing a system-based paste. The gold bumps 6a formed here are cylindrical with a diameter of about 0.10 mm, and the In-based alloy bumps 6b are hemispherical with a diameter of about 0.15 mm. After that, the gold bump 6a and the In-based alloy bump 6b
By aligning and heating and pressure bonding, the gold bumps 6a are embedded in the In-based alloy bumps 6b, and the structure shown in FIG. 1 is realized.

FIG. 2 shows the relationship between the heating temperature and the connection resistance in the structure of the semiconductor device. As is apparent from FIG. 2, among the bump materials, the melting point t of the In-based alloy having a lower melting point is lower than that of the In-based alloy. The connection resistance increases at high temperatures because Au 6a diffuses into the In-based alloy 7b to form a new alloy. Therefore, all the manufacturing steps after the bump heating and pressure bonding are performed at a lower temperature.

FIG. 3 shows the relationship between the height of the bumps 7 and the connection resistance in the semiconductor device having the above structure.
The pressure of the pressure bonding condition was fixed to a temperature below the melting point of the In-based alloy 6b, and the pressure was changed to change the height of the bump. Here, the height h is the sum of the heights of the Au bumps 6a and the connection pads 4a on the surface of the circuit board 4. Therefore, in the region smaller than h, the structure of the present invention as shown in FIG. 1 is adopted. However, in a region larger than h, the sectional structure becomes as shown in FIG. In this region, the In-based alloy bump 6b exists between the Au bump 6a and the connection pad 4a on the surface of the circuit board 4, and the structure is different from that of the present invention, and the connection resistance is high. , Was also unreliable. in this way,
In order to realize the above structure, conditions such as temperature and pressure during heating and pressure bonding are important factors.

Embodiment 2 FIG. 4 is a cross-sectional view showing another example of the essential structure of a semiconductor device according to the present invention, in which 1 is a semiconductor element chip and 4 is a circuit board. Then, the semiconductor element chip 1 is mounted (installed) facedown on the surface of the circuit board 4 via the bumps 7 having a double structure. That is, the semiconductor element chip 1 has a columnar shape corresponding to the electrode pads 1a made of, for example, Al provided on the surface portion and the connection pads 4a formed by printing and firing a gold paste on the surface of the circuit board 4, for example. Cu 7a and this cylindrical Cu 7a
Is mounted facedown through bumps 7 and barrier metal 8 having a double structure made of eutectic solder 7b of Pb / Sn = 60/40 concentrically and integrally arranged on the outer periphery of the. In FIG. 1, 3 indicates a passivation film (layer) formed on the surface of the mounted semiconductor element chip 1 and 9 indicates an insulating layer provided on the surface of the circuit board 4.

In the above-mentioned structure, the bump 7 having the double structure has the inner Cu (copper bump) 7a and Pb / Sn =
60/40 eutectic solder 7b is interposed between the barrier metal 8 and the Al pad 1a on the surface of the semiconductor element chip 1 and the wiring board 4 respectively.
It is electrically and mechanically connected to the connection pad 4a on the surface.

Next, a method of manufacturing the semiconductor device having the above-mentioned structure will be described with reference to the sectional views of FIGS. Figure 5
(a) to (i) schematically show an embodiment of the manufacturing means. First, the Al pad 1a is exposed on the surface of the semiconductor element chip 1 on which the Al pad 1a is formed, and the passivation film 3 is formed.
Is formed, and Ti / Cu, for example, is vapor-deposited on the entire surface to form a barrier metal layer 8 (FIG. 5 (a)). Then, a thick film resist is formed on the formed barrier metal layer 8.
AZ4903 (Hoechst Japan Co., Ltd., trade name) is spin-coated to form a resist layer 10 with a film thickness of about 50 μm, and then one side of the electrode pad 1a having an opening (exposed surface) of 100 μm □ is exposed and developed by exposure and development. An opening 11 is formed in the resist layer 10 with a size of 60 μm, which is 40 μm smaller (FIG. 5 (b)).

As described above, after selectively opening 11 a part of the portion corresponding to the electrode pad 1a, a solution of 250 g / l of copper sulfate and 50 g / l of sulfuric acid (specific gravity 1.84) was added under non-ultraviolet light. Ti to form the barrier metal layer 8 at a bath temperature of 25 ° C.
/ Cu as cathode and high-purity copper as anode, current density 5
While applying A / dm ² and gently stirring, 35 μm of copper (Cu) 8a was plated on the opening 11 (FIG. 5 (c)). Then, the resist layer 10 is again exposed and developed to selectively remove the outer peripheral region of the copper (Cu) 7a deposited by the plating, and the resist layer 11 is opened to have a side dimension of 100 μm. 11 ′
(Fig. 5 (d)). After that, the plating bath is 40g / l of total tin.
, Stannous 35 g / l, lead 44 g / l, free boric acid 40 g / l, boric acid 25 g / l and glue 3.0 g / l, and the barrier metal layer 8 is formed at a bath temperature of 25 ° C. Cu as the cathode,
While using 40% tin as an anode and applying a current density of 3.2 A / dm ² and gently stirring, Pb / Sn = 40/6 in the opening 11 ′.
Alloy 8b of 0 was plated to a thickness of 35 μm (FIG. 5 (e)). Thus, after forming the double-structured bump 7 on the surface of the electrode pad 1a on the surface of the semiconductor element chip 1 through the barrier metal layer 8,
The resist layer 10 was dissolved and removed with acetone (FIG. 5 (f)).

Next, with a size of 120 μm, which is larger than the double-structured bump 7 formed on the surface of the semiconductor element chip 1,
The outer peripheral surface 20 μm width of the double-layered bump 7 is again coated with a positive resist OFPR-800 (trade name of Tokyo Ohka Co., Ltd.) and exposed with a mixed solution of ammonium persulfate, sulfuric acid and ethanol using this as a mask. Barrier metal layer 8
And Cu forming part of the barrier metal layer 8 exposed by a mixed solution of EDTA, ammonia and hydrogen peroxide are removed by etching, and then the positive resist mask is dissolved and removed with acetone. Did (Fig. 5 (g)
).

By the above, the required double structure type pumb 7
The semiconductor element chip 1 in which the above-mentioned is formed is held by a required collet (not shown) in a face-down positional relationship with the circuit board 4, and the bump 7 and the connection pad 4a on the surface of the circuit board 4 are For example, the bumps 7 that are aligned and correspond to each other by the alignment means using a half mirror.
And the connection pad 4a are brought into contact with each other (FIG. 5 (h)). At this time, the circuit board 4 is placed on a stage having a heating mechanism, and is higher than the melting point of the eutectic solder (Pb / Sn) 7b forming the bumps 7, and the melting point of Cu which is the first metal 7a. It has been preheated to about 280 ° C, which is a lower temperature. On the other hand, the collet holding the semiconductor element chip 1 is also heated in a nitrogen atmosphere at the same temperature as the stage temperature (280 ° C.) to melt the eutectic solder (Pb / Sn) 7b forming the bump 7. The semiconductor element chip 1 was electrically connected and mounted on the surface of the circuit board 4 (FIG. 5 (i)). Then, a silicone resin 5 was filled and cured between the semiconductor element chip 1 and the circuit board 4 (gap) so as to cover the mounted semiconductor element chip 1 to form a semiconductor device.

When the thermal resistance of the semiconductor element chip mounted on the semiconductor device configured as described above was evaluated, it was found that when the circuit board was an alumina substrate, the value was 20 ° C./W by natural cooling with the semiconductor element chip of 5 mm □. It was This value is 40 in the case of a semiconductor device in which the bumps are made of Cu only.
Although it is ℃ / W, it exhibits twice the heat dissipation characteristics. On the other hand, in the case of a semiconductor device in which the bumps are formed only by eutectic solder (Pb / Sn), in order to set the thermal resistance value to 20 ° C / W, five fins are provided on the back surface of the mounted semiconductor element chip. It is necessary to dispose a heat radiation fin, and the thickness of the semiconductor device is 1 / thick compared to the case where this heat radiation fin is arranged.
It decreases to about 10.

The coefficient of thermal expansion of silicon 3.5 × 10 ^-6 /
Equivalent to about twice the temperature (coefficient of thermal expansion 6.0 to 6.5 × 10 ^-6 /
In the case of a semiconductor device mounted on an alumina-based circuit board and configured as shown in FIG. 5, the contact angle between the bump and the electrode pad / connection pad is 60 °, and the temperature cycle test (- 55 ℃ (30 min) ~ 25 ℃ (5 min) ~ 150
No fracture was observed at the connection point even after 3000 cycles of ℃ (30 min) to 25 ℃ (5 min). Furthermore, when a high temperature and high humidity storage test was conducted, no failure was observed until the passage of 3000 hours. As described above, silicone resin or the like was filled and cured between the semiconductor element chip 1 and the circuit board 4 (gap). In the case of the constructed semiconductor device, no failure was recognized until 5000H.

The invention is not limited to the embodiments described above.

For example, in the first embodiment, the method of forming the bumps on the semiconductor element chip is not limited to the ball bump method, but may be a plating method. In that case, as a barrier metal on the Al pad of the semiconductor chip
After forming the Ti-W layer, gold electroplating is performed. Further, the connection pads on the circuit board may of course be formed by using another metal other than the gold thick film, or may be formed by a thin film, and the forming method may be vapor deposition, sputtering, or the like.
The bumps formed on the bumps are not limited to the In-based alloy, and the forming method may be plating or vapor deposition, and the outer metal (that is, the second metal) may be In or
It may be an alloy containing at least one of Pb, Bi, Sn, and Cd.

The resin used for the encapsulation is not limited to the silicone type, and for example, an acrylic type or an epoxy type, which has an encapsulating effect and is not particularly limited as long as it is an insulative resin, but compared with the metal used for the bumps. It is desirable that the Young's modulus is low. Further, it is preferable not to include a step that requires a temperature higher than the melting point of the lower one of the two kinds of metals forming the bump. Furthermore, the present invention is particularly effective when the semiconductor element chip is a solid-state imaging element chip and the wiring board is a transparent board in the visible light region.

Furthermore, in the structure of the second embodiment, the first metal 8a and the second metal 8b forming the double-structured bump 8 are limited to Cu and Pb / Sn eutectic solder, respectively. Alternatively, for example, it may be a component obtained by adding In, Sb or the like to Cu alloy or Pb / Sn, and the point is that the second metal has a high thermal conductivity coefficient as the first metal, or the second metal
With respect to the above metal, the first metal may be selected and set so as to have a high melting point, and the thicknesses of both of them forming the double structure are not limited to the above-mentioned numerical values. Furthermore, when forming a bump having a double structure by electroplating the barrier metal layer as a cathode, the configuration (dimensions, thickness, materials, etc.) of the barrier metal layer is not limited to the above examples, and electroplating may be performed. However, it may be formed by other means such as chemical plating, or structurally, it is sufficient that the second metal layer substantially covers the outer peripheral surface of the first metal.
Of course, the circuit board is not limited to the alumina type, but may be the silicon type, for example.

In addition, various modifications may be made without departing from the scope of the present invention.

[0034]

As described in detail above, according to the semiconductor device of the present invention, a defect occurs due to a difference in thermal expansion between the semiconductor element chip and the circuit board, a defect occurs due to accumulation of heat generated by the semiconductor element chip, or Breakage due to thermal stress in the bump connecting portion is easily and surely eliminated or prevented. That is, it is possible to realize and provide a semiconductor device in which a highly reliable connection is formed electrically and mechanically, and which is made thinner or smaller.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration example of a main part of a semiconductor device according to the present invention.

FIG. 2 is a curve diagram showing the relationship between the heating temperature and the connection resistance in the bump connection forming step in the semiconductor device according to the present invention.

FIG. 3 is a curve diagram showing the relationship between bump height and connection resistance in a semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view showing another configuration example of the main part of the semiconductor device according to the invention.

FIG. 5 schematically shows an embodiment of a method for manufacturing a semiconductor device according to the present invention, in which a is a sectional view showing a state in which a barrier metal layer is formed on the electrode pad surface of a semiconductor element chip, and b. Is a cross-sectional view showing a state in which a first metal forming a bump having a double structure is masked for electroplating, c
Is a cross-sectional view showing a state where a first metal forming a double-structure bump is electroplated, and d is a cross-sectional view showing a masking state for electroplating a second metal forming a double-structure bump, e is a cross-sectional view showing a state in which a second metal forming a double-structured bump is electroplated, f is a cross-sectional view showing a state in which masking is removed after forming the double-structured bump, and g is a barrier metal layer. Is a cross-sectional view showing a state in which the semiconductor element chip is selectively removed by etching, h is a cross-sectional view showing a state in which the semiconductor element chip is placed facedown on the circuit board surface, and i is a semiconductor element chip mounted facedown on the circuit board surface (bump FIG.

FIG. 6 is a cross-sectional view showing a structural example of bumps formed on a conventional semiconductor element chip surface.

FIG. 7 is a cross-sectional view showing another structural example of a bump formed on the surface of a conventional semiconductor element chip.

FIG. 8 is a cross-sectional view schematically showing the structure when bumping semiconductor element chips by a conventional face-down method.

FIG. 9 is a cross-sectional view schematically showing a structure in which a semiconductor element chip is bump-bonded under a connection condition other than the present invention.

[Explanation of symbols]

1 ... Semiconductor element chip 1a ... Electrode pad 2, 2 '
... bumps 3 ... passivation film 4 circuit board
4a ... Connection pad 5 ... Filling resin layer 6, 7 ... Double structure bump 6a, 7a ... First metal
6b, 7b ... second metal 8 ... barrier metal layer 9 ... insulating layer 10 ... resist (mask) layer 11,11 '... resist (mask) opening

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[Procedure amendment]

[Submission date] June 7, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Fig. 2]

[Figure 3]

[Figure 4]

[Figure 5]

[Figure 6]

[Figure 7]

[Figure 8]

[Figure 9]

Claims (1)

[Claims] 1. A semiconductor device comprising a circuit board having required connection pads on a main surface thereof, and a semiconductor element chip mounted face down on the connection pads of the circuit board via bumps, wherein the bumps are semiconductors. A first metal for electrically connecting the electrode pad of the element chip and a connection pad of the circuit board; and a second metal layer integrally covering the peripheral surface of the first metal, and the first metal The semiconductor device is selected and set to have a Young's modulus or thermal conductivity coefficient higher than that of the second metal.