JPH05342995A - Mis type cold cathode electron emitting apparatus - Google Patents

Abstract

PURPOSE:To heighten the probability that hot electron goes through a gate insulating film and a gate electrode and heighten the drawn electric current out of a cold cathode. CONSTITUTION:A MIS-type cold cathode electron emitting apparatus is composed of a cathode electrode 37 formed on a substrate 31, an ultra thin gate electrode 35 formed on the substrate 31 while having an ultra thin gate insulating film 34 between them, and anode electrode 38 set on the opposite to the cathode electrode 37. Regarding the MIS-type cold cathode electron emitting apparatus wherein electrons are emitted from the gate insulating film 34 to the anode electrode 38 by applying voltage between the cathode electrode 37 to the anode electrode 38, the gate insulating film 34 and a gate electrode 35 are formed on the substrate 31 while having a high resistance layer 3 between the substrate 31 and them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a MIS type cold cathode electron emission device.

[0002]

2. Description of the Related Art In recent years, the video / information related market has expanded,
High-definition, high-brightness, large-screen display elements are being developed as display elements. A display element using a conventional CRT is inevitably increased in volume with an increase in screen size, and its thinning has become a major issue.

Liquid crystal display elements (LCDs) are being rapidly mass-produced at present, and by taking advantage of their thinness, CR
It is a display element that may replace T. The LCD can be used as a full-color display, and is the most effective display element for TVs, personal computers, and car navigation display elements.

However, the response speed of LCD is several 10 msec.
And it is slower than CRT, and the viewing angle is limited (up and down 30 ~
60 °, about 60 ° to 120 ° on the left and right), and since it is not a self-luminous display element, illumination by a backlight is necessary, which makes it difficult to reduce power consumption. On the other hand, the field of vacuum microelectronics, which was created by combining vacuum tube technology and micromachining, has emerged, and the solidification technology for vacuum tubes is advancing rapidly.

FIG. 10 shows the Stanford Research Institute (SR)
I) Spindt type cold cathode electron source (microemitter) proposed by Spindt et al.
S., Electron Devices, 38, 10, 2355. 1991). In the figure, 1 is a Si substrate that functions as a cathode electrode, and may be glass or the like if it is flat. A metal gate electrode 3 is provided on the substrate 1 via an insulating film 2. Reference numeral 4 in the drawing denotes a cone-shaped metal tip provided in the gate opening 5. The operation of the device of FIG. 10 is as described below.

First, when a positive voltage is applied to the gate electrode 3 with respect to the substrate 1 connected to the metal tip 4 serving as an electron emission source, an electric field is concentrated at the tip of the metal tip 4,
Electrons are extracted from the metal tip 4 into the vacuum 6 by field emission. Therefore, the gate electrode 3 becomes an electron extraction electrode. Further, the anode electrode (not shown) is connected to Spindt.
A part of the electrons extracted by the gate electrode 3 can be taken out as an anode current by arranging them facing the micro-emitter and applying a positive voltage higher than the gate voltage to the anode electrode.

The device of this structure is a conventional CRT which is small in size,
It is a solid type and is extremely thin and can realize the function of a vacuum tube. Further, Spindt-type micro-emitters are arranged in an array, a large current can be taken out, and an electron emission source excellent in uniformity can be obtained by the effect of averaging. The microemitter is being applied not only to vacuum electronic circuits but also to the flat panel display shown in FIG.

FIG. 11 is a cross-sectional structure of a display element presented by LETI, France, in which a microemitter is applied to a flat panel display (IEDM91-197). Reference numeral 11 in the figure denotes a Spindt type micro-emitter, and an ITO anode transparent electrode 13 formed on a glass substrate 12 is formed facing this. A phosphor 14 is formed on the transparent electrode 13 so as to face the metal tip 4, and the electron 15 extracted from the metal tip 4 by the gate electrode 3 is a phosphor.
When it is incident on 14, it emits fluorescence 16 and can function as a self-luminous display element.

However, since the above-mentioned microemitter draws electrons into a vacuum by utilizing field emission, the material (related to work function), shape, tip
The anode current changes depending on the positional relationship of the gate, the degree of vacuum in the atmosphere, and the species of gas adsorbed on the tip surface.
Affects aging and noise. Therefore, it is a fact that there are many problems to be solved in practical use of the display device using the emitter, such as manufacturing accuracy and stability of the tip surface.

12 (A) and 12 (B) show a cold cathode electron source having a MOS type structure announced by Tohoku University Research Institute ('92. Spring, Japan Society of Applied Physics 31a-Nc-5). However, the same figure (A) is its sectional structure, and the same figure (B) is X- of the same figure (A).
It is a schematic diagram of the energy band structure of X.

Reference numeral 21 in the figure denotes an n-type Si substrate. On this substrate 21, a thick (0.45 μm) field insulating film (S
iO ₂ ) 22 and extremely thin (~ 10 nm) gate insulating film (Si
O ₂ ) 23 is formed. An extremely thin (6 nm) gate electrode 24 made of Al is formed on the gate insulating film 23. This gate electrode 24 has a contact electrode
25 are connected. An anode electrode 26 is disposed above the substrate 21, and a cathode electrode 27 is disposed on the back surface of the substrate 21.
Is provided. Then, a positive voltage is applied to the anode electrode 26, and a negative voltage is applied to the cathode electrode 27.

When this voltage is applied, an electron accumulation layer is formed on the surface of the substrate 21 as shown in the energy band structure of FIG.
28 is formed, and the electrons tunnel through the gate insulating film 23 by the electric field of the gate electrode 24 to which a positive voltage is applied to the substrate 21, and reach the gate electrode 24. Since the mean free path of electrons in the gate electrode 24 is 2.4 nm,
By providing the gate electrode 24 having the same thickness as this, a part of the electron group 25 tunneled through the gate insulating film 23 is drawn to the anode electrode 26 and drawn into the vacuum 29 as free electrons 30.

This structure is characterized in that the electron emission surface is SiO ₂
Since it is covered with and is passivated, it is more stable than the conventional Spindt type cold cathode in which the electron emission surface is exposed in vacuum.

[0014]

However, the MOS
The type tunnel cathode can be expected to have good stability, which is not possible with conventional cold cathodes, and can draw electrons at a low voltage, but has a drawback that the drawing current is small. This is because the gate insulating film 23 through which electrons are tunneled is relatively thick, the thickness of the gate electrode 24 is thicker than the mean free path of electrons, and the energy of electrons in the Si substrate 21 is small. It is considered that the energy of electrons is small in order to tunnel through the insulating film 23 and penetrate the gate electrode 24.

The present invention has been made in view of the above circumstances, and the energy of electrons is increased by forming a structure for accelerating electrons in the substrate to increase the probability that hot electrons penetrate through the gate oxide film and the gate electrode. It is an object of the present invention to provide a MIS-type cold cathode electron emission device which can increase the extraction current from the cold cathode.

[0016]

The present invention is directed to a cathode electrode formed on a substrate, an ultrathin gate electrode formed on the substrate via an ultrathin gate insulating film, and a cathode electrode facing the cathode electrode. An MIS cold-cathode electron-emitting device that emits electrons from the gate insulating film to the anode electrode by applying a voltage to the cathode electrode and the anode electrode. In the MIS type cold cathode electron emission device, the gate insulating film and the gate electrode are provided via a resistance layer.

In the present invention, the high resistance layer preferably has an impurity concentration of 1 × 10 ¹⁴ atom / cm ^3. Below. The reason for this is that if this value is exceeded, it is difficult to obtain a depletion layer having a sufficient width to serve as an electron acceleration region near the substrate surface.

In the present invention, the thickness of the ultrathin gate insulating film and the ultrathin gate electrode is preferably several nm to ten nm. This is because hot electrons accelerated in an electron acceleration region when a voltage is applied to the gate electrode or the like are efficiently tunneled and penetrate the gate insulating film and the gate electrode.

[0019]

According to the present invention, a region for accelerating electrons is provided in the substrate, hot electrons accelerated in the depleted region are efficiently tunneled, and the amount of electrons penetrating the gate electrode is increased. It is possible to obtain a larger amount of electrons at a low voltage as compared with the amount of electrons obtained from the tunnel cathode.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) Reference will be made to FIGS.

In the figure, 31 is a high concentration n ⁺ Mold (100) Si
It is a substrate. On this substrate 31, p ⁻ formed by epitaxial growth A layer or i layer (high / low resistance layer) 32 is formed. Here, the substrate 31 and the high resistance layer 32 are collectively referred to as a base. A thick S of about 0.5 μm is formed on the substrate.
An iO ₂ film (field oxide film) 33 is formed, and a thermal oxide film (gate insulating film) 34 having a thickness of several nm is formed in each gate opening 33a of the field oxide film 33. A gate electrode having a thickness of several nm is formed on the gate insulating film 34.
35 is formed so as to extend on the field oxide film 33.
Here, the gate electrode 35 is made of metal or highly doped polycrystalline silicon. A gate contact electrode 36 connected to the gate electrode 35 is formed on the field oxide film 33. A cathode electrode 37 is formed on the back surface of the substrate 31. An anode electrode 38 is arranged above the substrate so as to face the cathode electrode 37. In FIG. 1B, 39 is the end of the gate contact electrode 36, 40 is the end of the gate electrode 35, 41 is the end of the gate opening 34, 42 is the end 41 of the gate opening and the field oxidation. A slanted portion between the end portions of the film 33, and 43 denotes a gate contact electrode pad.

Next, the operation of the MIS type cold cathode electron emission device having the above structure will be described. At this time, the cathode electrode 37 is grounded as shown in FIG.
A positive voltage V _G is applied to 36 and a positive voltage V _A is applied to the anode electrode 38. The energy band diagram at this time is schematically shown in FIG.

By applying a positive voltage V _G to the gate electrode 35, the high resistance layer 34 of the substrate 31 is depleted, and this depletion layer is used as an electron acceleration region. The electrons 44 are injected into the depletion layer from the substrate 31 and accelerated, and tunnel through the gate insulating film 34 to reach the gate electrode 35. Reference numeral 45 in the drawing denotes an electron group extracted from the substrate 31 to the gate electrode 35, and a part of the electron group is emitted to the anode electrode 38. 47 in the figure is a group of electrons emitted to 46 in vacuum.

In the band diagram of FIG. 12B (conventional), the energy of electrons is small because the surface is an n-type storage layer, and the energy of the electrons is tunneled through the gate insulating film by the gate voltage, and the vacuum is generated at the anode electrode. 1D according to the first embodiment, a depletion layer is intentionally provided in the substrate 31 to inject electrons into the depleted high resistance layer 32 from the substrate 31 side to accelerate. By increasing the energy of the electrons by doing so, the electrons can be easily tunneled through the gate insulating film 34 by the voltage applied to the gate electrode 35. The high-energy electrons pass through the gate electrode 35 and jump out into the vacuum, and are trapped by the anode electrode 38 to which a voltage higher than the gate voltage is applied, resulting in an anode current.

As described above, according to the first embodiment, the high concentration n ⁺ Since the high / low resistance layer 32 formed by epitaxial growth is provided on the mold (100) Si substrate 31, and the gate insulating film 34 and the gate electrode 35 each having a thickness of about several nm are provided therethrough. a positive voltage V _G to the gate contact electrode 36, a positive voltage V _a is applied to the anode electrode 38, and by grounding the cathode electrode 37, intentionally provided depletion in the substrate 31, the substrate 31 side The electrons can be easily tunneled through the gate insulating film 34 by the voltage applied to the gate electrode 35 by injecting and accelerating the electrons into the depleted high resistance layer 32 to accelerate the electrons.

In the first embodiment, the substrate (1
Although the (00) Si substrate is used, the present invention is not limited to this, and a (111) Si substrate or a Si semiconductor substrate such as GaAs may be used.

In the first embodiment described above, the case where the planar shapes of the gate electrode, the gate contact electrode and the gate opening are rectangular is described, but the present invention is not limited to this, and may be circular as shown in FIG. Good. (Example 2)

Reference will be made to FIGS. 3 (A) and 3 (B). However, the same members as those in FIG. 51 in the figure
Is a gate electrode in which a plurality of fine holes 52 are formed in a grid pattern at a position corresponding to the gate insulating film 34.

In the second embodiment, as in the first embodiment, the cathode electrode 37 is grounded and a positive voltage is applied to the gate electrode 51 via the gate contact electrode 36. Due to this gate voltage, the high resistance layer 32 is depleted, and the electrons injected from the substrate 31 into the depletion layer are accelerated in the depletion layer and become a high energy state, and then penetrate through the gate insulating film 34 by tunneling. Here, since a plurality of fine holes 52 are opened in the gate electrode 51, the electrons that become the anode (not shown) current that is taken out into the vacuum pass through the fine holes 52 and the components that have passed through the gate electrode 51. It is the sum of the ingredients. Therefore, according to the second embodiment, by optimizing the size of the fine holes 52 of the gate electrode 51 and the thickness of the high resistance layer 32, it is expected that a larger anode current than that of the first embodiment can be obtained.

FIGS. 4 (A) to 4 (C) show the first and second embodiments.
FIG. 3 is a band diagram when an electron is drawn out by the device according to FIG. Electrons injected from the substrate 31 by applying a positive voltage to the gate electrode 35 (or 51) with respect to the substrate 31 to deplete the high resistance layer 32.
It shows that 44 is accelerated and taken out into the vacuum 46.
Not all hot electrons reaching the interface 53 of the substrate 31 / gate insulating film 34 (Si / SiO ₂ ) tunnel through the gate insulating film 34, and electrons are accumulated at the interface (FIG. 4 (B)). ). The positive voltage applied to the gate electrode reduces the width of the depletion layer 54 formed in the high resistance layer 32, and the barrier potential between the substrate 31 and the high resistance layer 32 (54 indicates the substrate 31 and the high resistance layer 32). Substrate due to depletion layer formed between)
The electrons injected from 31 are cut off.

By the way, the electrons 55 accumulated at the Si / SiO ₂ interface 53 are lost by tunneling through the gate insulating film 34 by the gate voltage, so that the width of the depletion layer 54 expands again and the gap between the substrate 31 and the high resistance layer 32 is increased. The barrier potential of the substrate 31 is lowered, and electrons are injected from the substrate 31. Therefore, in reality, it seems that the band state intermediate between those in FIG. 4 (A) and FIG. 4 (B) appears, and the injection of electrons into the depletion layer is expected to continue, but the amount is small and the acceleration of electrons is also high. It will not be done enough.

Therefore, as shown in FIG. 4C, a negative voltage is applied to the gate electrode to recombine the electrons 55 accumulated at the Si / SiO ₂ interface with the holes 56 to eliminate them. After that, as shown in FIG. 4A again, a positive voltage is applied to the gate electrode to deplete the high resistance layer 32 and at the same time lower the potential barrier formed between the substrate 31 or the high resistance layer 32. Then, the amount of electrons injected from the substrate 31 into the depletion layer 54 is increased and sufficiently accelerated, and then the gate insulating film 34 is tunneled. By repeating the operation of FIGS. 4A and 4C by the drive circuit, a large amount of hot electrons can be extracted into a vacuum and extracted as an anode current. (Example 3)

Referring to FIG. However, the same members as those in FIG. The device of FIG.
Type MIS structure is introduced into a micro-emitter, the MIS electrode is used as a first gate electrode, and a second gate electrode that surrounds the periphery of the micro-emitter is separately provided to increase the amount of electrons extracted from the micro-emitter. Is.

Reference numeral 61 in the figure denotes a cone-shaped micro-emitter formed on a part of the surface of the high resistance layer 32. A first gate insulating film 62 having a thickness of several nm to 10 nm is formed on the surface of the micro-emitter 61. A first gate electrode 63 having a thickness of several nm is formed on the first gate insulating film 62 so as to extend onto the field oxide film 33. The first gate electrode 63 is made of metal or highly doped polycrystalline silicon. The first gate electrode 63 includes
The first gate contact electrode 64 is connected. A second gate electrode 65 is formed on the first gate electrode 63 on the field oxide film 33 so as to surround the micro emitter 61 via an insulating film 64.

In the third embodiment, the first gate electrode 63 has the first
A positive voltage is applied to the cathode electrode 37 via the gate contact electrode 64 to deplete the high resistance layer 32 as in the first embodiment, and electrons are injected from the substrate 31 to the high resistance layer to form a depletion layer. After accelerating, the first gate insulating film 62 is tunneled,
The electrons reaching the first gate electrode 63 and penetrating through the first gate electrode 63 are drawn by a positive voltage applied to an anode electrode (not shown) and taken out as an anode current. By applying a positive voltage to the second gate electrode 65 also with respect to the cathode electrode 37 to concentrate the electric field at the tip of the microemitter 61, it is possible to promote the field emission of electrons from the microemitter 61. (Example 4)

Reference will be made to FIGS. 6A and 6B. However, the same members as those in FIG. Example 4 is an example in which the MIS field emission electron source of Example 1 or 2 is integrated and applied to a flat panel display.

In FIG. 6A, one pixel is one M
It is composed of an IS type cold cathode electron source 71 and a MOS transistor 72. The MIS cold cathode electron source 71 has a gate insulating film 34 and a gate electrode 35. The MOS transistor 72 is
N-type source / drain 74, 75 formed in the P-well 73
And a gate electrode 77 formed on the P well 73 via a gate oxide film 76. The gate oxide film 76 corresponding to the source region 74 is partially removed, and a metal wiring 78 connects the source region 74 and the gate electrode 35. The gate oxide film 76 corresponding to the drain region 75 is also partially removed, and a drain electrode 79 is provided there.

Normally, the substrate 31 and P well 73 are grounded, and M
A positive voltage is applied to the gate electrode 77 of the OS transistor 72, and M
The MIS cold cathode electron source 71 is driven by turning on the OS transistor 72 and transmitting the drain voltage to the gate electrode 35 of the MIS cold cathode electron source 71 through the drain electrode 79.

In FIG. 6B, a MOS transistor
The source region 74 of 72 is the gate electrode 35 of the cold cathode electron source 71.
The drain region 75 is connected to the X line 80 and the gate electrode
77 is connected to the Y line 81. The Y line 81 is connected to the horizontal shift register 82, and the X line 80 is connected to the MOS transistor 72.
To the pulse generator 83, and the gate electrode 77 of the MOS transistor 72 is connected to the vertical shift register 84. The operation of the device having such a configuration is as follows.

In FIG. 6B, X-1 of X line 80
Gate electrode 77 of the MOS transistor 72 connected to
Apply a positive pulse voltage from the vertical shift register 84 to
At the same time, by applying a positive pulse voltage from the horizontal shift register 82 to Y-1 of the Y line 81, one cold cathode electron source 71 (eg 71a) is selectively connected to the pulse generator 83 in response to this. To be done.

By applying a positive voltage or a pulse voltage in which positive and negative are alternately repeated from the pulse generator 83 to the cold cathode electron source 71a, an electron beam is extracted from the cold cathode electron source 71a and arranged opposite to this. By applying a positive voltage higher than that of the gate electrode 35 of the cold cathode electron source to the transparent anode electrode (not shown) having the inclined plate, it is possible to obtain light emission from the fluorescent plate on which the cold cathode electron source 71a is located.

In the vertical shift register 84, X- of the X line 80
1 is selected, and Y-1 and Y are sequentially output from the horizontal shift register 82.
By applying a pulse voltage for selecting −2, Y−3, ..., The cold cathode electron source 71 is scanned in the lateral direction, and the amount of the electron beam emitted from the cold cathode electron source 71 by the pulse generator 83 is changed. The light emission pattern of the flat panel display can be arbitrarily changed by controlling. The brightness of this light emission pattern can be changed in an analog manner by controlling the pulse voltage from the pulse generator. (Example 5)

Reference will be made to FIGS. 7 (A) and 7 (B). However, the same members as those in FIG. In Example 5, hot electrons traveling laterally in a depletion layer formed on the surface of a Si substrate were provided on the depletion layer by M.
By applying a positive voltage to the IS electrode, the MIS structure is tunneled and the electrons are taken out into a vacuum.

Reference numeral 91 in the figure denotes a p-type Si substrate. In the element region surrounded by the field oxide film 33 of the substrate 91, n
⁺ The source and drain regions 92 and 93 of the mold are formed separately from each other, and p ⁻ is formed between the source and drain regions 92 and 93. Alternatively, an i layer (high resistance layer) 94 is formed. On the device region surrounded by the field oxide film 33, a thickness of several nm to
A gate electrode 96 having a thickness equal to or less than the mean free path of electrons is formed through a gate insulating film 95 having a thickness of about 10 nm.

In the device having such a structure, the source region
92 is grounded, and a positive voltage V _D is applied to the drain region 93. The high resistance layer 94 formed on the surface between the source region 92 and the drain region 93 is depleted by the drain voltage V _D , and an electron current flows between the source region 92 and the drain region 93 at the gate voltage V _G = 0V. This electron current is generated by injecting electrons into the depleted channel by lowering the barrier potential on the gate electrode 96 side. The injected electrons are accelerated between the depletion layers, become hot electrons, and reach the drain region 93. Here, when a positive voltage is applied to the gate electrode 96, the hot electrons tunnel through the gate insulating film 95, reach the gate electrode 96, and further jump out into the vacuum to face the substrate 34 in the vacuum. Anode electrode (not shown) to which a higher voltage is applied
Is taken into. It should be noted that 98 in the figure indicates the traveling direction of hot electrons, and a part thereof flows into a vacuum and the rest flows into a drain region 93. In the fifth embodiment, as shown in FIG. 7B, the gate electrode 96 partially covers the source / drain regions 92 and 93, but the channel current is the gate voltage V _G = 0.
Since the drain voltage V _D flows even when the voltage is V, the gate electrode 96 does not necessarily have to cover the source / drain regions 92 and 93.

In the fifth embodiment, the extraction of hot electrons into the vacuum is performed by the positive gate voltage V _G applied to the gate electrode 96. However, as shown by 97 in FIG. By applying a magnetic field directed to the side opposite to this side, the amount of extracted electrons in the vacuum can be increased.

FIGS. 8A to 8C are layout diagrams of MIS type cathodes different from those in FIG. 7B. In particular,
8A shows an example having two source regions 101 for one drain region 100, and FIG. 8B shows an example having four source regions 102 for one drain region 100. (C) shows examples in which a circular sole region is shown around the circular drain region 100. Note that 103
The shaded area indicates the gate electrode. This gate electrode can be arranged in a mesh shape. (Example 6)

Referring to FIG. However, the same members as those in FIGS. 1 and 7 are designated by the same reference numerals and the description thereof will be omitted. This Example 6 is
High-energy electrons due to avalanche breakdown of a reverse-biased pin diode are drawn into a vacuum by a MIS type electrode.

Reference numeral 111 in the figure is a depletion layer formed in the high resistance layer 32. On the surface of the depletion layer 111, a plurality of n ⁺ The diffusion layer 112 is formed in a lattice shape. Part of diffusion layer 11
2 is n ⁺ for electrically contacting through the opening formed in the interlayer insulating film 113. A contact electrode 114 is formed. p ⁺ Type Si substrate 31 and n ⁺ The diffusion layer 112
And constitute a pin diode.

The two pin diodes are reverse biased and deplete the high resistance layer 32. Furthermore, when the reverse bias voltage is increased, avalanche breakdown occurs. This is because electrons accelerated in the depletion layer have high energy and
Hole pairs are generated, and the generated electrons are successively depleted.
A large current is generated through the process of generating electron-hole pairs in 1. The electrons flow in the depletion layer 111 toward the surface of the high resistance layer 32, and are taken into the diffusion layer 112. Since the diffusion layer 112 is formed in a lattice shape, some electrons reach the high resistance layer 32 / gate insulating film in an accelerated state, and are tunneled by the positive gate voltage V _G applied to the gate electrode to cause the gate insulating film to tunnel. Through the gate electrode to reach the gate electrode, part of which is pulled out into the vacuum through the gate electrode and is disposed to face the substrate 31 to be an anode electrode (not shown) which is biased to a voltage higher than V _G or V _R. It is taken in and becomes the anode current. At this time, by applying a magnetic field in the direction in which the electrons flow, the electrons spiral,
The generation of electron-hole pairs can be promoted and the avalanche breakdown voltage can be lowered.

Although the above embodiments 1 to 6 describe the case where the thermal oxide film is used as the gate insulating film, the present invention is not limited to this, and a thermal nitride film may be used. Further, the MOS transistors can be integrated on the same substrate in any of the embodiments, and a MIS type cold cathode drive circuit and the like can be included. Furthermore, by using a transparent electrode such as ITO as an anode electrode and forming a phosphor on the transparent electrode, it is possible to apply to a flat package play as a self-luminous display element.

[0052]

As described in detail above, according to the present invention, a region for accelerating electrons is provided in the substrate, hot electrons accelerated in the depleted region are efficiently tunneled, and the hot electrons serve as a gate insulating film. It is possible to provide a MIS-type cold cathode electron emission device capable of increasing the probability of penetrating through the gate electrode and thus increasing the current drawn from the cold cathode.

[Brief description of drawings]

1 is an explanatory view of a MIS type cold cathode electron emission device according to Embodiment 1 of the present invention, FIG. 1 (A) is a sectional view, and FIG.
1B is a plan view of FIG. 1A, and FIG. 1C is FIG. 1A.
FIG. 1D is a cross-sectional view showing a state in which a bias voltage is applied to the anode of FIG. 1, and FIG. 1D is a bandgap diagram taken along line XX of FIG.

FIG. 2 is a plan view of a device showing a modification of the electron emission device of FIG.

3A and 3B are explanatory views of a MIS type cold cathode electron emission device according to Example 2 of the present invention, FIG. 3A being a cross-sectional view and FIG.
(B) is a plan view of FIG.

FIG. 4 shows energy band diagrams at the time of drawing out electrons in FIGS. 1 and 2.

FIG. 5 is a sectional view of an MIS type cold cathode electron emission device according to Example 3 of the present invention.

6A and 6B are explanatory views of a MIS type cold cathode electron emission device according to Embodiment 4 of the present invention, FIG. 6A being a sectional view and FIG.
(B) is a circuit diagram of the same figure (A).

7A and 7B are explanatory views of a MIS type cold cathode electron emission device according to Example 5 of the present invention, FIG. 7A being a cross-sectional view and FIG.
FIG. 3B is a plan view of the main part of FIG.

8 is a diagram showing various layouts of source and drain regions in a device having the same principle as that of the electron emission device of FIG. 7.

FIG. 9 is a sectional view of a MIS type cold cathode electron emission device according to Example 6 of the present invention.

FIG. 10 is a schematic sectional view of a Spindt type micro-emitter.

FIG. 11 is a schematic diagram showing an application example of the micro-emitter of FIG. 11 to a flat panel display.

12A and 12B are explanatory views of a conventional MOS type cold cathode electron emission device. FIG. 12A is a sectional view and FIG. 12B is the same figure.
Energy band diagram along the line XX of FIG.

[Explanation of symbols]

31 ... Si substrate, 32 ... High resistance layer, 33 ... Field oxide film,
34, 62, 67 ... Gate insulating film, 35, 51, 63, 65, 77 ... Gate electrode, 36, 64 ... Gate contact electrode, 37 ... Cathode electrode, 38 ... Anode electrode, 61 ... Micro-emitter, 71 ...
MIS type cold cathode electron beam, 72 ... MOS transistor, 73 ...
P well, 74 ... Source region, 75 ... Drain region.

Claims (1)

[Claims] 1. A cathode electrode formed on a substrate, an ultrathin gate electrode formed on the substrate via an ultrathin gate insulating film, and an anode electrode provided opposite to the cathode electrode. A MIS-type cold cathode electron emission device comprising: a gate insulating film to emit electrons to the anode electrode by applying a voltage to the cathode electrode and the anode electrode. A MIS-type cold cathode electron emission device comprising a film and a gate electrode.