KR100235318B1 - Emitter array of field emission device and manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emitter array of a field emission device and a method of manufacturing the same, wherein a transistor having a MOSFET structure in which a drain region for draft is extended to an emitter region is formed on one side of a semiconductor substrate, and the semiconductor of the drain is formed. The substrate is etched to form a conical emitter, but the drift region is quickly formed by the RTP method so that there is no other effect on the device, and the nitride film is formed thick after the transistor is formed so that the transistor is not affected during the emitter array process. As the current limiter (CURRENT LIMITER) prevents excessive current flow by adjusting the channel width of the EDMOSFET, and by integrating the high voltage device with the emitter array, the driver LSI is formed in the region of the high voltage device and the low voltage logic. The circuit can be disadvantageous, so that the formation of the device is easy, and the process yield and It is possible to improve the reliability of the party action.

Description

Emitter array of field emission device and its manufacturing method

1a to 1e is a manufacturing process diagram of a high voltage device used in the emitter array of the field emission device according to the present invention.

2a to 2k is an emitter array manufacturing process diagram of the field emission device according to the present invention.

* Explanation of symbols for main parts of the drawings

1: semiconductor substrate 2: P well

3: N-well 4: N + well

5: gate oxide film 6: polysilicon layer

7: source region 7A: first P + region

7B: N + region 7C: 2P + region

8: field plate 9: source contact

10: nitride film 11, 16: groove

12 emitter 13: thermal oxide film

14 oxide film 15 first photosensitive film

17 conductive layer 18 second photosensitive film

19: control hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emitter array for use in a field emission display (FED) and a method of manufacturing the same, and more particularly, to an E.MOS field effect transistor using Resurf, a transistor for high voltage power. Drain MOS Field Effect Traisister (hereinafter referred to as RESURF EDMOSFET) is used to expand the ohmic contact of the drain to secure the space where emitter tips are formed, to ensure sufficient position between emitter array cells, The present invention relates to an emitter array of a field emission type device capable of active matrix addressing by forming a tip and inserting a power device for each pixel, thereby providing a method of manufacturing the same.

FED, also called an electroluminescent display device, is a display device that uses a field emission device that emits cold electrons by applying a relatively low voltage, for example, a voltage of about tens to 10 kV, by using a phenomenon in which an electric field is concentrated on an angled portion. Is a kind of flat panel display device that appeared in the research process of thinning of CRT, and it has the advantages of high definition of CRT, light thin type of liquid crystal display (hereinafter referred to as LCD), and low manufacturing cost than light emitting diode. It is attracting attention as an image display element.

In particular, the FED can not only manufacture the thin and thin, but also solve the problems of process yield, manufacturing cost, and enlargement, which are crucial disadvantages of the LCD.

That is, in case of LCD, even if one unit pixel is defective, the whole product is treated badly. However, FED has a smaller number of unit pixels in one pixel group, so even if one or two unit pixels are defective, There is no problem in operation, and the yield of the whole product is improved.

In addition, the FED is simpler in structure than LCD, has low power consumption, and is suitable for portable display devices.

A typical FED consists of a light emitting unit arranged on each of the front substrates and a field emitter arranged on the rear substrate, and the field emitting unit includes a cathode and an emitter protruding conically from the cathode. The cathode is composed of a gate partitioned with an insulating layer.

Here, a removal hole for exposing a cathode is formed by removing a gate and an insulating layer on an upper portion of the portion intended as the emitter, and an emitter is formed on the cathode exposed by the control hole.

The light emitting part is composed of an anode formed of a transparent electrode such as ITO on the front substrate and a fluorescent layer 9 coated on the anode.

The FED of the structure has an anode, a gate, and a cathode emitter having a three-pole tube corresponding to an anode, a grid, and a cathode of a CRT.

As a result, a large amount of electrons (-) are emitted from the emitter by a strong electric field between the gate and the emitter, and these electrons (-) are accelerated by an anode to which a high voltage is applied and collide with the fluorescent layer to emit visible light.

Since the FED has a relatively high voltage applied to the pixel compared to the logic circuit, the FED includes a transistor for protecting and switching the pixel. The transistor of the conventional FED is formed separately from the pixel and connected to the wiring.

Therefore, the conventional FED has a problem in that the transistor and the pixel forming process influence each other, so that the breakdown voltage of the transistor is low or the tip formation of the pixel is difficult, resulting in inferior process yield and reliability of device operation.

The present invention is to solve the above problems, an object of the present invention is to expand the ohmic contact portion of the drain by using a RESURF EDMOSFET to secure the space for forming the emitter tip, the silicon etching process on the portion Emitter array of field emission type devices that can form a tip to secure sufficient positions between emitter array cells, and enable active matrix addressing by inserting power devices for each pixel to improve process yield and reliability of device operation In providing.

Another object of the present invention is to integrate a high voltage device with an emitter array to separate the region of the high voltage device and the low voltage logic circuit area in the process of forming the driver integrated circuit, and to form a stable high voltage device having a high breakdown voltage. The present invention provides a method of manufacturing an emitter array of a field emission device that can improve the reliability.

The feature of the emitter of the field emission device according to the present invention for achieving the object as described above, the field emission comprising a plurality of emitter array formed on a semiconductor substrate, and a transistor connected to the emitter array An emitter array of a device comprising: emitter tips of an emitter array formed in the drain region of the transistor.

Another feature of the emitter of the field emission device according to the present invention is a transistor of a MOSFET structure formed on a semiconductor engine of the first conductivity type and an emitter tip of an emitter array formed in the drain region of the transistor. 2. An emitter array of a field emission type device comprising: a source region formed of a high concentration impurity of a first conductivity type on a semiconductor substrate on one side of a gate of the transistor, and an impurity of a second conductivity type on one side of the source region; And a source contact region formed therein and a drain region formed of an impurity of a second conductivity type formed on the semiconductor substrate on the other side of the gate.

A feature of the method of manufacturing an emitter array of a field emission device according to the present invention for achieving another object is to form a transistor having a MOSFET structure on one side of a semiconductor substrate, the drain of the transistor to extend to the emitter region And etching the semiconductor substrate of the drain to form a conical emitter.

Hereinafter, an emitter array of a field emission device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

1a to 1e is a manufacturing process diagram of a high voltage device used in the emitter array of the field emission device according to the present invention, the completeness of the high voltage device RESURF EDMOSFET is shown in FIG. Explain.

First, the first conductivity type; For example, a P well 2 having a predetermined depth is formed on a P-type silicon semiconductor substrate 1, and N- is made of low-concentration second conductive impurity that is a drift region on one side of the P well 2. After the well 3 is formed, a drain 4 of N +, which is a second concentration impurity of high conductivity, is formed on one side of the N-well 3 by a method of rapid thermal processing. Here, the drain 4 becomes an emitter formation region of the pixel. (See also Figure 1a).

Then, a low concentration of P impurity may be ion-implanted to prevent the rapid expansion of the depletion region on the exposed P well 2 surface to increase the breakdown voltage at the drain side, thereby reducing the depth of the edge portion of the N-well 3. (See also part 1b).

Thereafter, P-type impurities such as boron ions are implanted into P (2), which is supposed to be a source, to form the first P + region 7A at a predetermined depth, and then gate on the entire surface of the semiconductor substrate 1 The polysilicon layer which forms the oxide film 5 and becomes a gate electrode of a MOSFET on the gate oxide film 5 of the P well 2 adjacent to the boundary between the N-well 3 and the P-well 2 is formed. The pattern 6 is formed (see also 1c).

Thereafter, an N + region 7B is formed on the upper side of the first P + region 7A, and the second P + region is in contact with the first P + region 7A and the N + region 7B on the outer P well 2 thereof. 7C is formed to form a source electrode composed of the first and second P + regions 7A, 7B and N + region 7B. In this case, the N + region 7B and the second P + region 7C are formed by one drive-in process after each ion implantation (see also FIG. 1d).

Then, the gate oxide film 5 above the N + region 7B is removed to form a source contact 9, and a field plate 8 having a polysilicon layer pattern for preventing electric field concentration at the junction portion is formed. Complete the RESURF EDMOSFET (see also section 1e).

After forming the RESURF EDMOSFET shown in FIG. 1E as described above, an emitter array of field emission devices is formed in the drain 4 region of the RESURF EDMOSFET.

2A to 2K are process charts for manufacturing an emitter array of a field emission device according to the present invention, after forming the RESURF EDMOSFET through the process of FIGS. 1A to 1E, the drain 4 of the RESURF EDMOSFET is formed. An emitter array of field emission devices is formed in the region.

First, a nitride film pattern 10 is formed in the semiconductor substrate 1 to expose a predetermined portion of the emitter and a predetermined control hole (see FIG. 2A), and the semiconductor substrate 1 exposed to the nitride film pattern 10 is formed. ) Is isotropically dry-etched by the Reactive Ion Etching (RIE) method to form the emitter 12, which is a groove 11 and a silicon pillar protruding therein (see also FIG. 2B).

Thereafter, a predetermined thickness of the exposed semiconductor substrate 1 is thermally oxidized to form a thermal oxide film 13 to form a tip portion of the emitter 12 in a shape suitable for electron emission, for example, a cone shape. (See also 2c).

Thereafter, the nitride film pattern 10 was removed, and the oxide film 14 was applied to the entire surface of the structure by chemical vapor deposition (hereinafter referred to as CVD) method (see FIG. 2D), A first photosensitive layer 15 pattern is formed on the oxide layer 14 to expose the oxide layer 14 on the silicon pillar 12. (See also section 2e).

Then, the oxide layer 14 exposed by the first photoresist layer 15 pattern is etched to an end of the emitter 12, that is, a vertex of the cone, to the stage just before the exposure ceramic by anisotropic etching. It forms, (refer also to 2f), and removes the said 1st photosensitive film 15 pattern. (See also 2g).

Thereafter, the conductive layer 17 serving as a gate of the field emission device is formed on the entire surface of the structure by a conductive material, for example, a metal layer such as Mo, W, and the second photosensitive film 18 is formed on the entire surface of the structure. Apply. (See also 2h).

Then, the second photoresist film 18 is exposed and developed to form a second photoresist film 18 pattern exposing the conductive layer 17 on the upper side of the groove 16 (see FIG. 21). The conductive layer 17 exposed by the photosensitive film 18 pattern is etched to form a gate having the conductive layer 17 pattern. (See also section 2j).

Thereafter, the oxide film 14 and the thermal oxide film 13 exposed by the groove 16 are removed by an isotropic etching method to form a control hole 19 exposing the emitter 12. The second photoresist film 18 pattern is removed. (See also 2k).

As described above, the emitter array of the field emission device and the method of manufacturing the same according to the present invention form a transistor having a MOSFET structure in which the drain region for the draft is extended to the emitter region on one side of the semiconductor substrate, The semiconductor substrate of the drain is etched to form a conical emitter, but the drift region is quickly formed by the RTP method so that there is no other effect on the device, and after the formation of the transistor, a thick nitride film is formed to form a transistor. Since the channel width of the EDMOSFET is controlled so as to prevent excessive current from flowing, it acts as a current limiter and integrates a high voltage device together with an emitter array so that a driver LSI Regions and low voltage logic circuits can be disadvantageous to facilitate device formation It is advantageous to improve the yield over the process and reliability of device operation.

Claims (3)

A gate electrode formed on one side of the first conductive semiconductor substrate, a second conductive type contact region formed on the surface of the semiconductor substrate on one side of the gate electrode in contact with the gate electrode, and a lower and adjacent semi-structured substrate on the contact region. A source region of the first conductivity type formed in the first conductivity type, a low concentration impurity region of the second conductivity type formed in the semiconductor substrate on the other side of the gate electrode, and a drain of the second conductivity type formed on one side of the low concentration impurity region A field emission device comprising a RESURF EDMOSFET having a region, a field plate formed to overlap one side of the gate electrode, and a tip of an emitter array in which a surface of the semiconductor substrate of the drain region is etched to form a cone. Emitter array. A gate electrode is formed on one side of the first conductive semiconductor substrate, and a second conductive type contact region is formed on the surface of the semiconductor substrate on one side of the gate electrode and on the lower and adjacent semiconductor substrates. A source region of the first conductivity type, a low concentration impurity region of the second conductivity type formed in the semiconductor substrate on the other side of the gate electrode, a drain region of the second conductivity type formed on one side of the low concentration impurity region, and A process of forming a RESURF EDMOSFET having a field plate formed to overlap one side of the gate electrode, and an emitter of the field emission device including the tips of a conical emitter array by etching the surface of the semiconductor substrate in the drain region; Array. The method of claim 1, wherein the method of manufacturing an emitter array of a field emission device, characterized in that formed by the RTP method when forming the drain region.