JPH05341729A - Driving method for active matrix type thin film transistor liquid crystal panel - Google Patents

Abstract

PURPOSE:To provide a driving method for an active matrix type thin film transistor liquid crystal panel which attains low withstanding voltage for a switching driver of a drain bus line. CONSTITUTION:A counter electrodes is subdivided same as for gate bus lines 11, a circuit which switches VCOM voltage supplied to each counter electrode 15 is provided, and each counter electrode 15 is arranged facing with all picture element electrodes 14 connected to the corresponding gate bus lines 11 via a thin film transistor 13. Voltage data which varies synchronizing with writing timing of the corresponding gate bus lines 11 and includes polarity data, offset voltage of liquid crystal cells, and compensation voltage of effective voltage is supplied, also polarity of voltage data supplied to a drain bus line 12 is reversed so that picture element electrodes 14 connected to the adjacent gate bus lines 11 have different polarity each other, and voltage data of positive polarity and negative polarity are supplied as reversed information each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving an active matrix thin film transistor liquid crystal panel.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
Journal of Television Society Vol. 42, No. 1, P. 1
0-16 and P.I. 23-29. Conventionally, as a driving method of an active matrix type liquid crystal panel, especially a method using a thin film transistor (TFT-LCD), several different methods are used depending on the difference in the alternating current method, but the concept of the voltage supply method is the same. belongs to. Therefore, as a typical example, a driving method in which alternating current is performed at each scanning cycle (hereinafter referred to as frame mode)
Will be described.

FIG. 9 is a block diagram of such a conventional active matrix type thin film transistor liquid crystal panel, and FIG. 10 is a drive timing chart of the active matrix type thin film transistor liquid crystal panel. As shown in the figure, in an active matrix type thin film transistor liquid crystal panel, a gate bus line 51 and a drain bus line 52 are generally arranged orthogonally on a rear substrate, and a thin film transistor (TF) as a switching element corresponding to each pixel electrode is provided at an intersection thereof.
A transparent counter electrode 5 is provided on the front substrate by providing 53).
4 is provided, an alignment film that has been subjected to an alignment treatment in an appropriate direction is provided on the surfaces of both substrates, and the alignment films of both substrates are opposed to each other with a liquid crystal layer in between and bonded to each other, and on the back surfaces of the front substrate and the back substrate, Polarizing films are attached so that their polarization axes are parallel or perpendicular to each other, and due to the potential difference between the voltage of the pixel electrode and the voltage of the counter electrode supplied via the TFT 53,
The liquid crystal 55 in the portion sandwiched by both electrodes is switched.

A scanning circuit 60 is connected to the gate bus line 51 and a data circuit 70 is connected to the drain bus line 52 as switching means of the TFT 53, and the scanning circuit 60 is used as a gate selection signal of the TFT 53.
ON voltage V _{G (+)} and OFF voltage V _{G (-)} from TFT 53
The positive polarity write voltage V _{D (+)} and the negative polarity write voltage V _{D (-)} are supplied from the data circuit 70 as the drain selection and luminance data signals.

Further, as shown in FIG. 10, the voltage V _S of the pixel electrode written by the TFT 53 causes a voltage fluctuation twice in the voltage holding state. First, TFT
When the gate selection signal of 53 changes from the ON state to the OFF state, the voltage V _{S of the} pixel electrode connected to the TFT 53 to which the selection signal is supplied changes by ΔV ₁ due to the parasitic capacitance C _gS of the TFT. ..

Secondly, when the data signal changes to the polarity opposite to the polarity at the time of writing, it changes by ΔV ₂ due to the electric field effect between the pixel electrode and the drain bus line 52.
For this reason, the potential difference between the pixel electrode and the counter electrode is made uniform with respect to the variation of the voltage V _S of the pixel electrode with respect to the counter electrode during writing of positive polarity and during writing of negative polarity. The voltage V _COM is supplied.

FIG. 11 shows the electro-optical characteristics of a TN liquid crystal cell in the case where two polarizing films are attached so that their polarization axes are parallel to each other. The TN liquid crystal cell used in the active matrix thin film transistor liquid crystal panel has a threshold voltage V _{TH at} which the light transmittance sharply increases with respect to the potential difference between the pixel electrode and the counter electrode, and a saturation at which the fluctuation of the light transmittance decreases. In the voltage range ΔV in which the voltage V _SAT is present and V _{TH to} V _SAT , the voltage fluctuation shows the change of the light transmittance. Therefore, in order to achieve a complete ON state, V _SAT <V _S −V _{COM in} the positive polarity and V _SAT <V in the negative polarity.
_To set a voltage condition of _COM- V _S and achieve a complete OFF state, a voltage condition of V _TH > V _S −V _{COM in} the positive polarity and a voltage condition of V _TH > V _COM −V _{S in} the negative polarity. By setting, the liquid crystal cell can be switched.

[0008]

However, in the driving method of the active matrix type liquid crystal panel described above, the time from the writing of the data signal to the pixel electrode to the reversal of the voltage polarity of the drain bus line is different. In this case, for example, comparing the first gate bus line selected by the scanning circuit and the voltage V _{S of the} pixel electrode connected to the Nth gate bus line via the TFT, respectively, the pixel electrode and the drain bus line are compared. Due to the electric field effect between the _two , the period in which the voltage changes by ΔV ₂ is different, so that the average effective voltage applied to the liquid crystal layer in each scanning cycle is different, and the light transmittance is different.

For the switching of the liquid crystal layer, it is sufficient to generate a voltage fluctuation of ΔV between the pixel electrode and the counter electrode, but the voltage of the counter electrode is fixed and the voltage of the pixel electrode is positive. In order to change to a negative polarity, the driver of the drain bus line requires a switching voltage of V _SAT × 2 [corresponding to (V _TH + ΔV) × 2], and ΔV + V _TH ×
An extra switching voltage is required for the voltage of 2,
This has been an obstacle to lowering the withstand voltage of the driver.

The present invention reduces the above-mentioned variation in the average effective voltage applied to the liquid crystal layer for each scanning period by changing the AC method and reduces the extra switching voltage V _TH × 2 + ΔV applied to the drain bus line. In order to eliminate it, the counter electrodes are divided into the same number as the gate bus lines, and each counter electrode is arranged to face the pixel electrode group connected to the corresponding gate bus line via the TFT. By switching in synchronization with the selection cycle of each gate bus line, binary voltages of equal voltage levels are alternately supplied to all counter electrodes, and positive and negative polarities are supplied to the drain bus line. the data structure in which data is supplied as information which is inverted from each other, the variation of the V _COM voltage, the switching driver drain bus line low And to provide an excellent method of driving an active matrix type thin film transistor liquid crystal panel to achieve voltage.

[0011]

In order to achieve the above object, the present invention provides a gate bus line and a drain bus line which are arranged orthogonally on a back substrate, and which is provided at an intersection of the gate bus line and the drain bus line. A thin film transistor is provided corresponding to each pixel electrode, a transparent counter electrode is provided on the front substrate, alignment films that have been subjected to an alignment treatment in appropriate directions are provided on the surfaces of the back substrate and the front substrate, and the alignment films of both substrates are arranged together. ,
In a method for driving an active matrix type thin film transistor liquid crystal panel in which the opposite electrodes are arranged and bonded via a liquid crystal layer, and a polarizing film is adhered to the back surfaces of the back substrate and the front substrate, the counter electrodes are divided into the same number as the gate bus lines. , The counter electrode is arranged so as to face all the pixel electrodes connected to the corresponding gate bus line via the thin film transistor, and the voltage is changed in each counter electrode in synchronization with the write timing of the gate bus line corresponding to the counter electrode. A switching element is provided for each of the drain bus lines, and the voltage data supplied to each drain bus line is data in which the pixel electrodes connected to the adjacent gate bus lines have polarities different from each other, and the positive and negative voltage data are The voltage data that is supplied as voltages that are inverted from each other and that is supplied to each counter electrode Data, and supplies the offset voltage corresponding to the threshold voltage of the liquid crystal, in which so as to operate by supplying a selection signal to each gate bus line.

[0012]

According to the present invention, as described above, in the method of driving an active matrix type thin film transistor liquid crystal panel, the counter electrodes are divided into the same number as the gate bus lines,
A circuit for switching the V _COM voltage supplied to each counter electrode is provided, and each counter electrode is arranged to face each pixel electrode connected to the corresponding gate bus line via the thin film transistor. The voltage data, which fluctuates in synchronism with the write timing, is supplied as the voltage data including the polarity data, the offset voltage of the liquid crystal cell and the effective voltage correction voltage, and the voltage data supplied to the drain bus line is connected to the adjacent gate bus line. The polarity is inverted so that the pixel electrodes having different polarities are different from each other, and the positive polarity and negative polarity voltage data are supplied as mutually inverted information.

Therefore, it is possible to make the average applied voltage of the liquid crystal cell uniform and to reduce the withstand voltage of the switching driver of the gate bus line and the drain bus line. Further, this driving method can obtain the same effect even when an analog voltage is input to the drain bus line, and thus can be sufficiently applied to the gradation driving of the active matrix thin film transistor liquid crystal panel.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a schematic perspective view of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention. As shown in this figure, a gate bus line 11 and a drain bus line 12 are formed on a transparent rear substrate.
And are orthogonally arranged, and a thin film transistor (T
FT) 13 is provided, connected to the transparent pixel electrode 14 corresponding to an individual display cell, and an alignment film that has been subjected to an alignment treatment in an appropriate direction is provided.

On the other hand, transparent counter electrodes 15 are provided on the transparent front substrate, the transparent counter electrodes 15 being divided into the same number as the gate bus lines 11.
An alignment film that has been subjected to an alignment treatment in an appropriate direction is provided, the alignment films of both substrates are made to face each other, and each counter electrode faces all the pixel electrodes 14 connected to the corresponding gate bus line 11 via the TFT 13, In addition, it is aligned so as not to face the pixel electrodes 14 other than the pixel electrode 14, an appropriate gap is provided between both substrates, liquid crystal is injected and sealed, and the polarization axes of the two are aligned on the exposed surfaces of both substrates. A polarizing film is attached so as to be parallel or vertical. Reference numeral 15a indicates a portion facing the pixel electrode 14.

FIG. 2 is a schematic configuration diagram of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention,
3 is a schematic block diagram of a data circuit showing an embodiment of the present invention, FIG. 4 is a waveform diagram of voltage data supplied to a drain bus line showing an embodiment of the present invention, and FIG. 5 is an embodiment of the present invention. 6 is a schematic block diagram of the common variation circuit, and FIG. 6 is a timing chart of the common variation circuit showing an embodiment of the present invention.

As shown in these figures, the scanning circuit 20 is connected to the gate bus line 11, and the ON voltage is sequentially supplied from the first gate bus line in a time-sequential manner.
5 is connected to a common variable circuit 40 including a shift register section 41, a voltage amplification section 42, and a driver section 43,
All the pixel electrodes 14 (see FIG. 1) electrically connected to the individual counter electrodes 15 via the liquid crystal layer change in synchronization with the rising of the ON voltage application to the gate bus line 11 connected via the TFT 13. Then, individual voltage data V _COM1 ′, V _COM2 ′ ... V _COMf ′ including the polarity data and the offset voltage of the liquid crystal cell when each gate bus is selected is supplied to the corresponding counter electrode 15, and the drain bus 12 is provided with a data generator. Three
1. A data circuit 30 including a data inversion unit 32 and a data output unit 33 is connected, and image data 1 output from a data generation unit 31 in the data circuit 30 is output by the data inversion unit 32 to each gate bus line. In addition, the data 2 is created by operating with the alternating signal which alternately inverts to the same gate bus 11 with different polarity data for each writing cycle, and the data output unit 33 outputs positive polarity to each drain bus 12. The negative voltage data is supplied as information that is inverted from each other.

Further, in this case, as shown in FIG.
The voltage data of each drain bus 12 output from the data circuit 30 is ON voltage V _{D (+)} ′, OF in the positive polarity.
The F voltage V _{D (- )} 'is output as the ON voltage V _{D (-)} ' and the OFF voltage V _{D (+)} 'in the negative polarity. The voltage amplitude ΔV _D is set to be equal to ΔV shown in FIG. 11, and ΔV _D = V _{D (+)} ′ ₋ V _{D (−)} ′ = V _SAT −
Since it is given under the condition of V _TH = ΔV, the amplitude of the drain voltage is reduced by V _TH × 2 + ΔV as compared with the conventional example of FIG. Similarly, the amplitude of the gate voltage can be reduced to the same extent as the amplitude of the drain voltage is reduced.

On the other hand, the voltage data of each counter electrode output from the common variation circuit 40 is constructed as follows.
It changes immediately before the ON voltage of the first gate bus is applied, and
A signal D having write polarity data when the gate bus is selected
F and a clock signal φ _C which is synchronized with the rising of the ON voltage application to the gate bus and has a period of t _on time are supplied to the shift register unit, and output waveforms D ₁ and D ₂ delayed by one clock. , _Df is created, and this is supplied to the voltage amplification section, and R _{2 is set} by the operational amplifier and the resistors R ₁ and R _2.
/ R ₁ times reverse amplification is performed to create a voltage signal having a predetermined voltage amplitude including the offset voltage and the polarity correction voltage when the gate bus is selected, and V _COM1 ′ is _supplied via the protection resistor R ₃ and the driver unit. To the counter electrode corresponding to the first gate bus, V
_COM2 'to the counter electrode corresponding to the second gate bus,
V _COMf 'is supplied to the counter electrodes corresponding to the final gate bus, respectively.

Further, V _COM1 ′ output here,
Since V _COM2 ′ ... V _COMf ′ have the same voltage amplitude,
A drain driver for multiple driving can also be used. FIG. 7 is an equivalent circuit diagram of a liquid crystal cell showing an embodiment of the present invention, and FIG. 8 is a diagram showing drive timing of an active matrix thin film transistor liquid crystal panel showing the embodiment of the present invention.

In FIG. 8, T represents a write cycle in each gate bus line 11, t _on represents an ON voltage application time in each gate bus, and T and t _on in all gate bus lines have the same length. It is determined. Further, the potential fluctuation of the pixel electrode in the charge holding state of the liquid crystal cell is ΔV ₁ ′ = [C _gs / (C _gs + C _LC )] due to the parasitic capacitance C _gs of the TFT at the time of switching the corresponding TFT.
_{× (V G (+) '} -V G (-)') and the capacity between the two drain bus and the pixel electrodes sandwiching the pixel electrode when the voltage of the drain bus during write is varied by [Delta] V _D ' Due to C _DP1 and C _DP2 , there exists ΔV ₂ ′ = [(C _DP1 + C _DP2 ) / C _LC ] × ΔV _D ′.

[0022] 'be formed equivalent TFT in every pixel electrode, regardless of the position of the write voltage and the panel, for the same polarity, a variation of the same potential, [Delta] V _1' potential variation [Delta] V ₁ min By shifting only and determining the potential of the counter electrode, the same voltage can be held between all the pixel electrodes and the counter electrode. However, the potential fluctuation Δ
V ₂ ′ is generated during the period in which the potentials of the two drain buses sandwiching the pixel electrode fluctuate from the potential at the time of writing, so that the variation period is short and long, and the pixel electrode and the counter electrode The average effective voltage between the two changes, which causes uneven brightness depending on the position in the panel.

In the present embodiment, since the polarity of the drain bus line is inverted line by line, if the number of scanning lines is N and T = N × t _on , all the gate bus lines 11 in FIG. In the drive waveform, a period ΔV ₂ ′ of T × (N / 2) occurs, and the average effective voltage is ΔV ₂ ′ × [(N
/ 2) / (N-1)], but the average effective voltage between all the pixel electrodes and the counter electrode becomes uniform.

The voltage waveforms supplied to V _COM1 ′, V _COM2 ′ ... V _COMf ′ are ΔV ₁ ′, ΔV ₂ ′, polarity and V
_{When TH} is considered positive, V _{D (+)} '-ΔV-V _TH -Δ
V ₁ ′ −ΔV ₂ ′ × [(N / 2) / (N−1)] has a negative polarity, V _{D (−)} ′ + ΔV + V _TH −ΔV ₁ ′ + Δ
V ₂ ′ × [(N / 2) / (N-1)], Δ
A voltage signal having a fluctuation amplitude of V + 2V _TH + ΔV ₂ ′ × [N / (N−1)] and an effective voltage correction voltage ΔV ₂ ′ × [N
/ (N-1)] is added to the voltage amplitude to hold the average applied voltage ΔV + V _TH in all pixels. Therefore, even if the amplitude of the voltage data output from the data circuit is reduced by V _TH × 2 + ΔV, a uniform and sufficient applied voltage can be supplied to the liquid crystal cell.

The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the present invention, and these modifications are not excluded from the scope of the present invention.

[0026]

As described above in detail, according to the present invention, the counter electrode is divided in the same manner as the gate bus line,
A circuit for switching the V _COM voltage supplied to each counter electrode is provided, and each counter electrode is arranged to face each pixel electrode connected to the corresponding gate bus line via the TFT, and the corresponding gate bus line is provided. The voltage data that fluctuates in synchronization with the write timing and is supplied as voltage data including polarity data, liquid crystal cell offset voltage and effective voltage correction voltage, and that is supplied to the drain bus line is connected to the adjacent gate bus line. By reversing the polarities so that the pixel electrodes have different polarities from each other and supplying the voltage data of the positive polarity and the voltage of the negative polarity as mutually inverted information, the average applied voltage of the liquid crystal cells is made uniform and the gate bus is made uniform. It is possible to reduce the withstand voltage of the switching driver for the line and the drain bus line.

Further, this driving method can obtain the same effect even when an analog voltage is input to the drain bus line, and is therefore sufficiently applicable to gradation driving of an active matrix type thin film transistor liquid crystal panel. Further, in this driving method, since the voltage variation of the counter electrode does not occur during the charge retention period of each display cell, the variation of the pixel electrode caused by this voltage variation ΔV ₃ = C _gs × [(R ₂ /
It is an ideal low voltage drive without R ₁ ) × V _in ] / (C _gs + C _LC ).

[Brief description of drawings]

FIG. 1 is a schematic perspective view of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of an active matrix thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 3 is a schematic block diagram of a data circuit showing an embodiment of the present invention.

FIG. 4 is a waveform diagram of voltage data supplied to the drain bus line according to the embodiment of the present invention.

FIG. 5 shows a schematic block diagram of a common fluctuation circuit showing an embodiment of the present invention.

FIG. 6 is a diagram showing a timing chart of a common variation circuit showing an embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram of a liquid crystal cell showing an example of the present invention.

FIG. 8 is a diagram showing drive timing of an active matrix type thin film transistor liquid crystal panel showing an embodiment of the present invention.

FIG. 9 is a configuration diagram of a conventional active matrix thin film transistor liquid crystal panel.

FIG. 10 is a diagram showing a drive timing chart of a conventional active matrix thin film transistor liquid crystal panel.

FIG. 11 is an electrical diagram of a TN liquid crystal cell in the case where two conventional polarizing films are attached so that their polarization axes are parallel to each other.
It is a figure which shows an optical characteristic.

[Explanation of symbols]

 11 Gate Bus Line 12 Drain Bus Line 13 Thin Film Transistor (TFT) 14 Pixel Electrode 15 Counter Electrode 20 Scanning Circuit 30 Data Circuit 31 Data Generation Section 32 Data Inversion Section 33 Data Output Section 40 Common Fluctuation Circuit 41 Shift Register Section 42 Voltage Amplification Section 43 Driver

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Hiroshi Hamano 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (2)

[Claims] 1. A gate bus line and a drain bus line are arranged orthogonally on a rear substrate, and a thin film transistor is provided at an intersection of the gate bus line and the drain bus line corresponding to each pixel electrode. An opposing electrode is provided, and an alignment film that has been subjected to an alignment treatment in an appropriate direction is provided on the surfaces of the back substrate and the front substrate.
In a method for driving an active matrix type thin film transistor liquid crystal panel, which is arranged so as to be opposed to each other via a liquid crystal layer and is adhered, and a polarizing film is adhered to the back surfaces of the back substrate and the front substrate, the counter electrodes are divided into the same number as the gate bus lines. Then, the counter electrodes are arranged to face all the pixel electrodes connected to the corresponding gate bus lines via the thin film transistors,
Each counter electrode is provided with a switching element for changing the voltage in synchronization with the write timing of the gate bus line corresponding to the counter electrode, and the voltage data supplied to each drain bus line is connected to the adjacent gate bus line. Data in which the pixel electrodes have polarities different from each other and positive and negative voltage data are supplied as voltages inverted from each other, and the polarity data and the threshold voltage of the liquid crystal are included in the voltage data supplied to each counter electrode. A method for driving an active matrix thin film transistor liquid crystal panel, which comprises operating by supplying an offset voltage corresponding to the above, and supplying a selection signal to each gate bus line. 2. The active component according to claim 1, wherein an average fluctuating voltage of a pixel electrode, which fluctuates due to polarity inversion of voltage data supplied to the drain bus line, is supplied to a corresponding counter electrode as a correction voltage. Matrix type thin film transistor liquid crystal panel driving method.