JPH053388A - Manufacture of multilayer printed board and insulating layer for multilayer printed board - Google Patents

Manufacture of multilayer printed board and insulating layer for multilayer printed board

Info

Publication number
JPH053388A
JPH053388A JP15312291A JP15312291A JPH053388A JP H053388 A JPH053388 A JP H053388A JP 15312291 A JP15312291 A JP 15312291A JP 15312291 A JP15312291 A JP 15312291A JP H053388 A JPH053388 A JP H053388A
Authority
JP
Japan
Prior art keywords
layer
insulating layer
multilayer printed
filler component
printed board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP15312291A
Other languages
Japanese (ja)
Inventor
Koji Soegawa
公司 添川
Shigeo Nakamura
繁雄 中村
Kazumi Kobayashi
和美 小林
Hitoshi Yuyama
仁志 湯山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15312291A priority Critical patent/JPH053388A/en
Publication of JPH053388A publication Critical patent/JPH053388A/en
Withdrawn legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To secure required insulation and elevate the close adhesion with the electroless plated layer on the surface side, concerning the manufacture of an insulating layer for a multilayer printed board and the multilayer printed board. CONSTITUTION:In an insulating layer for a multilayer printed board, wherein a resin material 3a which has photosetting property and insulating property and filler ingredients 3b to stabilize this are mixed, the density of the filler ingredients 3b is made high on the surface side and low on the inner face side. Moreover, in the manufacture of a piling type of multilayer, it is so constituted as to form an insulating layer for a multilayer printed board in an insulating layer formation process.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、主として積み上げ方式
で作られる多層プリント基板の製造方法と該多層プリン
ト基板に適用される絶縁層に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multi-layer printed circuit board which is mainly manufactured by a stacking method and an insulating layer applied to the multi-layer printed circuit board.

【0002】[0002]

【従来の技術】従来、多層プリント基板では、絶縁層で
隔てられた導体層どうしがスルーホールのメッキ層やビ
アホールに充填した導体によって接続されている。
2. Description of the Related Art Conventionally, in a multilayer printed circuit board, conductor layers separated by an insulating layer are connected to each other by a plated layer of a through hole or a conductor filled in a via hole.

【0003】しかしながら、この場合にはスルーホール
やビアホールがドリルを用いるいわゆる孔開け加工によ
り形成されているため、これらの径を小径化する上で大
きな限界があり、従って、これらスルーホールやビアホ
ールよりも大きく形成する必要があるランドの径を0.
3〜0.5mmよりも小径にすることには一層大きな限界
がある。
However, in this case, since the through holes and the via holes are formed by so-called drilling using a drill, there is a large limit in reducing the diameter of these holes. The diameter of the land that needs to be formed large is 0.
There is an even greater limit to making the diameter smaller than 3 to 0.5 mm.

【0004】これらの限界を突破するため、現在、積み
上げ方式で多層プリント基板を形成することが試みられ
ている。積み上げ方式では、例えば図4に示すように、
絶縁材101の表面に導体層をプリントし、所定のパタ
ーンにエッチングして導体パターン102を形成する第
1層形成工程(a)、絶縁材101及び導体パターン1
02の表面に感光性絶縁層103を形成する絶縁層形成
工程(b)、絶縁層103の所要の部分を露光させて硬
化させ、非硬化部分を除去して絶縁層103を貫通する
穴104を形成する焼付・現像工程(c)、絶縁層10
3の表面をブラシで研磨したり、あるいは絶縁層103
に炭酸カルシウム等のフィラーが混入されている場合に
は酸で表面のフィラー成分を除去する等の粗荒化する表
面処理工程(d)、絶縁層103の表面に無電解メッキ
により表面側の無電解メッキ層105を形成する無電解
メッキ工程(e)、無電解メッキ層105の表面に電解
メッキ層を付着させて所要の厚さのメッキ層106に成
長させる電解メッキ工程(f)、メッキ層106をエッ
チングして表面側の導体パターン107を形成する第2
層形成工程(g)を経て第1層の導体パターン102と
第2層の導体パターン107とが穴104内のメッキ層
106を介して接続される。第3層以上の導体パターン
を形成する場合には、1層積み上げるごとに、更に、絶
縁層形成工程(b)から第2層形成工程(f)までの手
順が繰り返される。
In order to break through these limits, it is currently attempted to form a multilayer printed circuit board by a stacking method. In the stacking method, for example, as shown in FIG.
First layer forming step (a) of forming a conductor pattern 102 by printing a conductor layer on the surface of the insulator 101 and etching the conductor pattern into a predetermined pattern, the insulator 101 and the conductor pattern 1.
Insulating layer forming step (b) of forming the photosensitive insulating layer 103 on the surface of 02, exposing and curing a required portion of the insulating layer 103, removing the uncured portion, and forming a hole 104 through the insulating layer 103. Forming baking / developing step (c), insulating layer 10
The surface of 3 is polished with a brush, or the insulating layer 103
When a filler such as calcium carbonate is mixed in the surface, the surface treatment step (d) of roughening by removing the filler component on the surface with an acid, and the surface of the insulating layer 103 by electroless plating Electroless plating step (e) for forming the electrolytic plating layer 105, electrolytic plating step (f) for depositing an electrolytic plating layer on the surface of the electroless plating layer 105 and growing it to a plating layer 106 of a required thickness, plating layer Second etching of 106 to form the conductor pattern 107 on the front surface side
After the layer forming step (g), the first-layer conductor pattern 102 and the second-layer conductor pattern 107 are connected via the plated layer 106 in the hole 104. When forming a conductor pattern of a third layer or more, the procedure from the insulating layer forming step (b) to the second layer forming step (f) is repeated every time one layer is stacked.

【0005】上記焼付・現像工程(c)においては直径
0.15〜0.25mm程度の微細な穴104を形成でき
るので、導体パターン102,107のランドの径は
0.2mm程度まで小径化することができ、回路密度を著
しく高めることができる。
In the printing / developing step (c), since the fine holes 104 having a diameter of about 0.15 to 0.25 mm can be formed, the diameter of the lands of the conductor patterns 102 and 107 can be reduced to about 0.2 mm. Therefore, the circuit density can be significantly increased.

【0006】[0006]

【発明が解決しようとする課題】ところで、上記表面処
理工程(d)において、研磨によって絶縁層103の表
面を粗荒化する場合には、図5に示すように、絶縁層1
03の表面にV字形の傷103fが付けられる。このよ
うな傷103fを付けた絶縁層103の表面に無電解メ
ッキ層105を付着させた場合、後に例えば部品実装時
等に加熱された時に導体パターン107が絶縁層103
から剥離し易く、製品に対する信頼性が損なわれるおそ
れがある。
In the surface treatment step (d), when the surface of the insulating layer 103 is roughened by polishing, as shown in FIG.
A V-shaped scratch 103f is attached to the surface of 03. When the electroless plating layer 105 is adhered to the surface of the insulating layer 103 having such a scratch 103f, the conductor pattern 107 is applied to the insulating layer 103 when heated later, for example, when mounting components.
The product may be easily peeled off, and the reliability of the product may be impaired.

【0007】上記表面処理工程(d)において、絶縁層
103に混入してある表面のフィラー成分をクロム酸、
塩酸等の酸性処理液で溶出して除去する場合には、フィ
ラー成分が除去された後に図6に示すように、V字形の
穴103cの他に、入口よりも内部が拡大された穴10
3d、入口から斜めに凹入する穴103e等が洞設され
ることがある。このように内部が拡大された穴103d
や入口から斜めに凹入する穴103e等の複雑な形状の
穴を有する絶縁層103の表面に無電解メッキ層105
を付着させる場合には、無電解メッキ層105がその複
雑な形状の穴の中に入ることにより、剥離され難くなる
ので、研磨した場合よりは絶縁層103と無電解メッキ
層105との密着性が高められる。
In the surface treatment step (d), the filler component on the surface mixed in the insulating layer 103 is chromic acid,
In the case of elution and removal with an acidic treatment liquid such as hydrochloric acid, after the filler component is removed, as shown in FIG. 6, in addition to the V-shaped hole 103c, the hole 10 whose inside is larger than the inlet 10 is formed.
3d, a hole 103e or the like that is obliquely recessed from the entrance may be provided in a cave. The hole 103d whose inside is enlarged in this way
Or an electroless plating layer 105 on the surface of the insulating layer 103 having a hole having a complicated shape such as a hole 103e obliquely recessed from the entrance.
In the case of adhering, since the electroless plating layer 105 enters into the hole of the complicated shape and is less likely to be peeled off, the adhesiveness between the insulating layer 103 and the electroless plating layer 105 is higher than that in the case of polishing. Is increased.

【0008】しかしながら、一般に、絶縁層103の絶
縁性を確保するため、フィラー成分密度が低く抑えられ
ているので、穴103c〜103eの分布密度が低くな
り、絶縁層103とむ電解メッキ層105との接合強度
が例えば0.5〜1.0kgf/cm程度であり、実用上不満
が感じられる。
However, in general, in order to ensure the insulating property of the insulating layer 103, the density of the filler component is kept low, so that the distribution density of the holes 103c to 103e becomes low and the density of the insulating layer 103 and the electrolytic plating layer 105 is reduced. The bonding strength is, for example, about 0.5 to 1.0 kgf / cm, and it is practically unsatisfactory.

【0009】本発明は、上記の事情を鑑みてなされたも
のであり、所要の絶縁性を確保することができ、しか
も、表面側の無電解メッキ層との密着性を高められるよ
うにした多層プリント基板の製造方法及び多層プリント
基板用絶縁層を提供することを目的とする。
The present invention has been made in view of the above circumstances, and is a multi-layer structure capable of ensuring a required insulating property and enhancing the adhesion with the electroless plating layer on the surface side. An object of the present invention is to provide a method for manufacturing a printed board and an insulating layer for a multilayer printed board.

【0010】[0010]

【課題を解決するための手段】上記目的を達成するため
にこの発明は、図1に示すように、導体パターン2を形
成した絶縁材1上に、フィラー成分3bを含有した感光
硬化性の樹脂材料3aを露光して形成した絶縁層3と、
該絶縁層3の表面に該表面のフィラー成分3bを除去し
た後に形成した導体パターン7とを順次積み上げる積み
上げ方式の多層プリント基板の製造方法において、上記
絶縁層3として、フィラー成分3bの密度の低い内面層
32を形成した後、フィラー成分3bの密度が内面層3
2より高い表面層31を形成するようにしている。上記
絶縁層3の内面層32及び表面層31はドライフィルム
または液状樹脂を乾燥させて形成することができる。ま
た、上記フィラー成分3bの除去はクロム酸等の酸性溶
液を用いて化学的に行うことができる。
In order to achieve the above object, the present invention is, as shown in FIG. 1, a photosensitive curable resin containing a filler component 3b on an insulating material 1 on which a conductor pattern 2 is formed. An insulating layer 3 formed by exposing the material 3a to light;
In the method of manufacturing a multi-layer printed circuit board of a stacking type in which a conductor pattern 7 formed after removing the filler component 3b on the surface of the insulating layer 3 is sequentially stacked, the insulating layer 3 has a low density of the filler component 3b. After forming the inner surface layer 32, the density of the filler component 3b is reduced to the inner surface layer 3
The surface layer 31 higher than 2 is formed. The inner surface layer 32 and the surface layer 31 of the insulating layer 3 can be formed by drying a dry film or a liquid resin. Moreover, the removal of the filler component 3b can be performed chemically using an acidic solution such as chromic acid.

【0011】[0011]

【作用】本発明においては、フィラー成分3bの低い内
面側の部分で所要の絶縁性が確保される。しかも、表面
側ではフィラー成分3bの密度が高いので、表面に露出
したフィラー成分3bを除去すると、絶縁層3の表面に
入口よりも内部の拡大された穴、入口から斜めに凹入す
る穴等の複雑な形状の穴が高密度に分布することにな
り、この表面に付着される無電解メッキ層との接合強度
が高められる。
In the present invention, the required insulating property is ensured in the portion on the inner surface side where the filler component 3b is low. Moreover, since the density of the filler component 3b is high on the surface side, if the filler component 3b exposed on the surface is removed, the surface of the insulating layer 3 has an enlarged hole inside than the inlet, a hole obliquely recessed from the inlet, etc. The holes having a complicated shape are distributed at high density, and the bonding strength with the electroless plating layer attached to this surface is enhanced.

【0012】[0012]

【実施例】以下、本発明の実施例を図面に基づき具体的
に説明する。次に本発明の一実施例に係る多層プリント
基板の製造方法について図1に基づき説明する。
Embodiments of the present invention will be specifically described below with reference to the drawings. Next, a method for manufacturing a multilayer printed board according to an embodiment of the present invention will be described with reference to FIG.

【0013】この多層プリント基板の製造方法は、絶縁
層3として上記本発明の一実施例に係る絶縁層3を使用
することを除けば従来の積み上げ方式の多層プリント基
板の製造方法と同様である。即ち、例えば図1に示すよ
うに、絶縁材1の表面に導体層をプリントし、所定のパ
ターンにエッチングして導体パターン2を形成する第1
層形成工程(a)、絶縁材1及び導体パターン2の表面
に上記絶縁層3を積層して形成する絶縁層形成工程
(b)、絶縁層3の所要の部分を露光させて硬化させ、
非硬化部分を除去して絶縁層3を貫通する穴4を形成す
る焼付・現像工程(c)、絶縁層3の表面のフィラー成
分3bを除去して絶縁層3の表面を粗荒化する表面処理
工程(d)、絶縁層3の表面に無電解メッキにより表面
側の無電解銅メッキ層5を形成する無電解メッキ工程
(e)、無電解銅メッキ層5の表面に電解銅メッキ層を
付着させて所要の厚さの銅メッキ層6に成長させる電解
メッキ工程(f)、銅メッキ層6をエッチングして表面
側の導体パターン7を形成する第2層形成工程(g)を
経て第1層の導体パターン2と第2層の導体パターン7
とが積層され、穴4内の銅メッキ層6を介して接続され
る。
The method of manufacturing the multilayer printed circuit board is the same as the conventional method of manufacturing the multilayer printed circuit board of the stacking type except that the insulating layer 3 according to the embodiment of the present invention is used as the insulating layer 3. . That is, for example, as shown in FIG. 1, a conductor layer is printed on the surface of an insulating material 1 and etched into a predetermined pattern to form a conductor pattern 2.
A layer forming step (a), an insulating layer forming step (b) in which the insulating layer 3 is laminated on the surfaces of the insulating material 1 and the conductor pattern 2, and a desired portion of the insulating layer 3 is exposed and cured,
A baking / developing step (c) of removing the uncured portion to form a hole 4 penetrating the insulating layer 3, a surface of the insulating layer 3 roughening the surface of the insulating layer 3 by removing the filler component 3b. Treatment step (d), electroless plating step (e) of forming the electroless copper plating layer 5 on the surface side by electroless plating on the surface of the insulating layer 3, and electrolytic copper plating layer on the surface of the electroless copper plating layer 5. After the electrolytic plating step (f) of adhering and growing the copper plating layer 6 of a required thickness, the second layer forming step (g) of etching the copper plating layer 6 to form the conductor pattern 7 on the front side, One-layer conductor pattern 2 and second-layer conductor pattern 7
And are laminated and connected via the copper plating layer 6 in the hole 4.

【0014】第3層以上の導体パターンを形成する場合
には、1層積み上げるごとに、絶縁層形成工程(b)か
ら第2層形成工程(f)までの手順が繰り返される。上
記において、絶縁層3は、図1あるいは図2に拡大して
示すように感光硬化性及び絶縁性を有する樹脂材料3a
にこれを安定化させるフィラー成分3bを高密度に混合
した表面層31と、感光硬化性及び絶縁性を有する樹脂
材料3aにフィラー成分3bを低密度に混合した内面層
32とを積層したドライフィルムで構成される。
When forming a conductor pattern of a third layer or more, the procedure from the insulating layer forming step (b) to the second layer forming step (f) is repeated every time one layer is stacked. In the above, the insulating layer 3 is made of a resin material 3a having a photo-curing property and an insulating property as shown in an enlarged view in FIG. 1 or 2.
In addition, a dry film in which a surface layer 31 in which a filler component 3b for stabilizing the same is mixed at a high density and an inner surface layer 32 in which a filler component 3b is mixed at a low density in a resin material 3a having photocurability and insulation are laminated. Composed of.

【0015】上記内面層32の厚さは、要求される絶縁
性と、フィラー成分3bの配合率によって適宜設定され
る。また、表面層31の厚さは表面処理時に残留する程
度以上に設定してあればよい。
The thickness of the inner surface layer 32 is appropriately set depending on the required insulating property and the blending ratio of the filler component 3b. In addition, the thickness of the surface layer 31 may be set to a level that allows the surface layer 31 to remain during the surface treatment.

【0016】上記表面処理工程(d)においては、クロ
ム酸、塩酸等の酸性処理液に平均粒径が0.7μmの炭
酸マグネシウム又は炭酸カルシウムからなるフィラー成
分3bを溶解させて除去し、図3に詳細に示すように、
絶縁層3の表面にU字形ないしV字形に入口が開いた穴
3c、入口よりも内側が拡大している穴3d、入口から
斜めに凹入した穴3e等が形成される。
In the surface treatment step (d), the filler component 3b made of magnesium carbonate or calcium carbonate having an average particle diameter of 0.7 μm is dissolved and removed in an acidic treatment liquid such as chromic acid or hydrochloric acid, and then removed as shown in FIG. As shown in detail in
On the surface of the insulating layer 3, there are formed a U-shaped or V-shaped hole 3c having an opening, a hole 3d having an inner side larger than the entrance, and a hole 3e obliquely recessed from the entrance.

【0017】ここで、表面層31にはフィラー成分3b
が高密度に混合されているので、その表面にこれらの穴
3c〜3e、特に、入口よりも内側が拡大している穴3
d、入口から斜めに凹入した穴3e等が高密度に分布す
ることになる。従って、この後の無電解メッキ工程
(e)では、無電解銅メッキ層5がこの入口よりも内側
が拡大している穴3dや入口から斜めに凹入した穴3e
の中に入り込んで強固に接合され、この上に電解メッキ
工程(f)で形成された銅メッキ層6は例えば1.0〜
2.0kgf/cm程度以上の接合強度で強固に接合される。
この接合強度は表面層31のフィラー成分密度の増減に
対応して増減するので、表面層31のフィラー成分密度
を調整することにより、実用上必要とされる1.5kgf/
cm程度以上の接合強度を安定して得ることができる。
Here, the surface layer 31 contains the filler component 3b.
Are densely mixed with each other, so that the holes 3c to 3e are formed on the surface of the holes 3c to 3e, and in particular, the hole 3 whose inside is larger than the inlet 3a.
d, the holes 3e and the like that are obliquely recessed from the inlet are distributed at high density. Therefore, in the subsequent electroless plating step (e), the electroless copper-plated layer 5 has a hole 3d in which the inside is enlarged from the inlet or a hole 3e obliquely recessed from the inlet.
The copper plating layer 6 formed in the electrolytic plating step (f) is 1.0 to
It is firmly joined with a joining strength of about 2.0 kgf / cm or more.
Since this bonding strength increases / decreases in accordance with the increase / decrease in the filler component density of the surface layer 31, by adjusting the filler component density of the surface layer 31, 1.5 kgf /
A bonding strength of about cm or more can be stably obtained.

【0018】また、内面層32が所要の絶縁性を備えて
いるので、表面層31のフィラー成分密度を高密度化し
ても絶縁性が損なわれることはない。上記の実施例で
は、2層構造のドライフィルムで絶縁層3が構成されて
いるが、内面層32をドライフイルムで構成し、絶縁層
形成工程(b)で内面層32を積層した後、フィラーを
高密度に分散した液状の樹脂材料3aを例えばスピンコ
ータ、ロールコータ等で内面層32の表面に塗布するよ
うに構成してもよい。また、液状の内面層32を塗布し
て乾燥させ、その表面に液状の表面層31を塗布して絶
縁層3を形成することも可能である。
Further, since the inner surface layer 32 has a required insulating property, the insulating property is not impaired even if the filler component density of the surface layer 31 is increased. Although the insulating layer 3 is composed of a dry film having a two-layer structure in the above-mentioned embodiment, the inner surface layer 32 is composed of dry film, and after the inner surface layer 32 is laminated in the insulating layer forming step (b), the filler is added. The liquid resin material 3a in which is dispersed at high density may be applied to the surface of the inner surface layer 32 by, for example, a spin coater, a roll coater, or the like. Alternatively, the liquid inner surface layer 32 may be applied and dried, and the liquid surface layer 31 may be applied to the surface thereof to form the insulating layer 3.

【0019】[0019]

【発明の効果】以上のように、本発明の多層プリント基
板用絶縁層及び多層プリント基板の製造方法は、フィラ
ー成分の密度を内面側で低くしているので、内面側の部
分で必要とされる絶縁性を確保できるとともに、フィラ
ー成分の密度を表面側で高くしているので、表面側のフ
ィラー成分を溶出させることにより入口よりも内側が拡
大している穴、入口から斜めに凹入した穴等の複雑な形
状の穴を高密度に形成することができ、後に表面に付着
される無電解メッキ層との接合強度を高めて、表面側に
形成される導体パターンとの接合強度を高めることがで
きる。その結果、絶縁性を損なうことなく、導体パター
ンの剥離を防止して、製品に対する信頼性を高めること
ができる。
As described above, the insulating layer for a multilayer printed circuit board and the method for manufacturing a multilayer printed circuit board according to the present invention make the density of the filler component low on the inner surface side, so that it is required at the inner surface side portion. Insulation properties can be secured, and the density of the filler component is increased on the surface side, so by eluting the filler component on the surface side, a hole that is wider than the inside of the inlet, it was recessed diagonally from the inlet Holes with complicated shapes such as holes can be formed at high density, and the bonding strength with the electroless plating layer that will be adhered to the surface later is increased and the bonding strength with the conductor pattern formed on the surface side is increased. be able to. As a result, peeling of the conductor pattern can be prevented and the reliability of the product can be improved without impairing the insulating property.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係る多層プリント基板の製
造方法のフロー図である。
FIG. 1 is a flow chart of a method for manufacturing a multilayer printed circuit board according to an embodiment of the present invention.

【図2】本発明の絶縁層一実施例の概念図である。FIG. 2 is a conceptual diagram of an example of an insulating layer of the present invention.

【図3】表面処理後の実施例の模式図である。FIG. 3 is a schematic view of an example after surface treatment.

【図4】積み上げ方式による従来例の製造方法のフロー
図である。
FIG. 4 is a flow chart of a conventional manufacturing method using a stacking method.

【図5】研磨による表面処理後の従来例の模式図であ
る。
FIG. 5 is a schematic view of a conventional example after surface treatment by polishing.

【図6】フィラー成分溶出による表面処理後の従来例の
模式図である。
FIG. 6 is a schematic diagram of a conventional example after surface treatment by elution of filler components.

【符号の説明】[Explanation of symbols]

1 絶縁材 2 導体パターン 3 絶縁層 3a 樹脂材料 3b フィラー成分 7 導体パターン 31 表面層 32 内面層 1 insulation 2 conductor pattern 3 insulating layers 3a Resin material 3b Filler component 7 conductor pattern 31 surface layer 32 inner layer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 湯山 仁志 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hitoshi Yuyama             1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture             Within Fujitsu Limited

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 導体パターン(2) を形成した絶縁材(1)
上に、フィラー成分(3b)を含有した感光硬化性の樹脂材
料(3a)を露光して形成した絶縁層(3) と、該絶縁層(3)
の表面に該表面のフィラー成分(3b)を除去した後に形成
した導体パターン(7) とを順次積み上げる積み上げ方式
の多層プリント基板の製造方法において、上記絶縁層
(3) として、フィラー成分(3b)の密度の低い内面層(32)
を形成した後、フィラー成分(3b)の密度が内面層(32)よ
り高い表面層(31)を形成することを特徴とするする多層
プリント基板の製造方法。
1. An insulating material (1) having a conductor pattern (2) formed thereon.
An insulating layer (3) formed by exposing a photosensitive curable resin material (3a) containing a filler component (3b) thereon, and the insulating layer (3)
In the method for manufacturing a multi-layer printed circuit board of a stacking method, the conductive pattern (7) formed after removing the filler component (3b) on the surface of the
As the (3), the inner surface layer (32) having a low density of the filler component (3b)
The method for producing a multilayer printed board, comprising: forming a surface layer (31) having a density of the filler component (3b) higher than that of the inner surface layer (32) after forming the.
【請求項2】 上記内面層(32)及び表面層(31)をドライ
フィルムまたは液状樹脂を乾燥させて形成した請求項1
に記載の多層プリント基板の製造方法。
2. The inner layer (32) and the surface layer (31) are formed by drying a dry film or a liquid resin.
A method for manufacturing the multilayer printed circuit board according to.
【請求項3】 上記フィラー成分(3b)の除去を化学的に
行う請求項1に記載の多層プリント基板の製造方法。
3. The method for producing a multilayer printed circuit board according to claim 1, wherein the removal of the filler component (3b) is performed chemically.
【請求項4】 感光硬化性及び絶縁性を有する樹脂材料
(3a)とこれを安定化させるフィラー成分(3b)とを混合し
た多層プリント基板用絶縁層において、フィラー成分(3
b)の密度を表面側で高く、内面側で低くしたことを特徴
とする多層プリント基板用絶縁層。
4. A resin material having a photo-curing property and an insulating property.
(3a) and a filler component (3b) for stabilizing it are mixed in a multilayer printed circuit board insulating layer, the filler component (3
An insulating layer for a multilayer printed circuit board, wherein the density of b) is high on the surface side and low on the inner surface side.
JP15312291A 1991-06-25 1991-06-25 Manufacture of multilayer printed board and insulating layer for multilayer printed board Withdrawn JPH053388A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15312291A JPH053388A (en) 1991-06-25 1991-06-25 Manufacture of multilayer printed board and insulating layer for multilayer printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15312291A JPH053388A (en) 1991-06-25 1991-06-25 Manufacture of multilayer printed board and insulating layer for multilayer printed board

Publications (1)

Publication Number Publication Date
JPH053388A true JPH053388A (en) 1993-01-08

Family

ID=15555460

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15312291A Withdrawn JPH053388A (en) 1991-06-25 1991-06-25 Manufacture of multilayer printed board and insulating layer for multilayer printed board

Country Status (1)

Country Link
JP (1) JPH053388A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998047329A1 (en) * 1997-04-15 1998-10-22 Ibiden Co., Ltd. Adhesive for electroless plating, feedstock composition for preparing adhesive for electroless plating, and printed wiring board
US6248428B1 (en) 1997-04-15 2001-06-19 Ibiden Co., Ltd. Adhesive for electroless plating, raw material composition for preparing adhesive for electroless plating and printed wiring board
WO2001097582A1 (en) * 2000-06-15 2001-12-20 Ajinomoto Co., Inc. Adhesive film and method for manufacturing multilayer printed wiring board comprising the same
US7390974B2 (en) 1998-02-26 2008-06-24 Ibiden Co., Ltd. Multilayer printed wiring board with filled viahole structure

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998047329A1 (en) * 1997-04-15 1998-10-22 Ibiden Co., Ltd. Adhesive for electroless plating, feedstock composition for preparing adhesive for electroless plating, and printed wiring board
US6248428B1 (en) 1997-04-15 2001-06-19 Ibiden Co., Ltd. Adhesive for electroless plating, raw material composition for preparing adhesive for electroless plating and printed wiring board
US7390974B2 (en) 1998-02-26 2008-06-24 Ibiden Co., Ltd. Multilayer printed wiring board with filled viahole structure
US7622183B2 (en) 1998-02-26 2009-11-24 Ibiden Co., Ltd. Multilayer printed wiring board with filled viahole structure
US7737366B2 (en) 1998-02-26 2010-06-15 Ibiden Co., Ltd. Multilayer printed wiring board with filled viahole structure
US8115111B2 (en) 1998-02-26 2012-02-14 Ibiden Co., Ltd. Multilayer printed wiring board with filled viahole structure
US8987603B2 (en) 1998-02-26 2015-03-24 Ibiden Co,. Ltd. Multilayer printed wiring board with filled viahole structure
WO2001097582A1 (en) * 2000-06-15 2001-12-20 Ajinomoto Co., Inc. Adhesive film and method for manufacturing multilayer printed wiring board comprising the same

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A300 Withdrawal of application because of no request for examination

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Effective date: 19980903