JPH05336077A - Pulse counter - Google Patents

Abstract

PURPOSE:To accurately count the number of pulses of two signals regardless of a relatively simple constitution. CONSTITUTION:A simultaneous output detecting part 10 detects the simultaneous occurrence of correction pulses in both of correction pulse outputs S5 and S6 to output a detection pulse. A compensation pulse generating circuit 11 generates a compensation pulse in the check bit period in accordance with the output of the detection pulse from the simusltaneous output detecting part 10. OR between correction pulse outputs S5 and S6 and a compensation pulse output S13 of the compensation pulse generating circuit 11 is operated in an OR circuit 12, and an OR output S14 of the OR circuit 12 is given to a counter 6. The counter 6 counts pulses in this output S14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse counting device for counting the number of pulses such as correction pulses output from an error correction circuit of a digital communication device.

[0002]

2. Description of the Related Art In a digital communication device, an error rate is monitored to monitor a transmission line. The error rate is monitored by counting the number of correction pulses output from the error correction decoder every time the error correction decoder performs error correction.

By the way, in the microwave radio equipment of the digital communication equipment, four-phase phase modulation (4
The PSK) method is widely applied. In this 4PSK-type microwave radio device, the transmission signal includes two systems of digital signals, and each of the two systems of digital signals is subjected to error correction. However, only one 4PS containing two digital signals is transmitted.
Since it is a K signal, the error rate in such a system is
The error rates of the two systems of digital signals must be calculated in total.

FIG. 5 is a block diagram showing a conventional structure of a 4PSK type microwave radio apparatus. The incoming microwave is frequency-converted by the receiving unit 1 and then 4PSK demodulated by the demodulating unit 2 to obtain two systems of digital signals S1.
Converted to S2. The digital signals S1 and S2 are corrected for code errors in error correction decoders 3 and 4, respectively, and output signals S3 and S4 are obtained. Digital signal S
1 and S2 form, for example, an error correction code having a format as shown in FIG. 6, and the error correction decoders 3 and 4 detect / correct a code error in the information bit portion based on the data in the check bit portion.

The error correction decoders 3 and 4 output correction pulses as correction pulse outputs S5 and S6 each time a code error is corrected. The OR circuit 5 ORs the correction pulse outputs S5 and S6 of the error correction decoders 3 and 4 into one signal, and the counter 6 counts the number of correction pulses. Output as output S7

However, with such a configuration, when a code error occurs simultaneously in the digital signals S1 and S2 and a correction pulse occurs simultaneously in both the correction pulse outputs S5 and S6, one output is output from the OR circuit 5. Since only pulses appear, the counter 6 counts as one code error. Therefore, the counted number of errors is different from the actual number of errors.

In order to solve this point, as shown in FIG. 7, correction pulse outputs S5 and S6 of error correction decoders 3 and 4, respectively.
Can be counted by the counters 7 and 8, respectively, and the count values of the counters 7 and 8 can be added by the adder circuit 9 to obtain the error number output S7.

According to this configuration, the correction pulse output S5
Even if correction pulses occur in both S6 at the same time, they can be counted separately and the number of errors can be accurately counted. However, since this configuration requires two counters and an adder circuit, the configuration becomes complicated and the circuit scale becomes large.

[0009]

As described above, the prior art is as follows.
When counting the number of pulses of the two signals, the logical sum output of the two signals is counted, so that if pulses occur simultaneously in the two signals, the count value becomes incorrect.

In order to solve this point, if the number of pulses of two signals is counted separately and the sum of the two count values is calculated, the configuration becomes complicated and the circuit scale becomes large.

The present invention has been made in view of such circumstances, and an object thereof is to provide a pulse which can accurately count the number of pulses of two signals with a relatively simple structure. It is to provide a counting device.

[0012]

According to the present invention, there is provided a simultaneous pulse detecting means, such as a simultaneous output detecting section, for detecting the simultaneous occurrence of pulses in both of the two signals to be monitored. A pulse, such as a compensation pulse generating circuit, which generates a pulse in a period in which no pulse is generated in both of the two monitored signals in response to the detection of the simultaneous pulse generation in the two monitored signals. And a logical sum calculating means such as an OR circuit for calculating a logical sum of the pulse generated by the pulse generating means and the two monitored signals.
For example, the number of pulses in the output signal of the logical sum calculation means is counted by a counting means such as a counter.

[0013]

By taking such a measure, when pulses are simultaneously generated in both of the two signals to be monitored, two
Simultaneous pulse detection means that a pulse is simultaneously generated in both of the two monitoring target signals after one pulse obtained by calculating the logical sum of two pulses by the logical sum calculation means is given to the counting means. The pulse detected by the means and correspondingly generated by the pulse generating means during the period in which no pulse is generated in both of the two monitored signals is given to the counting means and counted.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a 4PSK type microwave radio apparatus configured by applying the pulse counting apparatus according to this embodiment. The same parts as those in FIG. 5 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the figure, 10 is a simultaneous output detection circuit. The simultaneous output detection circuit 10 detects that correction pulses are simultaneously generated in the correction pulse outputs S5 and S6 output from the error correction decoders 3 and 4. Simultaneous output detection circuit 10
When it is detected that the correction pulse is simultaneously generated in the correction pulse outputs S5 and S6, the detection pulse is output as the detection output S10.

Reference numeral 11 is a compensation pulse generating circuit. The compensating pulse generating circuit 11 includes a clock signal S11 and a timing pulse S11 supplied from a control unit (not shown).
The same number of compensation pulses as the detection pulses output from the simultaneous output detection circuit 10 are generated at a predetermined timing based on 12. Compensation pulse output S13 including this compensation pulse
Is input to the OR circuit 12. In addition to the compensation pulse output S13, the OR circuit 12 also includes correction pulse outputs S5 and S.
6 are input respectively, and the logical sum of these signals is taken. The OR output S14 of the OR circuit 12 is the counter 6
Entered in. The clock signal S11 is a signal synchronized with the digital signals S3 and S4. Further, the timing pulse S12 is at "L" level during a period (information bit period) in which the information bit portion of the error correction code format shown in FIG. 6 is input to the error correction decoders 3 and 4.
It is a signal that is at "H" level during the period (check bit period) during which the check bit portion is being input to the error correction decoders 3 and 4.

FIG. 2 is a diagram showing a specific configuration of the simultaneous output detection circuit 10 and the compensation pulse generation circuit 11. As shown in this figure, the simultaneous output detection circuit 10 includes an AND circuit 10
The correction pulse outputs S5 and S6 are input to the two input terminals of the AND circuit 101.
The output of the AND circuit 101 becomes the detection pulse output S10.

On the other hand, the compensation pulse generating circuit 11 is AND
Circuits 111 and 112, NOR circuit 113, shift register 114, inverter circuit 115, and AND circuit 11
It consists of 6.

The AND circuit 111 receives the detection pulse output S10 and the clock signal S11 of the simultaneous output detection circuit 10 (AND circuit 101), and the detection pulse output S10 is used as a gate signal to turn on / off the output of the clock signal S11. Turn off. A clock signal S11 and a timing pulse S12 are input to the AND circuit 112, and the timing pulse S12 is used as a gate signal to turn on / off the output of the clock signal S11. AND
The output signal S21 of the circuit 111 and the output signal S22 of the AND circuit 111 are input to the NOR circuit 113, respectively. The NOR circuit 113 takes the NOR logic of the output signals S21 and S22. The output signal of the NOR circuit 113 is input to the clock input terminal CIN of the shift register 114.

The timing pulse S12 is inputted to the inverter circuit 115, and the timing pulse S12 is inputted.
Reverse the logic of. The output signal S24 of the inverter circuit 115 is the data input terminal DI of the shift register 114.
Input to N. The shift register 114 has a predetermined number of stages, takes in the input signal to the data input terminal DIN in synchronization with the input signal to the clock input terminal CIN, and sequentially transfers each stage. Note that the number of stages of the shift register 114 is m ≦ l ≦ n (however, where l is the number of stages of the shift register 114, m is the maximum number of code errors generated for one error correction code, and n is the check bit length). , M <n). In this embodiment, m = 2
It is assumed that n = 16 and the number of stages of the shift register 114 is eight.

Output signal S25 of shift register 114
Is input to the AND circuit 116. AND circuit 116
Has one inverting input type input terminal, and the clock signal S11 is input to the inverting input type input terminal. The AND circuit 116 inverts the logic of the clock signal S11 using the output signal S25 of the shift register 114 as a gate signal and outputs the clock signal S11. The output signal of the AND circuit 116 is output as the compensation pulse output S13.

Next, the operation of counting the number of errors in the microwave radio apparatus configured as described above will be described. First,
If correction pulses are generated at the correction pulse outputs S5 and S6 of the error correction decoders 3 and 4 at different timings, the correction pulses appear at the OR output S14 of the OR circuit 12 as they are. Therefore, the counter 6 sets the count value n to n + 1. In this state, the correction pulse outputs S5 and S6
Since at least one of them is at the “L” level, the output signal (detection pulse output) S10 of the AND circuit 101 of the simultaneous output detection circuit 10 is at the “L” level, and the compensation pulse generation circuit 11 Does not work.

Now, as shown in FIG. 3, when a code error occurs between the bit indicated by a of the digital signal S5 and the bit indicated by b of the digital signal S6, the correction pulse output S
The correction pulses P1 and P2 are simultaneously generated in both S5 and S6.

As a result, first, a pulse P3 is generated at the OR output S14 of the OR circuit 12, and the counter 6 sets the count value n to n + 1. Therefore, the error count output S7 is stepped from n to n + 1.

On the other hand, the correction pulse outputs S5 and S
When a correction pulse is generated in both 6 simultaneously, both inputs of the AND circuit 101 of the simultaneous output detection circuit 10 become "H" level, and the output signal becomes "H" level during the period in which the correction pulse is generated. Become. That is, the simultaneous output detection circuit 10 detects that the correction pulse is simultaneously generated in both the correction pulse outputs S5 and S6, and outputs the detection pulse P4 as the detection pulse output S10 as shown in FIG. Detection pulse P4 from the simultaneous output detection circuit 10
Is output, the compensation pulse generating circuit 11 operates as follows.

That is, first, the AND circuit 111 is opened during the period when the detection pulse P4 is generated, and the clock signal S
11 is output as the output signal S21. If the code errors are not continuous, the pulse widths of the correction pulses P1 and P2 and the detection pulse P4 correspond to one cycle of the clock signal S11, and thus the output signal S21 of the AND circuit 111.
½ of the detection pulse P4 as shown in FIG.
A pulse P11 having a pulse width of

At this time, since the digital signals S1 and S2 input to the error correction decoders 3 and 4 are the information bit portion, the timing pulse S12 is at "L" level. Therefore, the AND circuit 112 is closed, and the output signal S22 of the AND circuit 112 is at "L" level. Thus, the output signal S23 of the NOR gate 23 is
As shown in FIG. 4, it is a signal obtained by inverting the logic of the output signal S21 of the AND circuit 111, and this signal is supplied to the clock input terminal CIN of the shift register 114.

The shift register 114 takes in the input signal to the data input terminal DIN at the rising timing of the input signal to the clock input terminal CIN. The data input terminal DIN of the shift register 114 has a signal S24 obtained by inverting the timing pulse S12 by the inverter circuit 115.
Has been input, so NOR at the time T1 in FIG.
“H” is taken into the shift register 114 in synchronization with the rising edge of the output signal S23 of the gate 23.

After that, when the digital signals S1 and S2 input to the error correction decoders 3 and 4 become the check bit portion and the timing pulse S12 becomes the "H" level, the AND circuit 112 opens and is shown in FIG. Thus, the clock signal S11 is output as the output signal S22 of the AND circuit 112.

When the digital signals S1 and S2 input to the error correction decoders 3 and 4 are the check bit portion, no correction pulse is output from the error correction decoders 3 and 4. Therefore, the detection pulse is not output from the simultaneous output detection circuit 10, the AND circuit 111 is closed, and the output signal S21 of the AND circuit 111 is at the “L” level. Thus, the output signal S23 of the NOR gate 23 is a signal obtained by inverting the logic of the output signal S22 of the AND circuit 112 as shown in FIG. 4, and this signal is supplied to the clock input terminal CIN of the shift register 114. ..

In this state, the shift register 114 transfers the signal. The timing pulse S
Since 12 is at the “H” level, the inverter circuit 115
The output signal S24 of is at "L" level, and "L" is sequentially taken into the shift register 114. Then, when the period of eight cycles of the clock signal S11 elapses from the time T2 when the timing pulse S12 changes to the “H” level, the “H” captured during the period when the timing pulse S12 is the “L” level shifts. It reaches the final stage of 114 and appears in the output signal S25 of the shift register 114 as a pulse P12 as shown in FIG. Since the number of stages of the shift register 114 is equal to or less than the check bit length, the pulse P12 is always when the timing pulse S12 is at the "H" level, that is, the digital signals S1 and S2 input to the error correction decoders 3 and 4.
Occurs when is the check bit part.

The pulse P12 thus generated is ANDed.
In the circuit 116, a pulse P13 whose pulse width is halved is formed as shown in FIG. This pulse P13 is a compensation pulse.

When the compensation pulse P13 is generated in the compensation pulse output S13 of the compensation pulse generating circuit 11 in this way,
As shown in FIG. 3, a pulse P is output to the logical sum output of the OR circuit 12.
5 results. In response to this, the counter 6 increments the count value +
1 Therefore, the error count output S7 is incremented to n + 2.

In one error correction code, 2
When a correction pulse is simultaneously generated in both the correction pulse outputs S5 and S6, the compensation pulse generating circuit 11 captures "H" twice in the shift register 114 while the timing pulse S12 is at "L" level. Thus, two pulses are generated in the output signal S25 of the shift register 114 during the period when the timing pulse S12 is at "H" level.
Therefore, the compensating pulse generator circuit 11 outputs two compensating pulses.
Is output, and the count value of the counter is incremented by +2.

As described above, according to this embodiment, when the correction pulses are simultaneously generated in both the correction pulse outputs S5 and S6, the compensation pulse generating circuit 11 generates the number of compensation pulses corresponding to the number of the correction pulses. However, since it is given to the counter 6, it is possible to count the correction pulse which could not be directly counted. Since the compensation pulse is output during the check bit period in which no correction pulse is generated in the correction pulse outputs S5 and S6, the compensation pulse does not overlap the correction pulse. Thus, the counter 6 can accurately count the number of correction pulses, and the accurate error number output S7 can be obtained.

Further, in the present embodiment, it is only necessary to add the simultaneous output detection circuit 10 and the compensation pulse generation circuit 11 which can be simply constructed by some basic logic circuits and shift registers, as in the conventional configuration shown in FIG. This can be realized by a very simple circuit as compared with the case where two counters and an adder circuit are provided.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the pulse counting device according to the present invention is applied to the microwave radio device of the 4PSK system to count the correction pulses, but the signal to be monitored may be arbitrary, and therefore it is applied. The device to be used is not limited to the 4PSK type microwave radio device.

In the above embodiment, the compensating pulse is generated during the check bit period, but it may be generated during that period by detecting the absence of the correction pulse during the information bit period. The specific configurations of the simultaneous output detection circuit 10 and the compensation pulse generation circuit 11 are not limited to those described in the above embodiment. In addition, various modifications can be made without departing from the scope of the present invention.

[0040]

According to the present invention, a simultaneous pulse detecting means such as a simultaneous output detecting section for detecting the simultaneous occurrence of a pulse in both of the two signals to be monitored, and the simultaneous pulse detecting means are used to detect the two signals. In response to the detection of simultaneous pulse generation in both signals to be monitored,
A pulse generating means such as a compensation pulse generating circuit for generating a pulse during a period in which no pulse is generated in both of the two monitored signals, and a logical sum of the pulse generated by the pulse generating means and the two monitored signals. For example, a logical sum calculation means such as an OR circuit is provided, and the number of pulses in the output signal of the logical sum calculation means is counted by a counting means such as a counter. The pulse counting device can accurately count the pulse numbers of the two signals.

[Brief description of drawings]

FIG. 1 is a 4PSK-type microwave radio apparatus configured by applying a pulse counter according to an embodiment of the present invention.

2 is a diagram showing a specific configuration of a simultaneous output detection circuit 10 and a compensation pulse generation circuit 11 in FIG.

3 is a time chart showing the timing of each signal in FIG.

4 is a time chart showing the timing of each signal in FIG.

FIG. 5 is a diagram illustrating a conventional technique.

FIG. 6 is a diagram illustrating a conventional technique.

FIG. 7 is a diagram illustrating a conventional technique.

[Explanation of symbols]

3, 4 ... Error correction decoder, 6 ... Counter, 10 ... Simultaneous output detection circuit, 11 ... Compensation pulse generation circuit, 12 ... OR circuit.

Claims (1)

[Claims] 1. A pulse counting device for counting the number of pulses in two monitored signals, a simultaneous pulse detecting means for detecting simultaneous generation of pulses in both of the two monitored signals, and the simultaneous pulse detection. Pulse generation means for generating a pulse in a period in which no pulse is generated in both of the two monitored signals in response to the detection of simultaneous pulse generation in both of the two monitored signals by the means, A logical sum calculating means for calculating a logical sum of the pulse generated by the pulse generating means and the two monitored signals; and a counting means for counting the number of pulses in the output signal of the logical sum calculating means. Characteristic pulse counting device.