JPH05335300A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH05335300A
JPH05335300A JP15889092A JP15889092A JPH05335300A JP H05335300 A JPH05335300 A JP H05335300A JP 15889092 A JP15889092 A JP 15889092A JP 15889092 A JP15889092 A JP 15889092A JP H05335300 A JPH05335300 A JP H05335300A
Authority
JP
Japan
Prior art keywords
insulating film
film
semiconductor
semiconductor device
protective film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15889092A
Other languages
Japanese (ja)
Inventor
Genzo Kadoma
玄三 門間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP15889092A priority Critical patent/JPH05335300A/en
Publication of JPH05335300A publication Critical patent/JPH05335300A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To eliminate the deterioration of film characteristics and device characteristics owing to moisture absorption of an applied insulating film in a semiconductor device wherein the applied insulating film is formed on a underlying primary coat and a semiconductor protective film is formed on the applied insulating film by coating an exposed end of the applied insulating film with the semiconductor protective film CONSTITUTION:A device isolating thick oxide film 2 is formed on a semiconductor substrate. Then, an insulating film 3 is deposited on the thick oxide film 2. Then, an interlayer insulating film 4 is formed holding an applied insulating film 5 therebetween. Thereafter, a semiconductor protective film 6 is formed, oversized, from a scribe line 7 so as to cover a scribe section formed before the formation of the semiconductor protective film Hereby, the scribe cross section from which the applied insulating film 5 is exposed is coated with the semiconductor protective film 6 to interrupt moisture absorption by the applied insulating film 5 and hence eliminate capacitance variations.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に係り、特
に、多層配線を有する半導体装置のように下地面に凹凸
等を生じ、塗布絶縁膜を形成して平坦化を行う半導体装
置に好適に用いられるものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, it is suitable for a semiconductor device such as a semiconductor device having a multi-layer wiring, in which unevenness is formed on a base surface and a coating insulating film is formed for planarization. Is used for.

【0002】[0002]

【従来の技術】従来、金属配線が多層構造に形成される
半導体装置において、下地面を平坦化するために塗布絶
縁膜を使用したものがある。
2. Description of the Related Art Conventionally, there is a semiconductor device in which a metal wiring is formed in a multi-layered structure, in which a coating insulating film is used to flatten a base surface.

【0003】図5、図6、及び図7はかかる半導体装置
の構成を示す部分断面図である。図5〜図7において、
1は半導体基板、2は素子分離用の厚い酸化膜、3は厚
い酸化膜2上に形成されるBPSG膜等の絶縁膜、4は
層間絶縁膜、5は塗布絶縁膜膜、6は半導体保護膜、7
はスクライブラインである。なお、図5は絶縁膜3上に
塗布絶縁膜5を設けた場合、図6は層間絶縁膜4内に塗
布絶縁膜を設けた場合、図7は層間絶縁膜4上に塗布絶
縁膜を設けた場合を示すものである。図5〜図7に示さ
れるように、半導体装置のスクライブ端面には、BPS
G膜等の絶縁膜3、層間絶縁膜4、塗布絶縁膜5、半導
体保護膜6が露出している。
5, 6, and 7 are partial cross-sectional views showing the structure of such a semiconductor device. 5 to 7,
1 is a semiconductor substrate, 2 is a thick oxide film for element isolation, 3 is an insulating film such as a BPSG film formed on the thick oxide film 4, 4 is an interlayer insulating film, 5 is a coating insulating film, 6 is semiconductor protection Membrane, 7
Is a scribe line. 5 shows the case where the coating insulating film 5 is provided on the insulating film 3, FIG. 6 shows the case where the coating insulating film is provided in the interlayer insulating film 4, and FIG. 7 shows the case where the coating insulating film is provided on the interlayer insulating film 4. It shows the case. As shown in FIGS. 5 to 7, BPS is formed on the scribe end surface of the semiconductor device.
The insulating film 3 such as a G film, the interlayer insulating film 4, the coating insulating film 5, and the semiconductor protective film 6 are exposed.

【0004】ここで使用される塗布絶縁膜5は、平坦化
に用いられるもので、非常に吸湿性が高く、液体絶縁膜
塗布後に十分に焼成しても、空気中に放置した場合、空
気中の水分の吸収により、膜特性の劣化、さらには、素
子特性の劣化が生じることもある。
The coating insulating film 5 used here is used for flattening, has a very high hygroscopic property, and even if it is sufficiently baked after coating the liquid insulating film, it is left in the air when left in the air. Due to the absorption of water, the film characteristics may be deteriorated and further the element characteristics may be deteriorated.

【0005】[0005]

【発明が解決しようとしている課題】上記従来の半導体
装置においては、スクライブ端面の塗布絶縁膜が空気中
に露出しているため、上記の塗布絶縁膜の性質により、
以下に示す問題点が生じていた。 (1)塗布絶縁膜の吸湿性が高いため、塗布絶縁膜上部
と下部にある金属を電極とするコンデンサーの容量が塗
布絶縁膜の水分吸収のため変動する。このため、素子の
高速性能が著しく劣化する。 (2)塗布絶縁膜の吸湿性が高いため、第1の配線と第
2の配線(層間絶縁膜及び塗布絶縁膜を介して設けられ
る)とをつなぐビアホール形成パターニング時に、塗布
絶縁膜より水分が放出し、ビアホール内に存在する第1
の配線上に高抵抗層が形成され、第1の配線と第2の配
線とのオーミックコンタクトが、まったくとれなくな
る。
In the above conventional semiconductor device, since the coating insulating film on the scribe end face is exposed in the air, the above-mentioned properties of the coating insulating film cause
The following problems have occurred. (1) Since the coated insulating film has a high hygroscopic property, the capacitance of the capacitors having metal electrodes above and below the coated insulating film varies due to absorption of water by the coated insulating film. Therefore, the high speed performance of the device is significantly deteriorated. (2) Since the coating insulating film has a high hygroscopic property, moisture is not absorbed from the coating insulating film at the time of patterning forming a via hole that connects the first wiring and the second wiring (provided via the interlayer insulating film and the coating insulating film). 1st which is emitted and exists in the via hole
A high-resistance layer is formed on the wiring, and ohmic contact between the first wiring and the second wiring cannot be made at all.

【0006】本発明は、上記塗布絶縁膜の吸湿による膜
特性、素子特性の劣化を排除することができる半導体装
置を提供することにある。
It is an object of the present invention to provide a semiconductor device capable of eliminating the deterioration of film characteristics and element characteristics due to moisture absorption of the coated insulating film.

【0007】[0007]

【課題を解決するための手段】本発明は、下地面上に塗
布絶縁膜を形成し、この塗布絶縁膜上に半導体保護膜を
形成した半導体装置において、前記塗布絶縁膜の露出端
部を前記半導体保護膜で被覆したことを特徴とする。
According to the present invention, in a semiconductor device in which a coating insulating film is formed on a base surface and a semiconductor protective film is formed on the coating insulating film, the exposed end portion of the coating insulating film is It is characterized by being covered with a semiconductor protective film.

【0008】ここで、塗布絶縁膜とは、液状溶液を塗
布、焼成することによって形成される無機質の絶縁膜を
いい、例えば、Siを用いた半導体素子製造プロセスに
おいては、シラノール等を有機溶剤に溶解させた溶液
を、塗布、焼成することで形成されるSiO2 膜が挙げ
られる。また塗布絶縁膜上に半導体保護膜を形成すると
は、塗布絶縁膜上に直接半導体保護膜を形成する場合の
他、層間絶縁層、配線層等の層を介して塗布絶縁膜上に
半導体保護膜を形成する場合を含むものとする。
Here, the coated insulating film is an inorganic insulating film formed by coating and baking a liquid solution. For example, in a semiconductor element manufacturing process using Si, silanol or the like is used as an organic solvent. An example is a SiO 2 film formed by applying and baking a dissolved solution. Forming the semiconductor protective film on the coated insulating film means not only the case where the semiconductor protective film is directly formed on the coated insulating film, but also the semiconductor protective film formed on the coated insulating film through a layer such as an interlayer insulating layer or a wiring layer. Including the case of forming.

【0009】[0009]

【作用】本発明は、塗布絶縁膜が露出している端部(例
えば、スクライブ端面)を半導体保護膜により被覆し、
塗布絶縁膜の吸湿経路を遮断することにより、素子特性
の劣化を抑えるものである。
According to the present invention, an end portion (for example, a scribe end surface) where the coated insulating film is exposed is covered with a semiconductor protective film,
By blocking the moisture absorption path of the coating insulating film, deterioration of element characteristics is suppressed.

【0010】なお、本発明においては、半導体保護膜の
段差被覆性を向上させるため、絶縁膜上に層間絶縁膜を
形成し、且つ前記塗布絶縁膜を該層間絶縁膜の上部又は
下部又はその内部に形成する場合に、該層間絶縁膜又は
/及び該絶縁膜をスクライブラインよりもアンダーサイ
ズで形成することがのぞましい。
In the present invention, in order to improve the step coverage of the semiconductor protective film, an interlayer insulating film is formed on the insulating film, and the coating insulating film is formed on the upper or lower part of the interlayer insulating film or inside thereof. In the case of forming the film, it is preferable that the interlayer insulating film and / or the insulating film is formed undersize than the scribe line.

【0011】また、本発明においては、半導体保護膜の
段差被覆性を向上させるため、半導体保護膜をスクライ
ブラインよりもオーバーサイズで形成することがのぞま
しい。
In addition, in the present invention, in order to improve the step coverage of the semiconductor protective film, it is desirable to form the semiconductor protective film in an oversize rather than the scribe line.

【0012】[0012]

【実施例】以下、本発明の実施例について図面を用いて
詳細に説明する。
Embodiments of the present invention will be described in detail below with reference to the drawings.

【0013】図1は本発明の半導体装置の第1実施例の
部分断面図である。図1に示すように、半導体基板1に
素子分離用の厚い酸化膜2を形成する。このとき、半導
体基板1上のchipとchipを分離するスクライブ
ラインは、図中の7で規定される。本実施例では、厚い
酸化膜2の膜厚は、4000〜8000Å程度である。
厚い酸化膜2の上に不図示の第1の電極直下に形成され
る絶縁膜3を堆積する。この絶縁膜3は、BPSG膜で
あり、膜厚は、4000〜8000Åを堆積した。次に
層間絶縁膜4を塗布絶縁膜5をはさみ込む形で形成し
た。なお、本発明は図5、図7に示した層間絶縁膜4の
下又は上に塗布絶縁膜5を形成する場合にも用いること
ができることは勿論である。
FIG. 1 is a partial sectional view of a first embodiment of a semiconductor device of the present invention. As shown in FIG. 1, a thick oxide film 2 for element isolation is formed on a semiconductor substrate 1. At this time, the scribe line separating the chip and the chip on the semiconductor substrate 1 is defined by 7 in the figure. In this embodiment, the thickness of the thick oxide film 2 is about 4000 to 8000Å.
An insulating film 3 formed directly under the first electrode (not shown) is deposited on the thick oxide film 2. This insulating film 3 was a BPSG film, and the film thickness was deposited from 4000 to 8000Å. Next, the interlayer insulating film 4 was formed by sandwiching the coating insulating film 5. It is needless to say that the present invention can be used in the case where the coating insulating film 5 is formed below or above the interlayer insulating film 4 shown in FIGS.

【0014】塗布絶縁膜5下の層間絶縁膜4の膜厚は3
000〜6000Å、塗布絶縁膜5の厚さは1000〜
3000Å、塗布絶縁膜5上の層間絶縁膜4は3000
〜6000Å形成した。この後、半導体保護膜6を、半
導体保護膜形成前までに形成されたスクライブ端面を被
覆するように形成する。本実施例においては、スクライ
ブライン7から半導体保護膜6をオーバーサイズ1〜8
μmで形成した。半導体保護膜6のスクライブラインか
らのオーバーサイズの距離(図中、d)は、スクライブ
ライン7からダイシングライン8までの距離(図中、
L)よりも十分短かくなるように設定される。また、こ
のとき半導体保護膜6には、P−SiN膜を6000〜
12000Å程度堆積した。
The thickness of the interlayer insulating film 4 below the coating insulating film 5 is 3
000-6000Å, the thickness of the coating insulating film 5 is 1000-
3000Å, the interlayer insulating film 4 on the coating insulating film 5 is 3000
~ 6000Å formed. After that, the semiconductor protective film 6 is formed so as to cover the scribe end face formed before the semiconductor protective film is formed. In the present embodiment, the semiconductor protective film 6 is oversized from the scribe line 7 to the oversizes 1 to 8.
μm. The oversize distance (d in the figure) from the scribe line of the semiconductor protective film 6 is the distance from the scribe line 7 to the dicing line 8 (in the figure,
It is set to be sufficiently shorter than L). At this time, a P-SiN film 6000 to the semiconductor protective film 6 is used.
About 12,000Å was deposited.

【0015】このとき、スクライブ端面を半導体保護膜
6で被覆したものと、被覆してないものとで、層間絶縁
膜4+塗布絶縁膜5の容量変動がどれくらい生じるかを
示したものが図2である。図2に示すように、層間絶縁
膜4+塗布絶縁膜5のスクライブ端面を半導体保護膜6
で被覆しない場合(図2中、白丸)には、湿度85%、
気温85℃の雰囲気中に110hr程度放置した時に、
30%程度の容量増加が観察される。
At this time, FIG. 2 shows how the capacitance variation of the interlayer insulating film 4 + the coated insulating film 5 occurs depending on whether the scribe end surface is covered with the semiconductor protective film 6 or not. is there. As shown in FIG. 2, the scribe end surface of the interlayer insulating film 4 + the coating insulating film 5 is covered with the semiconductor protective film 6
If not covered (white circle in Fig. 2), the humidity is 85%,
When left for 110 hours in an atmosphere with a temperature of 85 ° C,
A capacity increase of around 30% is observed.

【0016】一方、スクライブ端面を半導体保護膜6で
被覆した場合には、ほとんど容量変動が生じていない
(図2中、黒丸)。したがって図1のように、塗布絶縁
膜5が露出しているスクライブ端面を、半導体保護膜6
で被覆することにより、塗布絶縁膜の吸湿を遮断するこ
とができ、図2に示すような、ICの特性を左右させる
容量変動を排除することが可能となった。
On the other hand, when the scribe end face is covered with the semiconductor protective film 6, there is almost no capacitance variation (black circle in FIG. 2). Therefore, as shown in FIG. 1, the scribe end surface where the coating insulating film 5 is exposed is covered with the semiconductor protective film 6
By coating with, it is possible to block the moisture absorption of the coated insulating film, and it becomes possible to eliminate the capacitance fluctuation that influences the characteristics of the IC as shown in FIG.

【0017】次に本発明の半導体装置の第2実施例につ
いて、図3を用いて説明する。
Next, a second embodiment of the semiconductor device of the present invention will be described with reference to FIG.

【0018】図3は本発明の半導体装置の第2実施例の
部分断面図である。なお、図1と同一構成部材について
は同一符号を付して説明を省略する。
FIG. 3 is a partial sectional view of a second embodiment of the semiconductor device of the present invention. The same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

【0019】同図に示すように、本実施例においては、
スクライブ端面を半導体保護膜6で被覆するとき、その
半導体保護膜6のステップカバレージ(段差被覆性)を
さらに良くするために、不図示の第1の配線と第2の配
線(層間絶縁膜及び塗布絶縁膜を介して設けられる)を
つなぐビアホール形成パターニング時に、ビアホール形
成用マスクのスクライブラインを通常のスクライブライ
ンよりもアンダーサイズに形成した。さらに半導体保護
膜6の一部をPadの開口のために、パターニングする
時に、マスクのスクライブラインを通常のスクライブラ
インよりもオーバーサイズに形成した。これにより、半
導体保護膜6がスクライブ端面を被覆するステップカバ
レージが、さらに向上した。このとき、ビアホール形成
用マスクのアンダーサイズ量は、1〜8μmであり、半
導体保護膜6のPad開口用マスクのオーバーサイズ量
は、1〜8μmとした。本実施例においても、第1の実
施例と同様に容量変動を抑えることが可能となった。
As shown in the figure, in this embodiment,
When the scribe end face is covered with the semiconductor protective film 6, in order to further improve the step coverage (step coverage) of the semiconductor protective film 6, a first wiring and a second wiring (interlayer insulating film and coating) not shown are provided. The scribe line of the mask for forming a via hole is formed to be undersized than the normal scribe line during the patterning of forming a via hole for connecting (providing via an insulating film). Further, when patterning a part of the semiconductor protective film 6 for the pad opening, the scribe line of the mask was formed to be oversized as compared with the normal scribe line. As a result, the step coverage with which the semiconductor protective film 6 covers the scribe end surface is further improved. At this time, the undersize amount of the via hole forming mask was 1 to 8 μm, and the oversize amount of the pad opening mask of the semiconductor protective film 6 was 1 to 8 μm. Also in the present embodiment, it is possible to suppress the capacity fluctuation as in the first embodiment.

【0020】次に本発明の半導体装置の第3の実施例に
ついて、図4を用いて説明する。
Next, a third embodiment of the semiconductor device of the present invention will be described with reference to FIG.

【0021】図4は本発明の半導体装置の第3実施例の
部分断面図である。なお、図1と同一構成部材について
は同一符号を付して説明を省略する。
FIG. 4 is a partial sectional view of a third embodiment of the semiconductor device of the present invention. The same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

【0022】本実施例の場合も上記第2実施例と同様
に、半導体保護膜6のスクライブ付近でのステップカバ
レージを向上させるために実施したものである。図4に
示すように本実施例では、コンタクトホール穴あけ用の
マスクをスクライブライン7からdCNT 分アンダーサイ
ズに形成し、さらにビアホール形成用マスクをスクライ
ブラインからdvia 分アンダーサイズに形成した。この
とき、dCNT とdvia の関係は、dCNT <dvia であ
り、ここでは1μm<dCNT <6μm、2μm<dvia
<8μmとした。これにより、スクライブラインパター
ンを変えずに、半導体保護膜6のステップカバレージを
向上させることができた。また、本実施例の場合も、第
1の実施例と同様に、容量変動は、ほとんど観察されな
かった。
Also in the case of this embodiment, like the second embodiment, it is carried out to improve the step coverage in the vicinity of the scribe of the semiconductor protective film 6. As shown in FIG. 4, in this example, a mask for forming a contact hole was formed under the size of d CNT from the scribe line 7, and a mask for forming a via hole was formed under the size of d via from the scribe line. At this time, the relationship between d CNT and d via is d CNT <d via , and here 1 μm <d CNT <6 μm, 2 μm <d via
<8 μm. As a result, the step coverage of the semiconductor protective film 6 could be improved without changing the scribe line pattern. Also, in the case of this example, as in the first example, almost no capacity fluctuation was observed.

【0023】以上説明したように、露出するスクライブ
端面を、半導体保護膜で被覆する構造をとれば、容量変
動、およびビアホールの高抵抗化が排除できる。
As described above, by adopting a structure in which the exposed scribe end surface is covered with the semiconductor protective film, it is possible to eliminate capacitance variation and increase in resistance of the via hole.

【0024】なお本実施例では、半導体保護膜にP−S
iN、P−SiO、PSG、ポリイミドなどの有機膜を
使用し、層間絶縁膜には、P−SiO、PSG、NSG
等を使用することができる。いずれの場合にも、上記し
た半導体素子特性が得られた。
In this embodiment, the semiconductor protective film is made of PS.
An organic film such as iN, P-SiO, PSG, or polyimide is used, and P-SiO, PSG, NSG is used as the interlayer insulating film.
Etc. can be used. In any case, the above semiconductor device characteristics were obtained.

【0025】[0025]

【発明の効果】以上詳細に説明したように、本発明によ
れば、 (1)塗布絶縁膜が露出するスクライブ端面を半導体保
護膜で被覆することにより、塗布絶縁膜の水分の吸収を
完全に排除することができ、第1の配線と第2の配線
(層間絶縁膜及び塗布絶縁膜を介して設けられる)を電
極とするコンデンサーの容量増加を完全に阻止すること
ができる。これにより、半導体素子の応答速度の劣化を
完全に阻止できる効果がある。 (2)塗布絶縁膜が露出するスクライブ端面を、半導体
保護膜で被覆することにより、ビアホール形成パターニ
ング時、第1の配線上に高抵抗層がまったく形成されな
くなり、半導体素子の歩留りが向上する効果がある。 (3)塗布絶縁膜が露出するスクライブ端面を半導体保
護膜で被覆することにより、塗布絶縁膜からの水分の吸
収を完全に排除することが可能となり、半導体素子の信
頼性が向上する効果がある。
As described above in detail, according to the present invention, (1) by covering the scribe end surface where the coated insulating film is exposed with a semiconductor protective film, the absorption of moisture by the coated insulating film is completely completed. It can be eliminated, and it is possible to completely prevent an increase in capacitance of the capacitor having the first wiring and the second wiring (provided via the interlayer insulating film and the coating insulating film) as electrodes. This has the effect of completely preventing the deterioration of the response speed of the semiconductor element. (2) By covering the scribe end surface where the coated insulating film is exposed with the semiconductor protective film, the high resistance layer is not formed on the first wiring at all during the via hole formation patterning, and the yield of the semiconductor element is improved. There is. (3) By covering the scribe end surface where the coating insulating film is exposed with a semiconductor protective film, it is possible to completely eliminate the absorption of moisture from the coating insulating film, and there is an effect that the reliability of the semiconductor element is improved. ..

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置の第1実施例のスクライブ
付近の部分断面図である。
FIG. 1 is a partial cross-sectional view near a scribe of a first embodiment of a semiconductor device of the present invention.

【図2】本発明を実施した半導体装置と従来の半導体装
置の容量変動を表わす特性図である。
FIG. 2 is a characteristic diagram showing a capacitance variation between a semiconductor device implementing the present invention and a conventional semiconductor device.

【図3】本発明の半導体装置の第2実施例のスクライブ
付近の部分断面図である。
FIG. 3 is a partial cross-sectional view near a scribe of a second embodiment of the semiconductor device of the present invention.

【図4】本発明の半導体装置の第3実施例のスクライブ
付近の部分断面図である。
FIG. 4 is a partial cross-sectional view near a scribe of a third embodiment of the semiconductor device of the present invention.

【図5】従来の半導体装置のスクライブ付近の断面図で
ある。
FIG. 5 is a cross-sectional view of a conventional semiconductor device near a scribe.

【図6】従来の半導体装置のスクライブ付近の断面図で
ある。
FIG. 6 is a cross-sectional view of a conventional semiconductor device near a scribe.

【図7】従来の半導体装置のスクライブ付近の断面図で
ある。
FIG. 7 is a cross-sectional view of a conventional semiconductor device near a scribe.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 厚いシリコン酸化膜 3 BPSG膜 4 層間絶縁膜 5 塗布絶縁膜 6 半導体保護膜 7 スクライブライン 8 ダイシングライン 1 semiconductor substrate 2 thick silicon oxide film 3 BPSG film 4 interlayer insulating film 5 coating insulating film 6 semiconductor protective film 7 scribe line 8 dicing line

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 下地面上に塗布絶縁膜を形成し、この塗
布絶縁膜上に半導体保護膜を形成した半導体装置におい
て、 前記塗布絶縁膜の露出端部を前記半導体保護膜で被覆し
たことを特徴とする半導体装置。
1. A semiconductor device in which a coating insulating film is formed on a lower ground and a semiconductor protective film is formed on the coating insulating film, wherein an exposed end portion of the coating insulating film is covered with the semiconductor protective film. Characteristic semiconductor device.
【請求項2】 請求項1記載の半導体装置において、前
記塗布絶縁膜の露出端部がスクライブ端面にあり、この
スクライブ端面を前記半導体保護膜で被覆したことを特
徴とする半導体装置。
2. The semiconductor device according to claim 1, wherein an exposed end portion of the coating insulating film is a scribe end surface, and the scribe end surface is covered with the semiconductor protective film.
【請求項3】 請求項2記載の半導体装置において、前
記半導体保護膜を、スクライブラインよりもオーバーサ
イズで形成したことを特徴とする半導体装置。
3. The semiconductor device according to claim 2, wherein the semiconductor protective film is formed to be oversized as compared with a scribe line.
【請求項4】 請求項2記載の半導体装置において、絶
縁膜上に層間絶縁膜を形成し、且つ前記塗布絶縁膜を該
層間絶縁膜の上部又は下部又はその内部に形成するとと
もに、該絶縁膜又は該層間絶縁膜を、スクライブライン
よりもアンダーサイズで形成したことを特徴とする半導
体装置。
4. The semiconductor device according to claim 2, wherein an interlayer insulating film is formed on the insulating film, and the coating insulating film is formed on or under the interlayer insulating film or inside the insulating film. Alternatively, the semiconductor device is characterized in that the interlayer insulating film is formed undersize than the scribe line.
【請求項5】 請求項2記載の半導体装置において、絶
縁膜上に層間絶縁膜を形成し、且つ前記塗布絶縁膜を該
層間絶縁膜の上部又は下部又はその内部に形成するとと
もに、該絶縁膜及び該層間絶縁膜を、スクライブライン
よりもアンダーサイズで形成したことを特徴とする半導
体装置。
5. The semiconductor device according to claim 2, wherein an interlayer insulating film is formed on the insulating film, and the coating insulating film is formed on or under the interlayer insulating film or inside the insulating film. And a semiconductor device in which the interlayer insulating film is formed undersize than the scribe line.
【請求項6】 請求項3記載の半導体装置において、前
記半導体保護膜のスクライブラインからのオーバーサイ
ズの距離が、スクライブラインからダイシングラインま
での距離よりも十分短かいことを特徴とする半導体装
置。
6. The semiconductor device according to claim 3, wherein an oversize distance of the semiconductor protective film from a scribe line is sufficiently shorter than a distance from the scribe line to the dicing line.
JP15889092A 1992-05-27 1992-05-27 Semiconductor device Pending JPH05335300A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15889092A JPH05335300A (en) 1992-05-27 1992-05-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15889092A JPH05335300A (en) 1992-05-27 1992-05-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05335300A true JPH05335300A (en) 1993-12-17

Family

ID=15681621

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15889092A Pending JPH05335300A (en) 1992-05-27 1992-05-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05335300A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6242337B1 (en) 1997-10-08 2001-06-05 Nec Corporation Semiconductor device and method of manufacturing the same
JP2013030819A (en) * 2012-11-09 2013-02-07 Fujitsu Semiconductor Ltd Semiconductor device and method of manufacturing the same
US8937007B2 (en) 2007-03-30 2015-01-20 Fujitsu Semiconductor Limited Semiconductor device
WO2024079780A1 (en) * 2022-10-11 2024-04-18 三菱電機株式会社 Semiconductor wafer, semiconductor device, power conversion device, and cooling system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6242337B1 (en) 1997-10-08 2001-06-05 Nec Corporation Semiconductor device and method of manufacturing the same
US8937007B2 (en) 2007-03-30 2015-01-20 Fujitsu Semiconductor Limited Semiconductor device
JP2013030819A (en) * 2012-11-09 2013-02-07 Fujitsu Semiconductor Ltd Semiconductor device and method of manufacturing the same
WO2024079780A1 (en) * 2022-10-11 2024-04-18 三菱電機株式会社 Semiconductor wafer, semiconductor device, power conversion device, and cooling system

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