JPH0533413B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] An information processing device in which a system is started up in an initial setting mode and an operation mode, in which information transfer between a central processing unit and a memory device during startup in the information processing device is performed. In order to solve the problem that the bus control method is complicated and takes a long time for system diagnosis because it is performed using the same method as the operating mode, the information transfer method and route on the bus is changed in the initial setting mode. By controlling the timing and route to be different from those in the operation mode, more reliable information can be transferred efficiently and quickly.

[Industrial application field]

The present invention relates to an information processing apparatus that starts up an information processing system in an initial setting mode and an operation mode.

The central processing unit (hereinafter referred to as CPU) and memory device, which are the main devices that make up an information processing device, are:
There are very close connections, and data transfer between them is required to be at high speed and in large quantities.

However, in the field of small computers and office computers where manufacturing costs are important, it is generally necessary to reduce the amount of hardware as much as possible, so the hardware for information transfer and information transfer control is small and simple. something is required.

Furthermore, recently there has been a function that allows the CPU to grasp the address allocation status and total memory capacity of multiple memory cards, which are the storage elements that make up a memory device.
Prior to operation of the memory device, the CPU performs an initial diagnosis of the memory device, and if there is a defective memory card in the memory device, that memory card is logically separated and addresses are assigned to only the remaining memory cards to operate. Increasingly, there are many devices that have a function called .

There is a demand for the practical implementation of an information transfer system that can reliably meet the above requirements and functions at high speed.

[Conventional technology]

FIG. 4 is a block diagram illustrating a conventional example, and FIG. 5 is a diagram illustrating a bus during information transfer in the conventional example.

The block diagram of the conventional example shown in FIG. 4 gives instructions and commands to the functional blocks that make up the information processing system and controls various operations.
It is composed of a CPU 1 and a memory device 2 which is made up of a plurality of memory cards 21 to 23 and stores various information under the control of the CPU 1.

In addition, the CPU 1 of this example has a microprocessor (hereinafter referred to as MPU) 11 that controls the exchange of information with the memory device 2 based on a predetermined program, and a microprocessor (hereinafter referred to as MPU) 11 that controls the exchange of information with the memory device 2 based on a predetermined program. An address conversion unit 12 that converts data into data; a data transfer control unit 13 that controls data transfer between the MPU 11 and the memory device 2; and a bidirectional bus driver that exchanges address information between the MPU 11 and the address conversion unit 12. 14
1, and a bidirectional bus driver 14 that exchanges data information between the MPU 11 and the data transfer control unit 13.
2, bidirectional bus drivers 143 and 144 that exchange address data and data information between the data transfer control unit 13 and the memory device 2, and a unidirectional bus driver 151 that sends address data from the address conversion unit 12. It is configured with the following.

Furthermore, the memory cards 21 to 23 in the memory device 2 are composed of the same functional blocks, and the structure includes a memory module 221 which is the storage element of the memory cards 21 to 23, and a memory module 221 that stores address data transferred from the CPU 1. An address latch unit 222 that latches, an allocation address register 223 that is one of the control registers for the memory module 221 and that presets address allocation data for the memory module 221, and address data held in the address latch unit 222. A comparator 224(1) compares the contents of the address assigned to the assigned address register 223 with the address data held in the address latch section 222 and the card address of the memory card 21 to 23. The comparator 224(2) and a portion of the address data held in the address latch unit 222 are decoded and stored in a plurality of memory control information registers (assigned address register 222).
3. an address decoder 225 that converts the card information register 228, etc.) into selection information; a bidirectional bus driver 226 (1) that exchanges address data and data information transferred from the CPU 1; A unidirectional bus driver 227 that sends out contents; and a card information register 228 that is one of the control registers for the memory module 221 and stores information regarding the memory cards 21 to 23.
and a card address register 229 that stores address information of the memory cards 21 to 23.

Information is exchanged between the CPU 1 and the memory device 2 configured as described above, including address information configured as shown in FIG. 5(1) and address information configured as shown in FIG. 5(2). data information is transferred at time-sharing timing.

The example in Figure 5(1) consists of 32-bit address information, 4-bit parity bits, and 4-bit unused part, and the example in Figure 5(2) consists of 32-bit data information. , and 8 ECC bits.

Next, the information transfer operation will be explained by dividing it into a plurality of processing items.

[1] In the read operation of the information stored in the memory module 221, the address information output from the MPU 11 is converted into address data corresponding to the number of memory cards 21 to 23 in the memory device 2 by the address converter 12. Convert, unidirectional bus driver 151, bidirectional bus driver 144
and bidirectional bus driver 2 in memory card 22
26(1) to the address latch section 22.

Next, the memory card 22 address latch section 2
The upper part of the address data held in 2,
The contents of the allocation address for the memory module 221 set in the allocation address register 223 are compared by the comparator 224, and when they match, the contents of the allocation address for the memory module 221 in the memory card 22 are compared.
21 is selected.

Further, the data in the memory module 221 stored in the lower part of the address data held in the address latch section 22 is read out and sent to the MPU 11 via the path to the data transfer control section 13.

[2] When writing information to the memory module 221, the address from the MPU 11 is latched in the address latch section 222 in the memory card 22 in the same way as above.

When the upper part of the address data held in the address latch section 222 and the content of the allocated address set in the allocated address register 223 match in the comparator 224, the memory module 221 in the memory card 22 is selected in the same way as above. be done.

Next, the write data output from the MPU 11 is sent to the memory module 221 in the memory card 22 under the control of the data transfer control section 13, and is written to the lower part of the address data held in the address latch section 22. Ru.

[3] Memory control information register (i.e., allocation address register 223, card information register 228) in the initial setting mode of the memory device 2
etc.), the address output from the MPU 11 is latched by the address latch unit 222 via the address conversion unit 12.

A comparator 224(2) compares predetermined three bits of the address held in the address latch section 222 with the contents of the card address register 229 indicating the address of the memory card 22.

If there is a match in this comparison, the remaining address in the address latch section 222 is transferred to the address decoder 2.
25, and one of the memory control information registers in the memory card 22 (for example, card information register 228) is selected.

Next, the contents of one of the selected memory control information registers are transferred via the data transfer control unit 13.
Read into MPU11.

[4] When writing to the memory control information register in the initial setting mode of the memory device 2,
The address output from the MPU 11 is sent to one of the memory control information registers (for example, allocated address register 22) via the same route as in [3].
Select 3).

Next, the write data output from the MPU 11 is transferred to the previously selected address register 2 under the control of the data transfer control unit 13.
23.

As explained above, in the conventional example shown in FIG. 4, the CPU 1 and the memory are The control method of the bidirectional bus connecting the devices 2 is common, and all operations are performed via the bus controlled by time-sharing timing.

However, the following problems arose in this case. That is, (1) Depending on the type (difference in access time) of the memory element (memory module 221) mounted on the memory cards 21 to 23,
1 to 23 must be operated at the best timing.

That is, in the latest technology, the CPU 1 reads the card information of the memory cards 21 to 23 (for example, the capacity, type, etc. of the memory element mounted on the memory cards 21 to 23), and according to that information, the CPU 1 reads the card information of the memory cards 21 to 23 (for example, the capacity, type, etc. 23 is written into a timing setting register (one of the memory control information registers, for example, the allocation address register 223).

Memory element (memory module 221) before the value is set in this timing setting register
read/write timing (e.g. RAS
timing, CAS timing, write enable timing, etc.) are in an undefined state and cannot be used as read/write timing for the memory control information register.

(2) As described above, in the operating mode of the memory device 2, address information is sent using all bits of the bus in the first half cycle, and data information is transferred using all bits in the second half cycle as well.

This method is optimal because the memory element (memory module 221) itself has a large address space and a large data width.

However, the allocation address register 223 and card information register 2 in the memory initial setting mode
When reading/writing memory control information registers such as 28, the number of memory control information registers is not large, and the data width thereof is smaller than that of the memory element (memory module 221).

Therefore, the memory element (memory module 22
If a bus is used in common with 1) read/write, there will be considerable waste.

(3) The data information to the memory element (memory module 221) is ECC as shown in Figure 5.2.
However, since there are no so-called soft errors in the information in the memory control information register, there is no need to add complicated check bits.

Therefore, the information read from the memory control information register is treated like the data read from the memory element (memory module 221).
There is no need to pass through an ECC circuit (included in the data transfer control unit 13 and not shown).

Furthermore, writing/reading information to/from the memory control information register is performed as part of system diagnosis, and should be performed prior to diagnosis of the data transfer control section 13 including the ECC circuit.

[Problem that the invention seeks to solve]

As described above, the conventional bidirectional bus control method shown in Fig. 4 is inefficient in its use.
There are problems such as diagnosis of the memory device 2, which has a closer relationship with the CPU 1, through the data transfer control unit 13, which is not sufficiently diagnosed.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the principle of the invention.

The principle block diagram of the present invention shown in FIG. 1 is composed of a CPU 10 and a memory device 20 having the same functions as those explained in FIG.

Further, the CPU 10 of the present invention includes the functional blocks 11, 12, 141, 144, 155 explained in FIG.
Then, it generates the bus control timing for the newly defined initial setting mode command and the bus control timing for the operation mode command, and controls the bus driver in the CPU 1 (bidirectional bus driver 145, etc.) and the bus driver in the memory device 2. (Bidirectional bus driver 226
(1), 226(2), etc.) at respective timings, and a bidirectional bus driver 145.

Furthermore, the memory device 20 of the present invention is comprised of memory cards 21' to 23', which will be explained below. That is, the functional block 221 explained in FIG.
~223,224(1),226(1),227,228
and a bidirectional bus driver 226(2) connected in parallel to the bidirectional bus driver 226(1) to the memory module 221.

[Effect]

By configuring the memory initialization mode so that address information transfer and data information transfer on the bus are controlled in non-time-sharing timing using specific parts, bus bits are not wasted in each transfer of address information and data information. This enables more efficient and faster transfer control.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram illustrating an embodiment of the present invention, and FIG. 3 is a diagram illustrating an information transfer situation in the embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The information in the initial setting mode in this embodiment is as follows:
Bit configuration information as shown in FIG. 3(1) is transferred at non-time division timing. Also, the operation mode is shown in Figure 3.
The information shown in (2) and (3) is transferred in time-sharing timing.

Control of this non-time division timing and time division timing is controlled by the timing control unit 14 in response to an initial setting mode command and an operation mode command sent from the MPU 11.

Note that FIG. 3 (2) and (3) have the same contents as FIG. 5 (1) and (2), and the information shown in FIG. 3 (1) is the allocation address register 223, card information register 228, etc. 13-bit register addresses for memory control information registers such as
Consists of 3-bit card address for 3'
16-bit address information and memory module 2
It consists of 16-bit data information for 21 and an 8-bit unused portion.

Further, the bidirectional bus drivers 226(1) and 226(2) in the memory cards 21' to 23' are controlled by the timing control section 14 so that both directions are switched at the same timing in the operation mode.

On the other hand, in the initial setting mode, the direction of the bidirectional bus driver 226(1) is switched by writing and reading information to the memory control information register, but the direction of the bidirectional bus driver 226(2) is always changed from the CPU 1 to the memory device. 2 (ie, memory card 22'), only address information is transferred.

Next, the information transfer processing status in this embodiment will be explained below. Note that the operations described in the [Prior Art] section and the operations in [1] and [2] are the same, so the explanation will be omitted for [3] and [4].

[3] The command issued by the MPU 11 when reading the memory control information register in the memory initialization mode is the same command as the command to read the register in the address translation unit 12.

The address information output from the MPU 11 is sent to the address conversion unit 12 and the unidirectional bus driver 151.
A predetermined three bits of the data are compared with the card address of the memory card 22' by the comparator 224(2).

If there is a match in this comparison, the remaining part is converted by the address decoder 225, one of the memory control information registers (for example, card information register 228) in the memory card 22' is selected, and its contents are transferred to the bidirectional bus driver. 145,
Transferred via the address conversion unit 12, the MPU
11.

[4] When writing memory control information registers in memory initialization mode, one of the memory control information registers (for example, allocation address register 2)
23) is selected.

Next, the write data output from the MPU 11 is written to the allocated address register 223 via the bidirectional bus driver 141, address conversion unit 12, bidirectional bus driver 145, and bidirectional bus driver 226(1).

As described above, in the initial setting mode of the memory device 2, the bus is controlled using non-time division timing that does not require complicated timing, so initial diagnosis of the system can be performed at high speed with less hardware.

In addition, in the operation mode after the initial settings are completed, address information transfer and data information transfer are controlled in a time-sharing manner using a limited number of buses as shown in Fig. 3, 2 and 3. Efficient bus control becomes possible.

〔Effect of the invention〕

According to the present invention as described above, address information,
No bus bits are wasted in transferring each piece of data information, allowing more efficient and faster transfer control.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the principle of the present invention.
FIG. 2 is a block diagram explaining an embodiment of the present invention;
FIG. 3 is a diagram for explaining the information transfer situation in the embodiment of the present invention, FIG. 4 is a block diagram for explaining the conventional example, and FIG. 5 is a diagram for explaining the bus during information transfer in the conventional example. . In the figure, 1 and 10 are CPUs, 2 and 20 are memory devices, 11 is an MPU, 12 is an address conversion unit,
13 is a data transfer control section, 14 is a timing control section, 21 to 23, 21' to 23' are memory cards,
141 to 145, 226(1), 226(2) are bidirectional bus drivers, 151, 227 are unidirectional bus drivers, 221 is a memory module, 222 is an address latch section, 223 is an assigned address register,
224(1) and 224(2) are comparators, 225 is an AS decoder, 228 is a card information register, and 229 is a card address register, respectively.

Claims (1)

[Scope of Claims] 1. The central processing unit 10 is configured by connecting a central processing unit 10 and a memory device 20 via a bidirectional bus, and further controls the startup of an information processing system.
Each control register 223, 2 in the memory device 20
28 and an operation mode after the control registers 223 and 228 are initialized and the memory device 20 becomes operational, the information processing device comprising: When controlling the processing setting mode, a division control means 14 controls the timing of dividing the bidirectional bus into a plurality of bit groups; and the control register 22 in the initial setting mode.
3,228 read/write data transfer path 1
45, 226(1), 226(2), and the control register 22 in the initial setting mode.
A predetermined command for instructing the transfer of 3,228 read/write data is defined, and when controlling the initial setting mode by generation of the predetermined command, a plurality of pieces of information for the control registers 223 and 228 are transferred to the division control means 14. An information processing device, characterized in that: a bidirectional bus is controlled and transferred at non-time-sharing timing, and when the operation mode is controlled, the plurality of pieces of information are controlled and transferred using the bi-directional bus at time-sharing timing.